FSConfig.py revision 10780
110780SCurtis.Dunham@arm.com# Copyright (c) 2010-2012, 2015 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 422934Sktlim@umich.edufrom m5.objects import * 432995Ssaidi@eecs.umich.edufrom Benchmarks import * 4410046Snilay@cs.wisc.edufrom m5.util import * 452934Sktlim@umich.edu 4610747SChris.Emmons@arm.com# Populate to reflect supported os types per target ISA 4710747SChris.Emmons@arm.comos_types = { 'alpha' : [ 'linux' ], 4810747SChris.Emmons@arm.com 'mips' : [ 'linux' ], 4910747SChris.Emmons@arm.com 'sparc' : [ 'linux' ], 5010747SChris.Emmons@arm.com 'x86' : [ 'linux' ], 5110747SChris.Emmons@arm.com 'arm' : [ 'linux', 5210747SChris.Emmons@arm.com 'android-gingerbread', 5310747SChris.Emmons@arm.com 'android-ics', 5410747SChris.Emmons@arm.com 'android-jellybean', 5510747SChris.Emmons@arm.com 'android-kitkat' ], 5610747SChris.Emmons@arm.com } 5710747SChris.Emmons@arm.com 582934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 592934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 602934Sktlim@umich.edu read_only=False) 612934Sktlim@umich.edu 622934Sktlim@umich.edu def childImage(self, ci): 632934Sktlim@umich.edu self.image.child.image_file = ci 642934Sktlim@umich.edu 6510720Sandreas.hansson@arm.comclass MemBus(SystemXBar): 666122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 676122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 686122SSteve.Reinhardt@amd.com 6910594Sgabeblack@google.comdef fillInCmdline(mdesc, template, **kwargs): 7010594Sgabeblack@google.com kwargs.setdefault('disk', mdesc.disk()) 7110697SCurtis.Dunham@arm.com kwargs.setdefault('rootdev', mdesc.rootdev()) 7210594Sgabeblack@google.com kwargs.setdefault('mem', mdesc.mem()) 7310594Sgabeblack@google.com kwargs.setdefault('script', mdesc.script()) 7410594Sgabeblack@google.com return template % kwargs 7510594Sgabeblack@google.com 7610594Sgabeblack@google.comdef makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): 7710118Snilay@cs.wisc.edu 784520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 794982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 804520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 814520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 822934Sktlim@umich.edu 832934Sktlim@umich.edu self = LinuxAlphaSystem() 843005Sstever@eecs.umich.edu if not mdesc: 853005Sstever@eecs.umich.edu # generic system 863304Sstever@eecs.umich.edu mdesc = SysConfig() 872995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 8810118Snilay@cs.wisc.edu 8910118Snilay@cs.wisc.edu self.tsunami = BaseTsunami() 9010118Snilay@cs.wisc.edu 9110118Snilay@cs.wisc.edu # Create the io bus to connect all device ports 9210720Sandreas.hansson@arm.com self.iobus = IOXBar() 9310118Snilay@cs.wisc.edu self.tsunami.attachIO(self.iobus) 9410118Snilay@cs.wisc.edu 9510118Snilay@cs.wisc.edu self.tsunami.ide.pio = self.iobus.master 9610118Snilay@cs.wisc.edu self.tsunami.ide.config = self.iobus.master 9710118Snilay@cs.wisc.edu 9810118Snilay@cs.wisc.edu self.tsunami.ethernet.pio = self.iobus.master 9910118Snilay@cs.wisc.edu self.tsunami.ethernet.config = self.iobus.master 10010118Snilay@cs.wisc.edu 10110118Snilay@cs.wisc.edu if ruby: 10210118Snilay@cs.wisc.edu # Store the dma devices for later connection to dma ruby ports. 10310118Snilay@cs.wisc.edu # Append an underscore to dma_ports to avoid the SimObjectVector check. 10410118Snilay@cs.wisc.edu self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 10510118Snilay@cs.wisc.edu else: 10610118Snilay@cs.wisc.edu self.membus = MemBus() 10710118Snilay@cs.wisc.edu 10810118Snilay@cs.wisc.edu # By default the bridge responds to all addresses above the I/O 10910118Snilay@cs.wisc.edu # base address (including the PCI config space) 11010118Snilay@cs.wisc.edu IO_address_space_base = 0x80000000000 11110118Snilay@cs.wisc.edu self.bridge = Bridge(delay='50ns', 1128713Sandreas.hansson@arm.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 11310118Snilay@cs.wisc.edu self.bridge.master = self.iobus.slave 11410118Snilay@cs.wisc.edu self.bridge.slave = self.membus.master 11510118Snilay@cs.wisc.edu 11610118Snilay@cs.wisc.edu self.tsunami.ide.dma = self.iobus.slave 11710118Snilay@cs.wisc.edu self.tsunami.ethernet.dma = self.iobus.slave 11810118Snilay@cs.wisc.edu 11910118Snilay@cs.wisc.edu self.system_port = self.membus.slave 12010118Snilay@cs.wisc.edu 1219826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 1222934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 1232934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 1242995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 1252934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1266765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1276765SBrad.Beckmann@amd.com read_only = True)) 1286765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1296765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1306765SBrad.Beckmann@amd.com self.terminal = Terminal() 1316765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1326765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1336765SBrad.Beckmann@amd.com self.console = binary('console') 13410594Sgabeblack@google.com if not cmdline: 13510594Sgabeblack@google.com cmdline = 'root=/dev/hda1 console=ttyS0' 13610594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 1376765SBrad.Beckmann@amd.com 1386765SBrad.Beckmann@amd.com return self 1396765SBrad.Beckmann@amd.com 14010588Sgabeblack@google.comdef makeSparcSystem(mem_mode, mdesc=None): 1418713Sandreas.hansson@arm.com # Constants from iob.cc and uart8250.cc 1428713Sandreas.hansson@arm.com iob_man_addr = 0x9800000000 1438713Sandreas.hansson@arm.com uart_pio_size = 8 1448713Sandreas.hansson@arm.com 1454486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1464486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1474486Sbinkertn@umich.edu read_only=False) 1484486Sbinkertn@umich.edu 1494486Sbinkertn@umich.edu def childImage(self, ci): 1504486Sbinkertn@umich.edu self.image.child.image_file = ci 1514486Sbinkertn@umich.edu 1523584Ssaidi@eecs.umich.edu self = SparcSystem() 1533584Ssaidi@eecs.umich.edu if not mdesc: 1543584Ssaidi@eecs.umich.edu # generic system 1553584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1563584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 15710720Sandreas.hansson@arm.com self.iobus = IOXBar() 1589036Sandreas.hansson@arm.com self.membus = MemBus() 1599164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 1603743Sgblack@eecs.umich.edu self.t1000 = T1000() 1614104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1623743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1639826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 1649826Sandreas.hansson@arm.com AddrRange(Addr('2GB'), size ='256MB')] 1658839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 1668839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 1678839Sandreas.hansson@arm.com self.rom.port = self.membus.master 1688839Sandreas.hansson@arm.com self.nvram.port = self.membus.master 1698839Sandreas.hansson@arm.com self.hypervisor_desc.port = self.membus.master 1708839Sandreas.hansson@arm.com self.partition_desc.port = self.membus.master 1713584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1723898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1733898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1748839Sandreas.hansson@arm.com self.disk0.pio = self.iobus.master 1758713Sandreas.hansson@arm.com 1768713Sandreas.hansson@arm.com # The puart0 and hvuart are placed on the IO bus, so create ranges 1778713Sandreas.hansson@arm.com # for them. The remaining IO range is rather fragmented, so poke 1788713Sandreas.hansson@arm.com # holes for the iob and partition descriptors etc. 1798713Sandreas.hansson@arm.com self.bridge.ranges = \ 1808713Sandreas.hansson@arm.com [ 1818713Sandreas.hansson@arm.com AddrRange(self.t1000.puart0.pio_addr, 1828713Sandreas.hansson@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 1838713Sandreas.hansson@arm.com AddrRange(self.disk0.pio_addr, 1848713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_addr + 1858713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_size - 1), 1868713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 1878713Sandreas.hansson@arm.com iob_man_addr - 1), 1888713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_l2_1.pio_addr, 1898713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_addr + 1908713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_size - 1), 1918713Sandreas.hansson@arm.com AddrRange(self.t1000.hvuart.pio_addr, 1928713Sandreas.hansson@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 1938713Sandreas.hansson@arm.com ] 1944103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1954103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1964103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1973745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 1983745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 1993745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 2003584Ssaidi@eecs.umich.edu 2018839Sandreas.hansson@arm.com self.system_port = self.membus.slave 2028706Sandreas.hansson@arm.com 2033584Ssaidi@eecs.umich.edu return self 2043584Ssaidi@eecs.umich.edu 20510588Sgabeblack@google.comdef makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, 20610780SCurtis.Dunham@arm.com dtb_filename=None, bare_metal=False, cmdline=None, 20710780SCurtis.Dunham@arm.com external_memory=""): 2088061SAli.Saidi@ARM.com assert machine_type 2098061SAli.Saidi@ARM.com 2107586SAli.Saidi@arm.com if bare_metal: 2117586SAli.Saidi@arm.com self = ArmSystem() 2127586SAli.Saidi@arm.com else: 2137586SAli.Saidi@arm.com self = LinuxArmSystem() 2147586SAli.Saidi@arm.com 2157586SAli.Saidi@arm.com if not mdesc: 2167586SAli.Saidi@arm.com # generic system 2177586SAli.Saidi@arm.com mdesc = SysConfig() 2187586SAli.Saidi@arm.com 2197586SAli.Saidi@arm.com self.readfile = mdesc.script() 22010720Sandreas.hansson@arm.com self.iobus = IOXBar() 2219036Sandreas.hansson@arm.com self.membus = MemBus() 2227586SAli.Saidi@arm.com self.membus.badaddr_responder.warn_access = "warn" 2239164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 2248839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 2258839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 2267586SAli.Saidi@arm.com 2277586SAli.Saidi@arm.com self.mem_mode = mem_mode 2287586SAli.Saidi@arm.com 2297586SAli.Saidi@arm.com if machine_type == "RealView_PBX": 2307586SAli.Saidi@arm.com self.realview = RealViewPBX() 2317586SAli.Saidi@arm.com elif machine_type == "RealView_EB": 2327586SAli.Saidi@arm.com self.realview = RealViewEB() 2338870SAli.Saidi@ARM.com elif machine_type == "VExpress_EMM": 2348870SAli.Saidi@ARM.com self.realview = VExpress_EMM() 23510512SAli.Saidi@ARM.com if not dtb_filename: 23610512SAli.Saidi@ARM.com dtb_filename = 'vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb' % num_cpus 23710037SARM gem5 Developers elif machine_type == "VExpress_EMM64": 23810037SARM gem5 Developers self.realview = VExpress_EMM64() 23910512SAli.Saidi@ARM.com if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 24010512SAli.Saidi@ARM.com print "Selected 64-bit ARM architecture, updating default disk image..." 24110512SAli.Saidi@ARM.com mdesc.diskname = 'linaro-minimal-aarch64.img' 24210512SAli.Saidi@ARM.com if not dtb_filename: 24310512SAli.Saidi@ARM.com dtb_filename = 'vexpress.aarch64.20140821.dtb' 2447586SAli.Saidi@arm.com else: 2457586SAli.Saidi@arm.com print "Unknown Machine Type" 2467586SAli.Saidi@arm.com sys.exit(1) 2477586SAli.Saidi@arm.com 2488528SAli.Saidi@ARM.com self.cf0 = CowIdeDisk(driveID='master') 2498528SAli.Saidi@ARM.com self.cf0.childImage(mdesc.disk()) 25010353SGeoffrey.Blake@arm.com 25110353SGeoffrey.Blake@arm.com # Attach any PCI devices this platform supports 25210353SGeoffrey.Blake@arm.com self.realview.attachPciDevices() 2538528SAli.Saidi@ARM.com # default to an IDE controller rather than a CF one 25410357SAli.Saidi@ARM.com try: 25510357SAli.Saidi@ARM.com self.realview.ide.disks = [self.cf0] 25610357SAli.Saidi@ARM.com except: 2578528SAli.Saidi@ARM.com self.realview.cf_ctrl.disks = [self.cf0] 2588528SAli.Saidi@ARM.com 25910507SAli.Saidi@ARM.com self.mem_ranges = [] 26010507SAli.Saidi@ARM.com size_remain = long(Addr(mdesc.mem())) 26110507SAli.Saidi@ARM.com for region in self.realview._mem_regions: 26210507SAli.Saidi@ARM.com if size_remain > long(region[1]): 26310507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=region[1])) 26410507SAli.Saidi@ARM.com size_remain = size_remain - long(region[1]) 26510507SAli.Saidi@ARM.com else: 26610507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 26710507SAli.Saidi@ARM.com size_remain = 0 26810507SAli.Saidi@ARM.com break 26910507SAli.Saidi@ARM.com warn("Memory size specified spans more than one region. Creating" \ 27010507SAli.Saidi@ARM.com " another memory controller for that range.") 27110507SAli.Saidi@ARM.com 27210507SAli.Saidi@ARM.com if size_remain > 0: 27310507SAli.Saidi@ARM.com fatal("The currently selected ARM platforms doesn't support" \ 27410507SAli.Saidi@ARM.com " the amount of DRAM you've selected. Please try" \ 27510507SAli.Saidi@ARM.com " another platform") 27610507SAli.Saidi@ARM.com 2778061SAli.Saidi@ARM.com if bare_metal: 2788061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 2798061SAli.Saidi@ARM.com self.realview.uart.end_on_eot = True 2808061SAli.Saidi@ARM.com else: 28110161Satgutier@umich.edu if machine_type == "VExpress_EMM64": 28210512SAli.Saidi@ARM.com self.kernel = binary('vmlinux.aarch64.20140821') 28310161Satgutier@umich.edu elif machine_type == "VExpress_EMM": 28410512SAli.Saidi@ARM.com self.kernel = binary('vmlinux.aarch32.ll_20131205.0-gem5') 28510161Satgutier@umich.edu else: 28610161Satgutier@umich.edu self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 28710161Satgutier@umich.edu 2889929SAli.Saidi@ARM.com if dtb_filename: 2899929SAli.Saidi@ARM.com self.dtb_filename = binary(dtb_filename) 2907586SAli.Saidi@arm.com self.machine_type = machine_type 29110071Satgutier@umich.edu # Ensure that writes to the UART actually go out early in the boot 29210594Sgabeblack@google.com if not cmdline: 29310594Sgabeblack@google.com cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 29410594Sgabeblack@google.com 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 29510697SCurtis.Dunham@arm.com 'mem=%(mem)s root=%(rootdev)s' 29610071Satgutier@umich.edu 29710780SCurtis.Dunham@arm.com # When using external memory, gem5 writes the boot loader to nvmem 29810780SCurtis.Dunham@arm.com # and then SST will read from it, but SST can only get to nvmem from 29910780SCurtis.Dunham@arm.com # iobus, as gem5's membus is only used for initialization and 30010780SCurtis.Dunham@arm.com # SST doesn't use it. Attaching nvmem to iobus solves this issue. 30110780SCurtis.Dunham@arm.com # During initialization, system_port -> membus -> iobus -> nvmem. 30210780SCurtis.Dunham@arm.com if external_memory: 30310780SCurtis.Dunham@arm.com self.realview.setupBootLoader(self.iobus, self, binary) 30410780SCurtis.Dunham@arm.com else: 30510780SCurtis.Dunham@arm.com self.realview.setupBootLoader(self.membus, self, binary) 3068528SAli.Saidi@ARM.com self.gic_cpu_addr = self.realview.gic.cpu_addr 3078528SAli.Saidi@ARM.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 3088287SAli.Saidi@ARM.com 30910747SChris.Emmons@arm.com # This check is for users who have previously put 'android' in 31010747SChris.Emmons@arm.com # the disk image filename to tell the config scripts to 31110747SChris.Emmons@arm.com # prepare the kernel with android-specific boot options. That 31210747SChris.Emmons@arm.com # behavior has been replaced with a more explicit option per 31310747SChris.Emmons@arm.com # the error message below. The disk can have any name now and 31410747SChris.Emmons@arm.com # doesn't need to include 'android' substring. 31510735Srb639@drexel.edu if (os.path.split(mdesc.disk())[-1]).lower().count('android'): 31610747SChris.Emmons@arm.com if 'android' not in mdesc.os_type(): 31710747SChris.Emmons@arm.com fatal("It looks like you are trying to boot an Android " \ 31810747SChris.Emmons@arm.com "platform. To boot Android, you must specify " \ 31910747SChris.Emmons@arm.com "--os-type with an appropriate Android release on " \ 32010747SChris.Emmons@arm.com "the command line.") 32110747SChris.Emmons@arm.com 32210747SChris.Emmons@arm.com # android-specific tweaks 32310747SChris.Emmons@arm.com if 'android' in mdesc.os_type(): 32410747SChris.Emmons@arm.com # generic tweaks 32510747SChris.Emmons@arm.com cmdline += " init=/init" 32610747SChris.Emmons@arm.com 32710747SChris.Emmons@arm.com # release-specific tweaks 32810747SChris.Emmons@arm.com if 'kitkat' in mdesc.os_type(): 32910747SChris.Emmons@arm.com cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 33010747SChris.Emmons@arm.com "android.bootanim=0" 33110747SChris.Emmons@arm.com 33210594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 33310747SChris.Emmons@arm.com 33410780SCurtis.Dunham@arm.com if external_memory: 33510780SCurtis.Dunham@arm.com # I/O traffic enters iobus 33610780SCurtis.Dunham@arm.com self.external_io = ExternalMaster(port_data="external_io", 33710780SCurtis.Dunham@arm.com port_type=external_memory) 33810780SCurtis.Dunham@arm.com self.external_io.port = self.iobus.slave 33910780SCurtis.Dunham@arm.com 34010780SCurtis.Dunham@arm.com # Ensure iocache only receives traffic destined for (actual) memory. 34110780SCurtis.Dunham@arm.com self.iocache = ExternalSlave(port_data="iocache", 34210780SCurtis.Dunham@arm.com port_type=external_memory, 34310780SCurtis.Dunham@arm.com addr_ranges=self.mem_ranges) 34410780SCurtis.Dunham@arm.com self.iocache.port = self.iobus.master 34510780SCurtis.Dunham@arm.com 34610780SCurtis.Dunham@arm.com # Let system_port get to nvmem and nothing else. 34710780SCurtis.Dunham@arm.com self.bridge.ranges = [self.realview.nvmem.range] 34810780SCurtis.Dunham@arm.com 34910780SCurtis.Dunham@arm.com self.realview.attachOnChipIO(self.iobus) 35010780SCurtis.Dunham@arm.com else: 35110780SCurtis.Dunham@arm.com self.realview.attachOnChipIO(self.membus, self.bridge) 3527586SAli.Saidi@arm.com self.realview.attachIO(self.iobus) 3537586SAli.Saidi@arm.com self.intrctrl = IntrControl() 3547586SAli.Saidi@arm.com self.terminal = Terminal() 3557949SAli.Saidi@ARM.com self.vncserver = VncServer() 3567586SAli.Saidi@arm.com 3578839Sandreas.hansson@arm.com self.system_port = self.membus.slave 3588706Sandreas.hansson@arm.com 3597586SAli.Saidi@arm.com return self 3607586SAli.Saidi@arm.com 3617586SAli.Saidi@arm.com 36210594Sgabeblack@google.comdef makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): 3635222Sksewell@umich.edu class BaseMalta(Malta): 3645222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 3655222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 3665222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 3675222Sksewell@umich.edu 3685222Sksewell@umich.edu self = LinuxMipsSystem() 3695222Sksewell@umich.edu if not mdesc: 3705222Sksewell@umich.edu # generic system 3715222Sksewell@umich.edu mdesc = SysConfig() 3725222Sksewell@umich.edu self.readfile = mdesc.script() 37310720Sandreas.hansson@arm.com self.iobus = IOXBar() 3749036Sandreas.hansson@arm.com self.membus = MemBus() 3759164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 3769826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange('1GB')] 3778839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 3788839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 3795222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 3805222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 3815222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 3825222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 3835222Sksewell@umich.edu self.malta = BaseMalta() 3845222Sksewell@umich.edu self.malta.attachIO(self.iobus) 3858839Sandreas.hansson@arm.com self.malta.ide.pio = self.iobus.master 3868839Sandreas.hansson@arm.com self.malta.ide.config = self.iobus.master 3878839Sandreas.hansson@arm.com self.malta.ide.dma = self.iobus.slave 3888839Sandreas.hansson@arm.com self.malta.ethernet.pio = self.iobus.master 3898839Sandreas.hansson@arm.com self.malta.ethernet.config = self.iobus.master 3908839Sandreas.hansson@arm.com self.malta.ethernet.dma = self.iobus.slave 3915222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 3925222Sksewell@umich.edu read_only = True)) 3935222Sksewell@umich.edu self.intrctrl = IntrControl() 3945222Sksewell@umich.edu self.mem_mode = mem_mode 3955478Snate@binkert.org self.terminal = Terminal() 3965222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 3975222Sksewell@umich.edu self.console = binary('mips/console') 39810594Sgabeblack@google.com if not cmdline: 39910594Sgabeblack@google.com cmdline = 'root=/dev/hda1 console=ttyS0' 40010594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 4015222Sksewell@umich.edu 4028839Sandreas.hansson@arm.com self.system_port = self.membus.slave 4038706Sandreas.hansson@arm.com 4045222Sksewell@umich.edu return self 4055222Sksewell@umich.edu 4065323Sgblack@eecs.umich.edudef x86IOAddress(port): 4075357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 4088323Ssteve.reinhardt@amd.com return IO_address_space_base + port 4095323Sgblack@eecs.umich.edu 4108858Sgblack@eecs.umich.edudef connectX86ClassicSystem(x86_sys, numCPUs): 4118713Sandreas.hansson@arm.com # Constants similar to x86_traits.hh 4128713Sandreas.hansson@arm.com IO_address_space_base = 0x8000000000000000 4138713Sandreas.hansson@arm.com pci_config_address_space_base = 0xc000000000000000 4148713Sandreas.hansson@arm.com interrupts_address_space_base = 0xa000000000000000 4158713Sandreas.hansson@arm.com APIC_range_size = 1 << 12; 4168713Sandreas.hansson@arm.com 4179036Sandreas.hansson@arm.com x86_sys.membus = MemBus() 4187905SBrad.Beckmann@amd.com 4197905SBrad.Beckmann@amd.com # North Bridge 42010720Sandreas.hansson@arm.com x86_sys.iobus = IOXBar() 4219164Sandreas.hansson@arm.com x86_sys.bridge = Bridge(delay='50ns') 4228839Sandreas.hansson@arm.com x86_sys.bridge.master = x86_sys.iobus.slave 4238839Sandreas.hansson@arm.com x86_sys.bridge.slave = x86_sys.membus.master 42410438Smajiuyue@ncic.ac.cn # Allow the bridge to pass through: 42510438Smajiuyue@ncic.ac.cn # 1) kernel configured PCI device memory map address: address range 42610438Smajiuyue@ncic.ac.cn # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 42710438Smajiuyue@ncic.ac.cn # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 42810438Smajiuyue@ncic.ac.cn # 3) everything in the IO address range up to the local APIC, and 42910438Smajiuyue@ncic.ac.cn # 4) then the entire PCI address space and beyond. 4308713Sandreas.hansson@arm.com x86_sys.bridge.ranges = \ 4318713Sandreas.hansson@arm.com [ 43210438Smajiuyue@ncic.ac.cn AddrRange(0xC0000000, 0xFFFF0000), 4338713Sandreas.hansson@arm.com AddrRange(IO_address_space_base, 4348713Sandreas.hansson@arm.com interrupts_address_space_base - 1), 4358713Sandreas.hansson@arm.com AddrRange(pci_config_address_space_base, 4368713Sandreas.hansson@arm.com Addr.max) 4378713Sandreas.hansson@arm.com ] 4388713Sandreas.hansson@arm.com 4398713Sandreas.hansson@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 4408713Sandreas.hansson@arm.com # the local APIC (two pages) 4419164Sandreas.hansson@arm.com x86_sys.apicbridge = Bridge(delay='50ns') 4428839Sandreas.hansson@arm.com x86_sys.apicbridge.slave = x86_sys.iobus.master 4438839Sandreas.hansson@arm.com x86_sys.apicbridge.master = x86_sys.membus.slave 4448815Sgblack@eecs.umich.edu x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 4458815Sgblack@eecs.umich.edu interrupts_address_space_base + 4468858Sgblack@eecs.umich.edu numCPUs * APIC_range_size 4478858Sgblack@eecs.umich.edu - 1)] 4487905SBrad.Beckmann@amd.com 4497905SBrad.Beckmann@amd.com # connect the io bus 4507905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 4517905SBrad.Beckmann@amd.com 4528839Sandreas.hansson@arm.com x86_sys.system_port = x86_sys.membus.slave 4538706Sandreas.hansson@arm.com 4547905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 4557905SBrad.Beckmann@amd.com # North Bridge 45610720Sandreas.hansson@arm.com x86_sys.iobus = IOXBar() 4577905SBrad.Beckmann@amd.com 4588929Snilay@cs.wisc.edu # add the ide to the list of dma devices that later need to attach to 4598929Snilay@cs.wisc.edu # dma controllers 4608929Snilay@cs.wisc.edu x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 46110118Snilay@cs.wisc.edu x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 4627905SBrad.Beckmann@amd.com 4637905SBrad.Beckmann@amd.com 46410588Sgabeblack@google.comdef makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): 4655613Sgblack@eecs.umich.edu if self == None: 4665613Sgblack@eecs.umich.edu self = X86System() 4675613Sgblack@eecs.umich.edu 4685133Sgblack@eecs.umich.edu if not mdesc: 4695133Sgblack@eecs.umich.edu # generic system 4705133Sgblack@eecs.umich.edu mdesc = SysConfig() 4715133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 4725133Sgblack@eecs.umich.edu 4736802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 4746802Sgblack@eecs.umich.edu 4755133Sgblack@eecs.umich.edu # Physical memory 47610041Snilay@cs.wisc.edu # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 47710041Snilay@cs.wisc.edu # for various devices. Hence, if the physical memory size is greater than 47810041Snilay@cs.wisc.edu # 3GB, we need to split it into two parts. 47910041Snilay@cs.wisc.edu excess_mem_size = \ 48010041Snilay@cs.wisc.edu convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 48110041Snilay@cs.wisc.edu if excess_mem_size <= 0: 48210041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange(mdesc.mem())] 48310041Snilay@cs.wisc.edu else: 48410046Snilay@cs.wisc.edu warn("Physical memory size specified is %s which is greater than " \ 48510046Snilay@cs.wisc.edu "3GB. Twice the number of memory controllers would be " \ 48610046Snilay@cs.wisc.edu "created." % (mdesc.mem())) 48710046Snilay@cs.wisc.edu 48810041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange('3GB'), 48910041Snilay@cs.wisc.edu AddrRange(Addr('4GB'), size = excess_mem_size)] 4905613Sgblack@eecs.umich.edu 4915613Sgblack@eecs.umich.edu # Platform 4925638Sgblack@eecs.umich.edu self.pc = Pc() 4937905SBrad.Beckmann@amd.com 4947905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 4957905SBrad.Beckmann@amd.com if Ruby: 4967905SBrad.Beckmann@amd.com connectX86RubySystem(self) 4977905SBrad.Beckmann@amd.com else: 4988858Sgblack@eecs.umich.edu connectX86ClassicSystem(self, numCPUs) 4995613Sgblack@eecs.umich.edu 5005613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 5015613Sgblack@eecs.umich.edu 5025841Sgblack@eecs.umich.edu # Disks 5035841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 5045841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 5055841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 5065841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 5075841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 5085841Sgblack@eecs.umich.edu 5095615Sgblack@eecs.umich.edu # Add in a Bios information structure. 5105615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 5115615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 5125615Sgblack@eecs.umich.edu 5135641Sgblack@eecs.umich.edu # Set up the Intel MP table 5148323Ssteve.reinhardt@amd.com base_entries = [] 5158323Ssteve.reinhardt@amd.com ext_entries = [] 5166135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 5176135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 5186135Sgblack@eecs.umich.edu local_apic_id = i, 5196135Sgblack@eecs.umich.edu local_apic_version = 0x14, 5206135Sgblack@eecs.umich.edu enable = True, 5216135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 5228323Ssteve.reinhardt@amd.com base_entries.append(bp) 5235644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 5246135Sgblack@eecs.umich.edu id = numCPUs, 5255644Sgblack@eecs.umich.edu version = 0x11, 5265644Sgblack@eecs.umich.edu enable = True, 5275644Sgblack@eecs.umich.edu address = 0xfec00000) 5286135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 5298323Ssteve.reinhardt@amd.com base_entries.append(io_apic) 53010437Smajiuyue@ncic.ac.cn # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 53110437Smajiuyue@ncic.ac.cn # but linux kernel cannot config PCI device if it was not connected to PCI bus, 53210437Smajiuyue@ncic.ac.cn # so we fix PCI bus id to 0, and ISA bus id to 1. 53310437Smajiuyue@ncic.ac.cn pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI') 53410437Smajiuyue@ncic.ac.cn base_entries.append(pci_bus) 53510437Smajiuyue@ncic.ac.cn isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA') 5368323Ssteve.reinhardt@amd.com base_entries.append(isa_bus) 53710437Smajiuyue@ncic.ac.cn connect_busses = X86IntelMPBusHierarchy(bus_id=1, 53810437Smajiuyue@ncic.ac.cn subtractive_decode=True, parent_bus=0) 5398323Ssteve.reinhardt@amd.com ext_entries.append(connect_busses) 5405843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 5415843Sgblack@eecs.umich.edu interrupt_type = 'INT', 5425843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 5435843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 54410437Smajiuyue@ncic.ac.cn source_bus_id = 0, 5455843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 5466044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5475843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 5488323Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 5496135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 5506135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 5516135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 5526135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 5536135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 55410437Smajiuyue@ncic.ac.cn source_bus_id = 1, 5556135Sgblack@eecs.umich.edu source_bus_irq = irq, 5566135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5576135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 5588323Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 5596135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 5606135Sgblack@eecs.umich.edu interrupt_type = 'INT', 5616135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 5626135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 56310437Smajiuyue@ncic.ac.cn source_bus_id = 1, 5646135Sgblack@eecs.umich.edu source_bus_irq = irq, 5656135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5666135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 5678323Ssteve.reinhardt@amd.com base_entries.append(assign_to_apic) 5686135Sgblack@eecs.umich.edu assignISAInt(0, 2) 5696135Sgblack@eecs.umich.edu assignISAInt(1, 1) 5706135Sgblack@eecs.umich.edu for i in range(3, 15): 5716135Sgblack@eecs.umich.edu assignISAInt(i, i) 5728323Ssteve.reinhardt@amd.com self.intel_mp_table.base_entries = base_entries 5738323Ssteve.reinhardt@amd.com self.intel_mp_table.ext_entries = ext_entries 5745641Sgblack@eecs.umich.edu 57510594Sgabeblack@google.comdef makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 57610594Sgabeblack@google.com cmdline=None): 5775613Sgblack@eecs.umich.edu self = LinuxX86System() 5785613Sgblack@eecs.umich.edu 5797905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 5809826Sandreas.hansson@arm.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 5815613Sgblack@eecs.umich.edu 5825450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 5835450Sgblack@eecs.umich.edu # just to avoid corner cases. 5849826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 5859232Sandreas.hansson@arm.com assert(phys_mem_size >= 0x200000) 58610041Snilay@cs.wisc.edu assert(len(self.mem_ranges) <= 2) 5875450Sgblack@eecs.umich.edu 58810041Snilay@cs.wisc.edu entries = \ 5898323Ssteve.reinhardt@amd.com [ 5908323Ssteve.reinhardt@amd.com # Mark the first megabyte of memory as reserved 5919622Snilay@cs.wisc.edu X86E820Entry(addr = 0, size = '639kB', range_type = 1), 5929622Snilay@cs.wisc.edu X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 59310041Snilay@cs.wisc.edu # Mark the rest of physical memory as available 5948323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0x100000, 59510041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 5969898Sandreas@sandberg.pp.se range_type = 1), 5978323Ssteve.reinhardt@amd.com ] 5985450Sgblack@eecs.umich.edu 59910438Smajiuyue@ncic.ac.cn # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 60010438Smajiuyue@ncic.ac.cn # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 60110438Smajiuyue@ncic.ac.cn # specific range can pass though bridge to iobus. 60210438Smajiuyue@ncic.ac.cn if len(self.mem_ranges) == 1: 60310438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 60410438Smajiuyue@ncic.ac.cn size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 60510438Smajiuyue@ncic.ac.cn range_type=2)) 60610438Smajiuyue@ncic.ac.cn 60710438Smajiuyue@ncic.ac.cn # Reserve the last 16kB of the 32-bit address space for the m5op interface 60810438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 60910438Smajiuyue@ncic.ac.cn 61010041Snilay@cs.wisc.edu # In case the physical memory is greater than 3GB, we split it into two 61110041Snilay@cs.wisc.edu # parts and add a separate e820 entry for the second part. This entry 61210041Snilay@cs.wisc.edu # starts at 0x100000000, which is the first address after the space 61310041Snilay@cs.wisc.edu # reserved for devices. 61410041Snilay@cs.wisc.edu if len(self.mem_ranges) == 2: 61510041Snilay@cs.wisc.edu entries.append(X86E820Entry(addr = 0x100000000, 61610041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 61710041Snilay@cs.wisc.edu 61810041Snilay@cs.wisc.edu self.e820_table.entries = entries 61910041Snilay@cs.wisc.edu 6205330Sgblack@eecs.umich.edu # Command line 62110594Sgabeblack@google.com if not cmdline: 62210594Sgabeblack@google.com cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1' 62310594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 62410003Ssteve.reinhardt@amd.com self.kernel = binary('x86_64-vmlinux-2.6.22.9') 6255133Sgblack@eecs.umich.edu return self 6265133Sgblack@eecs.umich.edu 6273584Ssaidi@eecs.umich.edu 6288801Sgblack@eecs.umich.edudef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 6298801Sgblack@eecs.umich.edu self = Root(full_system = full_system) 6302995Ssaidi@eecs.umich.edu self.testsys = testSystem 6312995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 6324981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 6334981Ssaidi@eecs.umich.edu 6348661SAli.Saidi@ARM.com if hasattr(testSystem, 'realview'): 6358661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 6368661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 6378661SAli.Saidi@ARM.com elif hasattr(testSystem, 'tsunami'): 6388661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 6398661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 6408661SAli.Saidi@ARM.com else: 6418661SAli.Saidi@ARM.com fatal("Don't know how to connect these system together") 6428661SAli.Saidi@ARM.com 6433025Ssaidi@eecs.umich.edu if dumpfile: 6443025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 6453025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 6462934Sktlim@umich.edu 6472934Sktlim@umich.edu return self 648