FSConfig.py revision 10037
12SN/A# Copyright (c) 2010-2012 ARM Limited 22190SN/A# All rights reserved. 32SN/A# 42SN/A# The license below extends only to copyright in the software and shall 52SN/A# not be construed as granting a license to any other intellectual 62SN/A# property including but not limited to intellectual property relating 72SN/A# to a hardware implementation of the functionality of the software 82SN/A# licensed hereunder. You may use the software subject to the license 92SN/A# terms below provided that you ensure that this notice is replicated 102SN/A# unmodified and in its entirety in all distributions of the software, 112SN/A# modified or unmodified, in source code or in binary form. 122SN/A# 132SN/A# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 142SN/A# Copyright (c) 2006-2008 The Regents of The University of Michigan 152SN/A# All rights reserved. 162SN/A# 172SN/A# Redistribution and use in source and binary forms, with or without 182SN/A# modification, are permitted provided that the following conditions are 192SN/A# met: redistributions of source code must retain the above copyright 202SN/A# notice, this list of conditions and the following disclaimer; 212SN/A# redistributions in binary form must reproduce the above copyright 222SN/A# notice, this list of conditions and the following disclaimer in the 232SN/A# documentation and/or other materials provided with the distribution; 242SN/A# neither the name of the copyright holders nor the names of its 252SN/A# contributors may be used to endorse or promote products derived from 262SN/A# this software without specific prior written permission. 272665SN/A# 282665SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312680Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322680Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342972Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353453Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361858SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372423SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382190SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3956SN/A# 40217SN/A# Authors: Kevin Lim 413776Sgblack@eecs.umich.edu 422036SN/Afrom m5.objects import * 432SN/Afrom Benchmarks import * 442190SN/Afrom m5.util import convert 452190SN/A 463453Sgblack@eecs.umich.educlass CowIdeDisk(IdeDisk): 473453Sgblack@eecs.umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 483453Sgblack@eecs.umich.edu read_only=False) 493453Sgblack@eecs.umich.edu 503453Sgblack@eecs.umich.edu def childImage(self, ci): 512190SN/A self.image.child.image_file = ci 522313SN/A 532235SN/Aclass MemBus(CoherentBus): 542423SN/A badaddr_responder = BadAddr() 552521SN/A default = Self.badaddr_responder.pio 562521SN/A 572190SN/A 582190SN/Adef makeLinuxAlphaSystem(mem_mode, mdesc = None): 593548Sgblack@eecs.umich.edu IO_address_space_base = 0x80000000000 603548Sgblack@eecs.umich.edu class BaseTsunami(Tsunami): 613548Sgblack@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 623548Sgblack@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 632330SN/A pci_func=0, pci_dev=0, pci_bus=0) 642SN/A 652680Sktlim@umich.edu self = LinuxAlphaSystem() 662680Sktlim@umich.edu if not mdesc: 672680Sktlim@umich.edu # generic system 682680Sktlim@umich.edu mdesc = SysConfig() 692680Sktlim@umich.edu self.readfile = mdesc.script() 702680Sktlim@umich.edu self.iobus = NoncoherentBus() 712680Sktlim@umich.edu self.membus = MemBus() 722680Sktlim@umich.edu # By default the bridge responds to all addresses above the I/O 732680Sktlim@umich.edu # base address (including the PCI config space) 742680Sktlim@umich.edu self.bridge = Bridge(delay='50ns', 752680Sktlim@umich.edu ranges = [AddrRange(IO_address_space_base, Addr.max)]) 762682Sktlim@umich.edu self.mem_ranges = [AddrRange(mdesc.mem())] 772680Sktlim@umich.edu self.bridge.master = self.iobus.slave 782680Sktlim@umich.edu self.bridge.slave = self.membus.master 792680Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 802680Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 812680Sktlim@umich.edu self.disk0.childImage(mdesc.disk()) 822SN/A self.disk2.childImage(disk('linux-bigswap2.img')) 832107SN/A self.tsunami = BaseTsunami() 842107SN/A self.tsunami.attachIO(self.iobus) 852107SN/A self.tsunami.ide.pio = self.iobus.master 862190SN/A self.tsunami.ide.config = self.iobus.master 872455SN/A self.tsunami.ide.dma = self.iobus.slave 882455SN/A self.tsunami.ethernet.pio = self.iobus.master 892107SN/A self.tsunami.ethernet.config = self.iobus.master 902159SN/A self.tsunami.ethernet.dma = self.iobus.slave 912SN/A self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 92246SN/A read_only = True)) 93246SN/A self.intrctrl = IntrControl() 94246SN/A self.mem_mode = mem_mode 95246SN/A self.terminal = Terminal() 96246SN/A self.kernel = binary('vmlinux') 97246SN/A self.pal = binary('ts_osfpal') 98246SN/A self.console = binary('console') 99246SN/A self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 100246SN/A 101246SN/A self.system_port = self.membus.slave 102246SN/A 103246SN/A return self 104246SN/A 1052190SN/Adef makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 106246SN/A class BaseTsunami(Tsunami): 107246SN/A ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 108246SN/A ide = IdeController(disks=[Parent.disk0, Parent.disk2], 109246SN/A pci_func=0, pci_dev=0, pci_bus=0) 110246SN/A self = LinuxAlphaSystem() 111246SN/A self.mem_ranges = [AddrRange(mdesc.mem())] 112246SN/A if not mdesc: 1132SN/A # generic system 1142680Sktlim@umich.edu mdesc = SysConfig() 1152423SN/A self.readfile = mdesc.script() 1162190SN/A 117180SN/A # Create pio bus to connect all device pio ports to rubymem's pio port 1182190SN/A self.piobus = NoncoherentBus() 1192190SN/A 1202190SN/A self.disk0 = CowIdeDisk(driveID='master') 1212190SN/A self.disk2 = CowIdeDisk(driveID='master') 1223453Sgblack@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 1232190SN/A self.disk2.childImage(disk('linux-bigswap2.img')) 1243453Sgblack@eecs.umich.edu self.tsunami = BaseTsunami() 1252521SN/A self.tsunami.attachIO(self.piobus) 1264997Sgblack@eecs.umich.edu self.tsunami.ide.pio = self.piobus.master 1274997Sgblack@eecs.umich.edu self.tsunami.ide.config = self.piobus.master 1284997Sgblack@eecs.umich.edu self.tsunami.ethernet.pio = self.piobus.master 1293548Sgblack@eecs.umich.edu self.tsunami.ethernet.config = self.piobus.master 1302654SN/A 1312521SN/A # 1322521SN/A # Store the dma devices for later connection to dma ruby ports. 1335499Ssaidi@eecs.umich.edu # Append an underscore to dma_devices to avoid the SimObjectVector check. 1343673Srdreslin@umich.edu # 1355497Ssaidi@eecs.umich.edu self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 1362190SN/A 1372518SN/A self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1382518SN/A read_only = True)) 1392190SN/A self.intrctrl = IntrControl() 1402190SN/A self.mem_mode = mem_mode 1412190SN/A self.terminal = Terminal() 1422190SN/A self.kernel = binary('vmlinux') 1432159SN/A self.pal = binary('ts_osfpal') 1442235SN/A self.console = binary('console') 1452103SN/A self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 146393SN/A 147393SN/A return self 1482190SN/A 149393SN/Adef makeSparcSystem(mem_mode, mdesc = None): 150393SN/A # Constants from iob.cc and uart8250.cc 1515250Sksewell@umich.edu iob_man_addr = 0x9800000000 152393SN/A uart_pio_size = 8 153393SN/A 1542875Sksewell@umich.edu class CowMmDisk(MmDisk): 155393SN/A image = CowDiskImage(child=RawDiskImage(read_only=True), 156393SN/A read_only=False) 1575250Sksewell@umich.edu 1582159SN/A def childImage(self, ci): 1592159SN/A self.image.child.image_file = ci 1602190SN/A 1612159SN/A self = SparcSystem() 1622159SN/A if not mdesc: 1632680Sktlim@umich.edu # generic system 1642159SN/A mdesc = SysConfig() 1652190SN/A self.readfile = mdesc.script() 1662159SN/A self.iobus = NoncoherentBus() 1672190SN/A self.membus = MemBus() 1682190SN/A self.bridge = Bridge(delay='50ns') 1692159SN/A self.t1000 = T1000() 1702235SN/A self.t1000.attachOnChipIO(self.membus) 1712313SN/A self.t1000.attachIO(self.iobus) 1722235SN/A self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 1732235SN/A AddrRange(Addr('2GB'), size ='256MB')] 1742235SN/A self.bridge.master = self.iobus.slave 1752235SN/A self.bridge.slave = self.membus.master 1762235SN/A self.rom.port = self.membus.master 1772254SN/A self.nvram.port = self.membus.master 1782254SN/A self.hypervisor_desc.port = self.membus.master 1792254SN/A self.partition_desc.port = self.membus.master 1802235SN/A self.intrctrl = IntrControl() 1812235SN/A self.disk0 = CowMmDisk() 1822190SN/A self.disk0.childImage(disk('disk.s10hw2')) 1832159SN/A self.disk0.pio = self.iobus.master 1842235SN/A 1852254SN/A # The puart0 and hvuart are placed on the IO bus, so create ranges 1862190SN/A # for them. The remaining IO range is rather fragmented, so poke 1872159SN/A # holes for the iob and partition descriptors etc. 1882680Sktlim@umich.edu self.bridge.ranges = \ 1892159SN/A [ 1902190SN/A AddrRange(self.t1000.puart0.pio_addr, 1912159SN/A self.t1000.puart0.pio_addr + uart_pio_size - 1), 1922159SN/A AddrRange(self.disk0.pio_addr, 1932159SN/A self.t1000.fake_jbi.pio_addr + 1942159SN/A self.t1000.fake_jbi.pio_size - 1), 1952190SN/A AddrRange(self.t1000.fake_clk.pio_addr, 1962159SN/A iob_man_addr - 1), 1972455SN/A AddrRange(self.t1000.fake_l2_1.pio_addr, 1982159SN/A self.t1000.fake_ssi.pio_addr + 1992455SN/A self.t1000.fake_ssi.pio_size - 1), 2002159SN/A AddrRange(self.t1000.hvuart.pio_addr, 2012455SN/A self.t1000.hvuart.pio_addr + uart_pio_size - 1) 2022455SN/A ] 2032455SN/A self.reset_bin = binary('reset_new.bin') 2042159SN/A self.hypervisor_bin = binary('q_new.bin') 2052190SN/A self.openboot_bin = binary('openboot_new.bin') 2062159SN/A self.nvram_bin = binary('nvram1') 2072455SN/A self.hypervisor_desc_bin = binary('1up-hv.bin') 2082159SN/A self.partition_desc_bin = binary('1up-md.bin') 2092455SN/A 2102159SN/A self.system_port = self.membus.slave 2112455SN/A 2122455SN/A return self 2132455SN/A 2142159SN/Adef makeArmSystem(mem_mode, machine_type, mdesc = None, 2152190SN/A dtb_filename = None, bare_metal=False): 2162159SN/A assert machine_type 2172190SN/A 2182159SN/A if bare_metal: 2192190SN/A self = ArmSystem() 2202159SN/A else: 2212190SN/A self = LinuxArmSystem() 2222159SN/A 2232447SN/A if not mdesc: 2242447SN/A # generic system 2252447SN/A mdesc = SysConfig() 2262447SN/A 2275260Sksewell@umich.edu self.readfile = mdesc.script() 2285260Sksewell@umich.edu self.iobus = NoncoherentBus() 2295260Sksewell@umich.edu self.membus = MemBus() 2305260Sksewell@umich.edu self.membus.badaddr_responder.warn_access = "warn" 2315260Sksewell@umich.edu self.bridge = Bridge(delay='50ns') 2325260Sksewell@umich.edu self.bridge.master = self.iobus.slave 2335260Sksewell@umich.edu self.bridge.slave = self.membus.master 2345260Sksewell@umich.edu 2354172Ssaidi@eecs.umich.edu self.mem_mode = mem_mode 2364172Ssaidi@eecs.umich.edu 2372190SN/A if machine_type == "RealView_PBX": 2382159SN/A self.realview = RealViewPBX() 2394172Ssaidi@eecs.umich.edu elif machine_type == "RealView_EB": 2402190SN/A self.realview = RealViewEB() 2413468Sgblack@eecs.umich.edu elif machine_type == "VExpress_ELT": 2422190SN/A self.realview = VExpress_ELT() 2434661Sksewell@umich.edu elif machine_type == "VExpress_EMM": 2444661Sksewell@umich.edu self.realview = VExpress_EMM() 2454661Sksewell@umich.edu elif machine_type == "VExpress_EMM64": 2464661Sksewell@umich.edu self.realview = VExpress_EMM64() 2472235SN/A else: 2482235SN/A print "Unknown Machine Type" 2492190SN/A sys.exit(1) 2502190SN/A 2512190SN/A self.cf0 = CowIdeDisk(driveID='master') 2522159SN/A self.cf0.childImage(mdesc.disk()) 2532235SN/A # default to an IDE controller rather than a CF one 2542190SN/A # assuming we've got one 2552190SN/A try: 2562159SN/A self.realview.ide.disks = [self.cf0] 2572190SN/A except: 2582159SN/A self.realview.cf_ctrl.disks = [self.cf0] 2592159SN/A 2602190SN/A if bare_metal: 2612159SN/A # EOT character on UART will end the simulation 2622190SN/A self.realview.uart.end_on_eot = True 2632159SN/A self.mem_ranges = [AddrRange(self.realview.mem_start_addr, 2642235SN/A size = mdesc.mem())] 2652190SN/A else: 2662834Sksewell@umich.edu self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 2674111Sgblack@eecs.umich.edu if dtb_filename: 2684111Sgblack@eecs.umich.edu self.dtb_filename = binary(dtb_filename) 2692834Sksewell@umich.edu self.machine_type = machine_type 2702834Sksewell@umich.edu if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 2712834Sksewell@umich.edu print "The currently selected ARM platforms doesn't support" 2722834Sksewell@umich.edu print " the amount of DRAM you've selected. Please try" 2732159SN/A print " another platform" 2742525SN/A sys.exit(1) 2752972Sgblack@eecs.umich.edu 2762972Sgblack@eecs.umich.edu boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 2775217Ssaidi@eecs.umich.edu 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() 2785217Ssaidi@eecs.umich.edu self.mem_ranges = [AddrRange(self.realview.mem_start_addr, 2795217Ssaidi@eecs.umich.edu size = mdesc.mem())] 2802159SN/A self.realview.setupBootLoader(self.membus, self, binary) 2812159SN/A self.gic_cpu_addr = self.realview.gic.cpu_addr 2822682Sktlim@umich.edu self.flags_addr = self.realview.realview_io.pio_addr + 0x30 2832682Sktlim@umich.edu 2842682Sktlim@umich.edu if mdesc.disk().lower().count('android'): 2852682Sktlim@umich.edu boot_flags += " init=/init " 2862682Sktlim@umich.edu self.boot_osflags = boot_flags 2872682Sktlim@umich.edu self.realview.attachOnChipIO(self.membus, self.bridge) 2882682Sktlim@umich.edu self.realview.attachIO(self.iobus) 2892682Sktlim@umich.edu self.intrctrl = IntrControl() 2902682Sktlim@umich.edu self.terminal = Terminal() 2912682Sktlim@umich.edu self.vncserver = VncServer() 2922680Sktlim@umich.edu 2932680Sktlim@umich.edu self.system_port = self.membus.slave 2942190SN/A 2952190SN/A return self 2962680Sktlim@umich.edu 2972680Sktlim@umich.edu 2982159SN/Adef makeLinuxMipsSystem(mem_mode, mdesc = None): 2992190SN/A class BaseMalta(Malta): 3002680Sktlim@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 3012SN/A ide = IdeController(disks=[Parent.disk0, Parent.disk2], 3022SN/A pci_func=0, pci_dev=0, pci_bus=0) 3032SN/A 3042680Sktlim@umich.edu self = LinuxMipsSystem() 3052SN/A if not mdesc: 3062680Sktlim@umich.edu # generic system 307716SN/A mdesc = SysConfig() 3082680Sktlim@umich.edu self.readfile = mdesc.script() 3092SN/A self.iobus = NoncoherentBus() 3103453Sgblack@eecs.umich.edu self.membus = MemBus() 3111917SN/A self.bridge = Bridge(delay='50ns') 3123453Sgblack@eecs.umich.edu self.mem_ranges = [AddrRange('1GB')] 3132521SN/A self.bridge.master = self.iobus.slave 3144997Sgblack@eecs.umich.edu self.bridge.slave = self.membus.master 3154997Sgblack@eecs.umich.edu self.disk0 = CowIdeDisk(driveID='master') 3164997Sgblack@eecs.umich.edu self.disk2 = CowIdeDisk(driveID='master') 3173548Sgblack@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 3183548Sgblack@eecs.umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 3192654SN/A self.malta = BaseMalta() 3202680Sktlim@umich.edu self.malta.attachIO(self.iobus) 3212521SN/A self.malta.ide.pio = self.iobus.master 3225499Ssaidi@eecs.umich.edu self.malta.ide.config = self.iobus.master 3233673Srdreslin@umich.edu self.malta.ide.dma = self.iobus.slave 3245497Ssaidi@eecs.umich.edu self.malta.ethernet.pio = self.iobus.master 3252SN/A self.malta.ethernet.config = self.iobus.master 3262680Sktlim@umich.edu self.malta.ethernet.dma = self.iobus.slave 3272518SN/A self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 3282680Sktlim@umich.edu read_only = True)) 3292SN/A self.intrctrl = IntrControl() 3302SN/A self.mem_mode = mem_mode 3312680Sktlim@umich.edu self.terminal = Terminal() 332595SN/A self.kernel = binary('mips/vmlinux') 3332680Sktlim@umich.edu self.console = binary('mips/console') 3342SN/A self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 3352190SN/A 3362190SN/A self.system_port = self.membus.slave 3372680Sktlim@umich.edu 3382SN/A return self 3392190SN/A 3405250Sksewell@umich.edudef x86IOAddress(port): 3412SN/A IO_address_space_base = 0x8000000000000000 3422190SN/A return IO_address_space_base + port 3432875Sksewell@umich.edu 3442SN/Adef connectX86ClassicSystem(x86_sys, numCPUs): 3452190SN/A # Constants similar to x86_traits.hh 3465250Sksewell@umich.edu IO_address_space_base = 0x8000000000000000 347217SN/A pci_config_address_space_base = 0xc000000000000000 3481858SN/A interrupts_address_space_base = 0xa000000000000000 3492680Sktlim@umich.edu APIC_range_size = 1 << 12; 3502190SN/A 3512190SN/A x86_sys.membus = MemBus() 3522680Sktlim@umich.edu 3532680Sktlim@umich.edu # North Bridge 3542190SN/A x86_sys.iobus = NoncoherentBus() 3552680Sktlim@umich.edu x86_sys.bridge = Bridge(delay='50ns') 3562190SN/A x86_sys.bridge.master = x86_sys.iobus.slave 3572680Sktlim@umich.edu x86_sys.bridge.slave = x86_sys.membus.master 3582190SN/A # Allow the bridge to pass through the IO APIC (two pages), 3592680Sktlim@umich.edu # everything in the IO address range up to the local APIC, and 3602190SN/A # then the entire PCI address space and beyond 3612235SN/A x86_sys.bridge.ranges = \ 3622680Sktlim@umich.edu [ 3632235SN/A AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr, 3642680Sktlim@umich.edu x86_sys.pc.south_bridge.io_apic.pio_addr + 3652680Sktlim@umich.edu APIC_range_size - 1), 3662254SN/A AddrRange(IO_address_space_base, 3672680Sktlim@umich.edu interrupts_address_space_base - 1), 3682680Sktlim@umich.edu AddrRange(pci_config_address_space_base, 3692235SN/A Addr.max) 3702235SN/A ] 3712680Sktlim@umich.edu 3722190SN/A # Create a bridge from the IO bus to the memory bus to allow access to 3732190SN/A # the local APIC (two pages) 3742680Sktlim@umich.edu x86_sys.apicbridge = Bridge(delay='50ns') 3752SN/A x86_sys.apicbridge.slave = x86_sys.iobus.master 3762190SN/A x86_sys.apicbridge.master = x86_sys.membus.slave 3772680Sktlim@umich.edu x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 3782SN/A interrupts_address_space_base + 3792680Sktlim@umich.edu numCPUs * APIC_range_size 380716SN/A - 1)] 3812SN/A 3822SN/A # connect the io bus 3832SN/A x86_sys.pc.attachIO(x86_sys.iobus) 3842SN/A 3852680Sktlim@umich.edu x86_sys.system_port = x86_sys.membus.slave 3862SN/A 3872455SN/Adef connectX86RubySystem(x86_sys): 3882680Sktlim@umich.edu # North Bridge 3892SN/A x86_sys.piobus = NoncoherentBus() 3902455SN/A 3912680Sktlim@umich.edu # add the ide to the list of dma devices that later need to attach to 3922SN/A # dma controllers 3932455SN/A x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 3942680Sktlim@umich.edu x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports) 3952455SN/A 3962455SN/A 3972680Sktlim@umich.edudef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, 3982SN/A Ruby = False): 3992SN/A if self == None: 4002680Sktlim@umich.edu self = X86System() 4012SN/A 4022455SN/A if not mdesc: 4032680Sktlim@umich.edu # generic system 4042SN/A mdesc = SysConfig() 4052455SN/A self.readfile = mdesc.script() 4062680Sktlim@umich.edu 4072SN/A self.mem_mode = mem_mode 4082455SN/A 4092680Sktlim@umich.edu # Physical memory 4102455SN/A self.mem_ranges = [AddrRange(mdesc.mem())] 4112455SN/A 4122680Sktlim@umich.edu # Platform 4132SN/A self.pc = Pc() 4142680Sktlim@umich.edu 4152SN/A # Create and connect the busses required by each memory system 4162680Sktlim@umich.edu if Ruby: 4172206SN/A connectX86RubySystem(self) 4182680Sktlim@umich.edu else: 4192252SN/A connectX86ClassicSystem(self, numCPUs) 4202680Sktlim@umich.edu 4212SN/A self.intrctrl = IntrControl() 4222680Sktlim@umich.edu 4232447SN/A # Disks 4242680Sktlim@umich.edu disk0 = CowIdeDisk(driveID='master') 4252447SN/A disk2 = CowIdeDisk(driveID='master') 4265260Sksewell@umich.edu disk0.childImage(mdesc.disk()) 4275260Sksewell@umich.edu disk2.childImage(disk('linux-bigswap2.img')) 4285260Sksewell@umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 4295260Sksewell@umich.edu 4305260Sksewell@umich.edu # Add in a Bios information structure. 4315260Sksewell@umich.edu structures = [X86SMBiosBiosInformation()] 4325592Sgblack@eecs.umich.edu self.smbios_table.structures = structures 4335260Sksewell@umich.edu 4344172Ssaidi@eecs.umich.edu # Set up the Intel MP table 4354172Ssaidi@eecs.umich.edu base_entries = [] 4364172Ssaidi@eecs.umich.edu ext_entries = [] 4372159SN/A for i in xrange(numCPUs): 4382680Sktlim@umich.edu bp = X86IntelMPProcessor( 4392SN/A local_apic_id = i, 4404172Ssaidi@eecs.umich.edu local_apic_version = 0x14, 4414172Ssaidi@eecs.umich.edu enable = True, 4422SN/A bootstrap = (i == 0)) 4433468Sgblack@eecs.umich.edu base_entries.append(bp) 4442680Sktlim@umich.edu io_apic = X86IntelMPIOAPIC( 4452SN/A id = numCPUs, 4462190SN/A version = 0x11, 4472680Sktlim@umich.edu enable = True, 4482190SN/A address = 0xfec00000) 4492190SN/A self.pc.south_bridge.io_apic.apic_id = io_apic.id 4502680Sktlim@umich.edu base_entries.append(io_apic) 4512SN/A isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 4522190SN/A base_entries.append(isa_bus) 4532680Sktlim@umich.edu pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 4542190SN/A base_entries.append(pci_bus) 4551858SN/A connect_busses = X86IntelMPBusHierarchy(bus_id=0, 4562680Sktlim@umich.edu subtractive_decode=True, parent_bus=1) 457360SN/A ext_entries.append(connect_busses) 458360SN/A pci_dev4_inta = X86IntelMPIOIntAssignment( 4592190SN/A interrupt_type = 'INT', 4602680Sktlim@umich.edu polarity = 'ConformPolarity', 461360SN/A trigger = 'ConformTrigger', 4621450SN/A source_bus_id = 1, 4632680Sktlim@umich.edu source_bus_irq = 0 + (4 << 2), 464360SN/A dest_io_apic_id = io_apic.id, 4654111Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 4664111Sgblack@eecs.umich.edu base_entries.append(pci_dev4_inta) 4674111Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 4682680Sktlim@umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 4692SN/A interrupt_type = 'ExtInt', 4702525SN/A polarity = 'ConformPolarity', 4712972Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4722972Sgblack@eecs.umich.edu source_bus_id = 0, 4732525SN/A source_bus_irq = irq, 4742680Sktlim@umich.edu dest_io_apic_id = io_apic.id, 4752525SN/A dest_io_apic_intin = 0) 4762SN/A base_entries.append(assign_8259_to_apic) 4772SN/A assign_to_apic = X86IntelMPIOIntAssignment( 4782190SN/A interrupt_type = 'INT', 479 polarity = 'ConformPolarity', 480 trigger = 'ConformTrigger', 481 source_bus_id = 0, 482 source_bus_irq = irq, 483 dest_io_apic_id = io_apic.id, 484 dest_io_apic_intin = apicPin) 485 base_entries.append(assign_to_apic) 486 assignISAInt(0, 2) 487 assignISAInt(1, 1) 488 for i in range(3, 15): 489 assignISAInt(i, i) 490 self.intel_mp_table.base_entries = base_entries 491 self.intel_mp_table.ext_entries = ext_entries 492 493def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, 494 Ruby = False): 495 self = LinuxX86System() 496 497 # Build up the x86 system and then specialize it for Linux 498 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 499 500 # We assume below that there's at least 1MB of memory. We'll require 2 501 # just to avoid corner cases. 502 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 503 assert(phys_mem_size >= 0x200000) 504 505 self.e820_table.entries = \ 506 [ 507 # Mark the first megabyte of memory as reserved 508 X86E820Entry(addr = 0, size = '639kB', range_type = 1), 509 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 510 # Mark the rest as available 511 X86E820Entry(addr = 0x100000, 512 size = '%dB' % (phys_mem_size - 0x100000), 513 range_type = 1), 514 # Reserve the last 16kB of the 32-bit address space for the 515 # m5op interface 516 X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2), 517 ] 518 519 # Command line 520 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 521 'root=/dev/hda1' 522 self.kernel = binary('x86_64-vmlinux-2.6.22.9') 523 return self 524 525 526def makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 527 self = Root(full_system = full_system) 528 self.testsys = testSystem 529 self.drivesys = driveSystem 530 self.etherlink = EtherLink() 531 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 532 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 533 534 if hasattr(testSystem, 'realview'): 535 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 536 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 537 elif hasattr(testSystem, 'tsunami'): 538 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 539 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 540 else: 541 fatal("Don't know how to connect these system together") 542 543 if dumpfile: 544 self.etherdump = EtherDump(file=dumpfile) 545 self.etherlink.dump = Parent.etherdump 546 547 return self 548