README revision 11971
111731Sjason@lowepower.comThis directory contains a demo of a coupling between gem5 and SystemC-TLM.  It
211731Sjason@lowepower.comis based on the gem5-systemc implementation in utils/systemc. This Readme gives
311731Sjason@lowepower.coman overall overview (I), describes the source files in this directory (II),
411731Sjason@lowepower.comexplains the build steps (III), shows how to run example simulations (IV-VI)
511731Sjason@lowepower.comand lists known issues (VII).
612137Sar4jc@virginia.edu
712137Sar4jc@virginia.edu
812137Sar4jc@virginia.eduI. Overview
912137Sar4jc@virginia.edu===========
1011731Sjason@lowepower.com
1111731Sjason@lowepower.comThe sources in this directory provide three SystemC modules that manage the
1211731Sjason@lowepower.comSystemC/gem5 co-simulation: Gem5SimControl, Gem5MasterTransactor, and
1311731Sjason@lowepower.comGem5SlaveTransactor. They also implement gem5's ExternalMaster::Port interface
1411731Sjason@lowepower.com(SCMasterPort) and ExternalSlave::Port interface (SCSlavePort).
1511731Sjason@lowepower.com
1611731Sjason@lowepower.com**SCMasterPort** and **Gem5MasterTransactor** together form a TLM-to-gem5
1711731Sjason@lowepower.combridge. SCMasterPort implements gem5's ExternalMaster::Port interface and forms
1811731Sjason@lowepower.comthe gem5 end of the bridge. Gem5MasterTransactor is a SystemC module that
1911731Sjason@lowepower.comprovides a target socket and represents the TLM side of the bridge. All TLM
2011731Sjason@lowepower.comrequests send to this target socket, are translated to gem5 requests and
2111731Sjason@lowepower.comforwarded to the gem5 world through the SCMasterPort. Then the gem5 world
2211731Sjason@lowepower.comhandles the request and eventually issues a response. When the response arrives
2311731Sjason@lowepower.comat the SCMasterPort it gets translated back into a TLM response and forwarded
2411731Sjason@lowepower.comto the TLM world through target socket of the Gem5MasterTransactor.
2511731Sjason@lowepower.comSCMasterPort and Gem5MasterTransactor are bound to each other by configuring
2611731Sjason@lowepower.comthem for the same port name.
2711731Sjason@lowepower.com
2811731Sjason@lowepower.com**SCSlavePort** and **Gem5SlaveTransactor** together form a gem5-to-TLM bridge.
2911731Sjason@lowepower.comGem5SlaveTransactor is a SystemC module that provides a initiator socket and
3011731Sjason@lowepower.comrepresents the TLM end of the bridge. SCSlavePort implements gem5's
3111731Sjason@lowepower.comExternalSlave::Port interface and forms the gem5 side of the bridge. All gem5
3211731Sjason@lowepower.comrequests sent to the SCSlavePort, are translated to TLM requests and forwarded
3311731Sjason@lowepower.comto the TLM world through the initiator socket of the Gem5SlaveTransactor. Then
3411731Sjason@lowepower.comthe TLM world handles the request and eventually issues a response. When the
3511731Sjason@lowepower.comresponse arrives at the Gem5SlaveTransactor it gets translated back into a
3611731Sjason@lowepower.comgem5 response and forwarded to the gem5 world through the SCSlavePort. SCSLavePort
3711731Sjason@lowepower.comand Gem5SlaveTransactor are bound to each other by configuring them for the
3811731Sjason@lowepower.comsame port name.
3911731Sjason@lowepower.com
4011731Sjason@lowepower.com**Gem5SimControl** is the central SystemC module that represents the complete
4111731Sjason@lowepower.comgem5 world. It is responsible for instantiating all gem5 objects according to a
4211731Sjason@lowepower.comgiven configuration file, for configuring the simulation and for maintaining
4311731Sjason@lowepower.comthe gem5 event queue. It also keeps track of all SCMasterPort and SCSlavePort
4411731Sjason@lowepower.comand responsible for connecting all Gem5MasterTransactor and Gem5SlaveTransactor
4511731Sjason@lowepower.commodules to their gem5 counterparts. This module must be instantiated exactly
4611731Sjason@lowepower.comonce in order to run a gem5 simulation from within an SystemC environment.
4711731Sjason@lowepower.com
4811731Sjason@lowepower.com
4911731Sjason@lowepower.comII. Files
5011731Sjason@lowepower.com=========
5111731Sjason@lowepower.com
5211731Sjason@lowepower.com    sc_slave_port.{cc,hh}     -- Implements SCSlavePort
5311731Sjason@lowepower.com    sc_master_port.{cc,hh}    -- Implements SCMasterPort
5411731Sjason@lowepower.com    sc_mm.{cc,hh}             -- Implementation of a TLM memory manager
5511731Sjason@lowepower.com    sc_ext.{cc,hh}            -- TLM extension that carries a gem5 packet
5611731Sjason@lowepower.com    sc_peq.{cc,hh}            -- TLM PEQ for scheduling gem5 events
5711731Sjason@lowepower.com    sim_control.{cc,hh}       -- Implements Gem5SimControl
5811731Sjason@lowepower.com    slave_transactor.{cc,hh}  -- Implements Gem5SlaveTransactor
5911731Sjason@lowepower.com    master_transactor.{cc,hh} -- Implements Gem5MasterTransactor
6011731Sjason@lowepower.com
6111731Sjason@lowepower.com    example/common/cli_parser.{cc,hh}     -- Simple cli argument parser
6211731Sjason@lowepower.com    example/common/report_hanlder.{cc,hh} -- Custom SystemC report handler
6311731Sjason@lowepower.com
6411731Sjason@lowepower.com    example/slave_port/main.cc           -- demonstration of the slave port
6511731Sjason@lowepower.com    example/slave_port/sc_target.{cc,hh} -- an example TLM LT/AT memory module
6611731Sjason@lowepower.com    example/slave_port/tlm.py            -- simple gem5 configuration
6711731Sjason@lowepower.com    example/slave_port/tlm_elastic.py    -- gem5 configuration with an elastic
6811731Sjason@lowepower.com                                            trace replayer
6911731Sjason@lowepower.com    example/slave_port/tgen.cfg          -- elastic traceplayer configuration
7011731Sjason@lowepower.com
7111731Sjason@lowepower.com    example/master_port/main.cc          -- demonstration of the master port
7211731Sjason@lowepower.com    example/master_port/traffic_generator.{cc/hh}
7311731Sjason@lowepower.com                                         -- an example traffic generator module
7411731Sjason@lowepower.com    example/master_port/tlm.py           -- simple gem5 configuration
7511731Sjason@lowepower.com
7611731Sjason@lowepower.comOther Files will be used from utils/systemc example:
7711731Sjason@lowepower.com
7811731Sjason@lowepower.com    sc_logger.{cc,hh},
7911731Sjason@lowepower.com    sc_module.{cc,hh},
8011731Sjason@lowepower.com    sc_gem5_control.{cc,hh},
8111731Sjason@lowepower.com    stats.{cc,hh}
8211731Sjason@lowepower.com
8311731Sjason@lowepower.com
8411731Sjason@lowepower.comIII. Build
8511731Sjason@lowepower.com==========
8611731Sjason@lowepower.com
8711731Sjason@lowepower.comFirst build a normal gem5 (cxx-config not needed, Python needed).
8811731Sjason@lowepower.comSecond build gem5 as a library with cxx-config support and (optionally)
8911731Sjason@lowepower.comwithout python.
9011731Sjason@lowepower.com
9111731Sjason@lowepower.com> cd ../..
9211731Sjason@lowepower.com> scons build/ARM/gem5.opt
9311731Sjason@lowepower.com> scons --with-cxx-config --without-python --without-tcmalloc \
9411731Sjason@lowepower.com>       build/ARM/libgem5_opt.so
9511731Sjason@lowepower.com> cd util/tlm
9611731Sjason@lowepower.com
9711731Sjason@lowepower.comNote: For MAC / OSX this command should be used:
9811731Sjason@lowepower.com> scons --with-cxx-config --without-python --without-tcmalloc \
9911731Sjason@lowepower.com>       build/ARM/libgem5_opt.dylib
10011731Sjason@lowepower.com
10111731Sjason@lowepower.comSet a proper LD_LIBRARY_PATH e.g. for bash:
10211731Sjason@lowepower.com> export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
10311731Sjason@lowepower.com
10411731Sjason@lowepower.comor for MAC / OSX:
10511731Sjason@lowepower.com> export DYLD_LIBRARY_PATH="$DYLD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
10611731Sjason@lowepower.com
10711731Sjason@lowepower.comThe build system finds your SystemC installation using pkg-config. Make sure
10811731Sjason@lowepower.comthat pkg-config is installed and your systemc.pc is within your
10911731Sjason@lowepower.comPKG_CONFIG_PATH. You can add SystemC to the PKG_CONFIG_PATH using the following
11011731Sjason@lowepower.comcommand:
11111731Sjason@lowepower.com> export PKG_CONFIG_PATH="/path/to/systemc/lib-<arch>/pkgconfig/:$PKG_CONFIG_PATH"
11211731Sjason@lowepower.com
11311731Sjason@lowepower.comTo build one of the examples:
11411731Sjason@lowepower.com
11511731Sjason@lowepower.com> cd examples/{master,slave}_port
11611731Sjason@lowepower.com> scons
11711731Sjason@lowepower.com> cd ../../
11811731Sjason@lowepower.com
11912137Sar4jc@virginia.edu
12012137Sar4jc@virginia.eduIV. Simple Examples
12112137Sar4jc@virginia.edu===================
12212137Sar4jc@virginia.edu
12312137Sar4jc@virginia.edu> cd examples/{master,slave}_port
12412137Sar4jc@virginia.edu
12512137Sar4jc@virginia.eduIn order to run our example simulation, we first need to create a config.ini
12612137Sar4jc@virginia.eduthat represents the gem5 configuration. We do so by starting gem5 with the
12712137Sar4jc@virginia.edudesired python configuration script.
12812137Sar4jc@virginia.edu
12912137Sar4jc@virginia.edu> ../../../../build/ARM/gem5.opt ./tlm.py
13012137Sar4jc@virginia.edu
13112137Sar4jc@virginia.eduThe message "fatal: Can't find port handler type 'tlm_{master,slave}'" is okay.
13212137Sar4jc@virginia.eduThe configuration will be stored in the m5out/ directory
13312137Sar4jc@virginia.edu
13412137Sar4jc@virginia.eduThe build step creates a binary gem5.opt.sc in the example directory.  It can
13512137Sar4jc@virginia.edunow be used to load in the generated configuration file from the previous
13612137Sar4jc@virginia.edunormal gem5 run.
13712137Sar4jc@virginia.edu
13812137Sar4jc@virginia.eduTry:
13912137Sar4jc@virginia.edu
14012137Sar4jc@virginia.edu> ./gem5.opt.sc m5out/config.ini -e 1000000
14112137Sar4jc@virginia.edu
14212137Sar4jc@virginia.eduIt should run a simulation for 1us.
14312137Sar4jc@virginia.edu
14412137Sar4jc@virginia.eduTo see more information what happens inside the TLM modules use the -v flag:
14512137Sar4jc@virginia.edu
14612137Sar4jc@virginia.edu> ./gem5.opt.sc m5out/config.ini -e 1000000 -v
14712137Sar4jc@virginia.edu
14812137Sar4jc@virginia.eduTo see more information about the port coupling use:
14912137Sar4jc@virginia.edu
15012137Sar4jc@virginia.edu> ./gem5.opt.sc m5out/config.ini -e 1000000 -d ExternalPort
15112137Sar4jc@virginia.edu
15212137Sar4jc@virginia.edu
15312137Sar4jc@virginia.eduV. Full System Setup
15412137Sar4jc@virginia.edu=====================
15512137Sar4jc@virginia.edu
15612137Sar4jc@virginia.eduApart from the simple examples, there is a full system example that uses
15712137Sar4jc@virginia.eduthe gem5-to-TLM bridge.
15812137Sar4jc@virginia.edu
15912137Sar4jc@virginia.edu>cd examples/slave_port
16012137Sar4jc@virginia.edu
16112137Sar4jc@virginia.eduBuild gem5 as described in Section III. Then, make a config file for the
16212137Sar4jc@virginia.eduC++-configured gem5 using normal gem5
16312137Sar4jc@virginia.edu
16412137Sar4jc@virginia.edu> ../../../../build/ARM/gem5.opt ../../../../configs/example/fs.py   \
16512137Sar4jc@virginia.edu  --tlm-memory=transactor --cpu-type=timing --num-cpu=1              \
16612137Sar4jc@virginia.edu  --mem-type=SimpleMemory --mem-size=512MB --mem-channels=1 --caches \
16712137Sar4jc@virginia.edu  --l2cache --machine-type=VExpress_EMM                              \
16812137Sar4jc@virginia.edu  --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb        \
16912137Sar4jc@virginia.edu  --kernel=vmlinux.aarch32.ll_20131205.0-gem5                        \
17012137Sar4jc@virginia.edu  --disk-image=linux-aarch32-ael.img
17112137Sar4jc@virginia.edu
17212137Sar4jc@virginia.eduThe message "fatal: Can't find port handler type 'tlm_slave'" is okay.
17312137Sar4jc@virginia.eduThe configuration will be stored in the m5out/ directory
17412137Sar4jc@virginia.edu
17512137Sar4jc@virginia.eduThe binary 'gem5.opt.sc' can now be used to load in the generated config
17612137Sar4jc@virginia.edufile from the previous normal gem5 run.
17712137Sar4jc@virginia.edu
17812137Sar4jc@virginia.eduTry:
17912137Sar4jc@virginia.edu
18012137Sar4jc@virginia.edu> ./gem5.opt.sc m5out/config.ini -o 2147483648
18112137Sar4jc@virginia.edu
18212137Sar4jc@virginia.eduThe parameter -o specifies the begining of the memory region (0x80000000).
18312137Sar4jc@virginia.eduThe system should boot now.
18412137Sar4jc@virginia.edu
18512137Sar4jc@virginia.eduFor convenience a run_gem5.sh file holds all those commands
18612137Sar4jc@virginia.edu
18712137Sar4jc@virginia.edu
18812137Sar4jc@virginia.eduVI. Elastic Trace Setup
18912137Sar4jc@virginia.edu========================
19012137Sar4jc@virginia.edu
19112137Sar4jc@virginia.eduElastic traces can also be replayed into the SystemC world.
19212137Sar4jc@virginia.eduFor more information on elastic traces please refer to:
19312137Sar4jc@virginia.edu
19412137Sar4jc@virginia.edu - http://www.gem5.org/TraceCPU
19512137Sar4jc@virginia.edu
19612137Sar4jc@virginia.edu - Exploring System Performance using Elastic Traces:
19712137Sar4jc@virginia.edu   Fast, Accurate and Portable
19812137Sar4jc@virginia.edu   R. Jagtap, S. Diestelhorst, A. Hansson, M. Jung, N. Wehn.
19912137Sar4jc@virginia.edu   IEEE International Conference on Embedded Computer Systems Architectures
20012137Sar4jc@virginia.edu   Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece.
20112137Sar4jc@virginia.edu
20212137Sar4jc@virginia.eduSimilar IV. the simulation can be set up with this command:
20312137Sar4jc@virginia.edu
20412137Sar4jc@virginia.edu> ../../../../build/ARM/gem5.opt ./tlm_elastic.py
20512137Sar4jc@virginia.edu
20612137Sar4jc@virginia.eduThen:
20712137Sar4jc@virginia.edu
20812137Sar4jc@virginia.edu> ./gem5.opt.sc m5out/config.ini
20912137Sar4jc@virginia.edu
21012137Sar4jc@virginia.edu
21112137Sar4jc@virginia.eduVII. Knwon issues
21212137Sar4jc@virginia.edu=================
21312137Sar4jc@virginia.edu
21412137Sar4jc@virginia.edu* For some toolchains, compiling libgem5 with tcmalloc leads to errors
21512137Sar4jc@virginia.edu  ('tcmalloc Attempt to free invalid pointer xxx') when linking libgem5 into a
21612137Sar4jc@virginia.edu  SystemC application.
21712137Sar4jc@virginia.edu* When SystemC was build with --enable-pthreads, SystemC applications linked
21812137Sar4jc@virginia.edu