README revision 11971
1955SN/AThis directory contains a demo of a coupling between gem5 and SystemC-TLM.  It
2955SN/Ais based on the gem5-systemc implementation in utils/systemc. This Readme gives
31762SN/Aan overall overview (I), describes the source files in this directory (II),
4955SN/Aexplains the build steps (III), shows how to run example simulations (IV-VI)
5955SN/Aand lists known issues (VII).
6955SN/A
7955SN/A
8955SN/AI. Overview
9955SN/A===========
10955SN/A
11955SN/AThe sources in this directory provide three SystemC modules that manage the
12955SN/ASystemC/gem5 co-simulation: Gem5SimControl, Gem5MasterTransactor, and
13955SN/AGem5SlaveTransactor. They also implement gem5's ExternalMaster::Port interface
14955SN/A(SCMasterPort) and ExternalSlave::Port interface (SCSlavePort).
15955SN/A
16955SN/A**SCMasterPort** and **Gem5MasterTransactor** together form a TLM-to-gem5
17955SN/Abridge. SCMasterPort implements gem5's ExternalMaster::Port interface and forms
18955SN/Athe gem5 end of the bridge. Gem5MasterTransactor is a SystemC module that
19955SN/Aprovides a target socket and represents the TLM side of the bridge. All TLM
20955SN/Arequests send to this target socket, are translated to gem5 requests and
21955SN/Aforwarded to the gem5 world through the SCMasterPort. Then the gem5 world
22955SN/Ahandles the request and eventually issues a response. When the response arrives
23955SN/Aat the SCMasterPort it gets translated back into a TLM response and forwarded
24955SN/Ato the TLM world through target socket of the Gem5MasterTransactor.
25955SN/ASCMasterPort and Gem5MasterTransactor are bound to each other by configuring
26955SN/Athem for the same port name.
27955SN/A
282665Ssaidi@eecs.umich.edu**SCSlavePort** and **Gem5SlaveTransactor** together form a gem5-to-TLM bridge.
292665Ssaidi@eecs.umich.eduGem5SlaveTransactor is a SystemC module that provides a initiator socket and
30955SN/Arepresents the TLM end of the bridge. SCSlavePort implements gem5's
31955SN/AExternalSlave::Port interface and forms the gem5 side of the bridge. All gem5
32955SN/Arequests sent to the SCSlavePort, are translated to TLM requests and forwarded
33955SN/Ato the TLM world through the initiator socket of the Gem5SlaveTransactor. Then
34955SN/Athe TLM world handles the request and eventually issues a response. When the
352632Sstever@eecs.umich.eduresponse arrives at the Gem5SlaveTransactor it gets translated back into a
362632Sstever@eecs.umich.edugem5 response and forwarded to the gem5 world through the SCSlavePort. SCSLavePort
372632Sstever@eecs.umich.eduand Gem5SlaveTransactor are bound to each other by configuring them for the
382632Sstever@eecs.umich.edusame port name.
39955SN/A
402632Sstever@eecs.umich.edu**Gem5SimControl** is the central SystemC module that represents the complete
412632Sstever@eecs.umich.edugem5 world. It is responsible for instantiating all gem5 objects according to a
422761Sstever@eecs.umich.edugiven configuration file, for configuring the simulation and for maintaining
432632Sstever@eecs.umich.eduthe gem5 event queue. It also keeps track of all SCMasterPort and SCSlavePort
442632Sstever@eecs.umich.eduand responsible for connecting all Gem5MasterTransactor and Gem5SlaveTransactor
452632Sstever@eecs.umich.edumodules to their gem5 counterparts. This module must be instantiated exactly
462761Sstever@eecs.umich.eduonce in order to run a gem5 simulation from within an SystemC environment.
472761Sstever@eecs.umich.edu
482761Sstever@eecs.umich.edu
492632Sstever@eecs.umich.eduII. Files
502632Sstever@eecs.umich.edu=========
512761Sstever@eecs.umich.edu
522761Sstever@eecs.umich.edu    sc_slave_port.{cc,hh}     -- Implements SCSlavePort
532761Sstever@eecs.umich.edu    sc_master_port.{cc,hh}    -- Implements SCMasterPort
542761Sstever@eecs.umich.edu    sc_mm.{cc,hh}             -- Implementation of a TLM memory manager
552761Sstever@eecs.umich.edu    sc_ext.{cc,hh}            -- TLM extension that carries a gem5 packet
562632Sstever@eecs.umich.edu    sc_peq.{cc,hh}            -- TLM PEQ for scheduling gem5 events
572632Sstever@eecs.umich.edu    sim_control.{cc,hh}       -- Implements Gem5SimControl
582632Sstever@eecs.umich.edu    slave_transactor.{cc,hh}  -- Implements Gem5SlaveTransactor
592632Sstever@eecs.umich.edu    master_transactor.{cc,hh} -- Implements Gem5MasterTransactor
602632Sstever@eecs.umich.edu
612632Sstever@eecs.umich.edu    example/common/cli_parser.{cc,hh}     -- Simple cli argument parser
622632Sstever@eecs.umich.edu    example/common/report_hanlder.{cc,hh} -- Custom SystemC report handler
63955SN/A
64955SN/A    example/slave_port/main.cc           -- demonstration of the slave port
65955SN/A    example/slave_port/sc_target.{cc,hh} -- an example TLM LT/AT memory module
66955SN/A    example/slave_port/tlm.py            -- simple gem5 configuration
67955SN/A    example/slave_port/tlm_elastic.py    -- gem5 configuration with an elastic
683918Ssaidi@eecs.umich.edu                                            trace replayer
694202Sbinkertn@umich.edu    example/slave_port/tgen.cfg          -- elastic traceplayer configuration
703716Sstever@eecs.umich.edu
71955SN/A    example/master_port/main.cc          -- demonstration of the master port
722656Sstever@eecs.umich.edu    example/master_port/traffic_generator.{cc/hh}
732656Sstever@eecs.umich.edu                                         -- an example traffic generator module
742656Sstever@eecs.umich.edu    example/master_port/tlm.py           -- simple gem5 configuration
752656Sstever@eecs.umich.edu
762656Sstever@eecs.umich.eduOther Files will be used from utils/systemc example:
772656Sstever@eecs.umich.edu
782656Sstever@eecs.umich.edu    sc_logger.{cc,hh},
792653Sstever@eecs.umich.edu    sc_module.{cc,hh},
802653Sstever@eecs.umich.edu    sc_gem5_control.{cc,hh},
812653Sstever@eecs.umich.edu    stats.{cc,hh}
822653Sstever@eecs.umich.edu
832653Sstever@eecs.umich.edu
842653Sstever@eecs.umich.eduIII. Build
852653Sstever@eecs.umich.edu==========
862653Sstever@eecs.umich.edu
872653Sstever@eecs.umich.eduFirst build a normal gem5 (cxx-config not needed, Python needed).
882653Sstever@eecs.umich.eduSecond build gem5 as a library with cxx-config support and (optionally)
892653Sstever@eecs.umich.eduwithout python.
901852SN/A
91955SN/A> cd ../..
92955SN/A> scons build/ARM/gem5.opt
93955SN/A> scons --with-cxx-config --without-python --without-tcmalloc \
943717Sstever@eecs.umich.edu>       build/ARM/libgem5_opt.so
953716Sstever@eecs.umich.edu> cd util/tlm
96955SN/A
971533SN/ANote: For MAC / OSX this command should be used:
983716Sstever@eecs.umich.edu> scons --with-cxx-config --without-python --without-tcmalloc \
991533SN/A>       build/ARM/libgem5_opt.dylib
100955SN/A
101955SN/ASet a proper LD_LIBRARY_PATH e.g. for bash:
1022632Sstever@eecs.umich.edu> export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
1032632Sstever@eecs.umich.edu
104955SN/Aor for MAC / OSX:
105955SN/A> export DYLD_LIBRARY_PATH="$DYLD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
106955SN/A
107955SN/AThe build system finds your SystemC installation using pkg-config. Make sure
1082632Sstever@eecs.umich.eduthat pkg-config is installed and your systemc.pc is within your
109955SN/APKG_CONFIG_PATH. You can add SystemC to the PKG_CONFIG_PATH using the following
1102632Sstever@eecs.umich.educommand:
1112632Sstever@eecs.umich.edu> export PKG_CONFIG_PATH="/path/to/systemc/lib-<arch>/pkgconfig/:$PKG_CONFIG_PATH"
1122632Sstever@eecs.umich.edu
1132632Sstever@eecs.umich.eduTo build one of the examples:
1142632Sstever@eecs.umich.edu
1152632Sstever@eecs.umich.edu> cd examples/{master,slave}_port
1162632Sstever@eecs.umich.edu> scons
1173053Sstever@eecs.umich.edu> cd ../../
1183053Sstever@eecs.umich.edu
1193053Sstever@eecs.umich.edu
1203053Sstever@eecs.umich.eduIV. Simple Examples
1213053Sstever@eecs.umich.edu===================
1223053Sstever@eecs.umich.edu
1233053Sstever@eecs.umich.edu> cd examples/{master,slave}_port
1243053Sstever@eecs.umich.edu
1253053Sstever@eecs.umich.eduIn order to run our example simulation, we first need to create a config.ini
1263053Sstever@eecs.umich.eduthat represents the gem5 configuration. We do so by starting gem5 with the
1273053Sstever@eecs.umich.edudesired python configuration script.
1283053Sstever@eecs.umich.edu
1293053Sstever@eecs.umich.edu> ../../../../build/ARM/gem5.opt ./tlm.py
1303053Sstever@eecs.umich.edu
1313053Sstever@eecs.umich.eduThe message "fatal: Can't find port handler type 'tlm_{master,slave}'" is okay.
1323053Sstever@eecs.umich.eduThe configuration will be stored in the m5out/ directory
1332632Sstever@eecs.umich.edu
1342632Sstever@eecs.umich.eduThe build step creates a binary gem5.opt.sc in the example directory.  It can
1352632Sstever@eecs.umich.edunow be used to load in the generated configuration file from the previous
1362632Sstever@eecs.umich.edunormal gem5 run.
1372632Sstever@eecs.umich.edu
1382632Sstever@eecs.umich.eduTry:
1393718Sstever@eecs.umich.edu
1403718Sstever@eecs.umich.edu> ./gem5.opt.sc m5out/config.ini -e 1000000
1413718Sstever@eecs.umich.edu
1423718Sstever@eecs.umich.eduIt should run a simulation for 1us.
1433718Sstever@eecs.umich.edu
1443718Sstever@eecs.umich.eduTo see more information what happens inside the TLM modules use the -v flag:
1453718Sstever@eecs.umich.edu
1463718Sstever@eecs.umich.edu> ./gem5.opt.sc m5out/config.ini -e 1000000 -v
1473718Sstever@eecs.umich.edu
1483718Sstever@eecs.umich.eduTo see more information about the port coupling use:
1493718Sstever@eecs.umich.edu
1503718Sstever@eecs.umich.edu> ./gem5.opt.sc m5out/config.ini -e 1000000 -d ExternalPort
1513718Sstever@eecs.umich.edu
1522634Sstever@eecs.umich.edu
1532634Sstever@eecs.umich.eduV. Full System Setup
1542632Sstever@eecs.umich.edu=====================
1552638Sstever@eecs.umich.edu
1562632Sstever@eecs.umich.eduApart from the simple examples, there is a full system example that uses
1572632Sstever@eecs.umich.eduthe gem5-to-TLM bridge.
1582632Sstever@eecs.umich.edu
1592632Sstever@eecs.umich.edu>cd examples/slave_port
1602632Sstever@eecs.umich.edu
1612632Sstever@eecs.umich.eduBuild gem5 as described in Section III. Then, make a config file for the
1621858SN/AC++-configured gem5 using normal gem5
1633716Sstever@eecs.umich.edu
1642638Sstever@eecs.umich.edu> ../../../../build/ARM/gem5.opt ../../../../configs/example/fs.py   \
1652638Sstever@eecs.umich.edu  --tlm-memory=transactor --cpu-type=timing --num-cpu=1              \
1662638Sstever@eecs.umich.edu  --mem-type=SimpleMemory --mem-size=512MB --mem-channels=1 --caches \
1672638Sstever@eecs.umich.edu  --l2cache --machine-type=VExpress_EMM                              \
1682638Sstever@eecs.umich.edu  --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb        \
1692638Sstever@eecs.umich.edu  --kernel=vmlinux.aarch32.ll_20131205.0-gem5                        \
1702638Sstever@eecs.umich.edu  --disk-image=linux-aarch32-ael.img
1713716Sstever@eecs.umich.edu
1722634Sstever@eecs.umich.eduThe message "fatal: Can't find port handler type 'tlm_slave'" is okay.
1732634Sstever@eecs.umich.eduThe configuration will be stored in the m5out/ directory
174955SN/A
175955SN/AThe binary 'gem5.opt.sc' can now be used to load in the generated config
176955SN/Afile from the previous normal gem5 run.
177955SN/A
178955SN/ATry:
179955SN/A
180955SN/A> ./gem5.opt.sc m5out/config.ini -o 2147483648
181955SN/A
1821858SN/AThe parameter -o specifies the begining of the memory region (0x80000000).
1831858SN/AThe system should boot now.
1842632Sstever@eecs.umich.edu
185955SN/AFor convenience a run_gem5.sh file holds all those commands
1863643Ssaidi@eecs.umich.edu
1873643Ssaidi@eecs.umich.edu
1883643Ssaidi@eecs.umich.eduVI. Elastic Trace Setup
1893643Ssaidi@eecs.umich.edu========================
1903643Ssaidi@eecs.umich.edu
1913643Ssaidi@eecs.umich.eduElastic traces can also be replayed into the SystemC world.
1923643Ssaidi@eecs.umich.eduFor more information on elastic traces please refer to:
1933643Ssaidi@eecs.umich.edu
1944494Ssaidi@eecs.umich.edu - http://www.gem5.org/TraceCPU
1954494Ssaidi@eecs.umich.edu
1963716Sstever@eecs.umich.edu - Exploring System Performance using Elastic Traces:
1971105SN/A   Fast, Accurate and Portable
1982667Sstever@eecs.umich.edu   R. Jagtap, S. Diestelhorst, A. Hansson, M. Jung, N. Wehn.
1992667Sstever@eecs.umich.edu   IEEE International Conference on Embedded Computer Systems Architectures
2002667Sstever@eecs.umich.edu   Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece.
2012667Sstever@eecs.umich.edu
2022667Sstever@eecs.umich.eduSimilar IV. the simulation can be set up with this command:
2032667Sstever@eecs.umich.edu
2041869SN/A> ../../../../build/ARM/gem5.opt ./tlm_elastic.py
2051869SN/A
2061869SN/AThen:
2071869SN/A
2081869SN/A> ./gem5.opt.sc m5out/config.ini
2091065SN/A
2102632Sstever@eecs.umich.edu
2112632Sstever@eecs.umich.eduVII. Knwon issues
2123918Ssaidi@eecs.umich.edu=================
2133918Ssaidi@eecs.umich.edu
2143940Ssaidi@eecs.umich.edu* For some toolchains, compiling libgem5 with tcmalloc leads to errors
2153918Ssaidi@eecs.umich.edu  ('tcmalloc Attempt to free invalid pointer xxx') when linking libgem5 into a
2163918Ssaidi@eecs.umich.edu  SystemC application.
2173918Ssaidi@eecs.umich.edu* When SystemC was build with --enable-pthreads, SystemC applications linked
2183918Ssaidi@eecs.umich.edu