1# Copyright (c) 2012 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Author: Dam Sunwoo
37#
38# Sample stats config file (AtomicSimpleCPU) for m5stats2streamline.py
39#
40# Stats grouped together will show as grouped in Streamline.
41# E.g.,
42#
43# commit_inst_count =
44#     system.cpu#.commit.committedInsts
45#     system.cpu#.commit.commitSquashedInsts
46#
47# will display the inst counts (committed/squashed) as a stacked line chart.
48# Charts will still be configurable in Streamline.
49
50[PER_CPU_STATS]
51# '#' will be automatically replaced with the correct CPU id.
52
53commit_inst_count =
54    system.cpu#.committedInsts
55
56cycles =
57    system.cpu#.num_busy_cycles
58    system.cpu#.num_idle_cycles
59
60register_access =
61    system.cpu#.num_int_register_reads
62    system.cpu#.num_int_register_writes
63
64mem_refs =
65    system.cpu#.num_mem_refs
66
67inst_breakdown =
68    system.cpu#.num_conditional_control_insts
69    system.cpu#.num_int_insts
70    system.cpu#.num_fp_insts
71    system.cpu#.num_load_insts
72    system.cpu#.num_store_insts
73
74icache =
75    system.il1_cache#.overall_hits::total
76    system.il1_cache#.overall_misses::total
77
78dcache =
79    system.dl1_cache#.overall_hits::total
80    system.dl1_cache#.overall_misses::total
81
82[PER_L2_STATS]
83# '#' will be automatically replaced with the correct L2 id.
84
85l2_cache =
86    system.l2_cache#.overall_hits::total
87    system.l2_cache#.overall_misses::total
88
89[OTHER_STATS]
90# Anything that doesn't belong to CPU or L2 caches
91
92physmem =
93    system.memsys.mem_ctrls.bytes_read::total
94    system.memsys.mem_ctrls.bytes_written::total
95