m5op_alpha.S revision 5505
1278SN/A/* 22188SN/A * Copyright (c) 2003-2006 The Regents of The University of Michigan 3278SN/A * All rights reserved. 4278SN/A * 5278SN/A * Redistribution and use in source and binary forms, with or without 6278SN/A * modification, are permitted provided that the following conditions are 7278SN/A * met: redistributions of source code must retain the above copyright 8278SN/A * notice, this list of conditions and the following disclaimer; 9278SN/A * redistributions in binary form must reproduce the above copyright 10278SN/A * notice, this list of conditions and the following disclaimer in the 11278SN/A * documentation and/or other materials provided with the distribution; 12278SN/A * neither the name of the copyright holders nor the names of its 13278SN/A * contributors may be used to endorse or promote products derived from 14278SN/A * this software without specific prior written permission. 15278SN/A * 16278SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17278SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18278SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19278SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20278SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21278SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22278SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23278SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24278SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25278SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26278SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Nathan Binkert 292665SN/A * Ali Saidi 30278SN/A */ 31278SN/A 32275SN/A#define m5_op 0x01 33287SN/A 344090Ssaidi@eecs.umich.edu#include "m5ops.h" 352188SN/A 36275SN/A#define INST(op, ra, rb, func) \ 372188SN/A .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func)) 382188SN/A 392188SN/A#define LEAF(func) \ 402188SN/A .align 3; \ 412188SN/A .globl func; \ 422188SN/A .ent func; \ 432188SN/Afunc: 442188SN/A 452188SN/A#define RET \ 462188SN/A ret ($26) 472188SN/A 482188SN/A#define END(func) \ 492188SN/A .end func 502188SN/A 515505Snate@binkert.org#define SIMPLE_OP(_f, _o) \ 525505Snate@binkert.org LEAF(_f) \ 535505Snate@binkert.org _o; \ 545505Snate@binkert.org RET; \ 555505Snate@binkert.org END(_f) 565505Snate@binkert.org 57275SN/A#define ARM(reg) INST(m5_op, reg, 0, arm_func) 582188SN/A#define QUIESCE INST(m5_op, 0, 0, quiesce_func) 592188SN/A#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func) 602188SN/A#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func) 612188SN/A#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func) 62287SN/A#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func) 63275SN/A#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func) 642358SN/A#define LOADSYMBOL(reg) INST(m5_op, reg, 0, loadsymbol_func) 65287SN/A#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func) 66287SN/A#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func) 67287SN/A#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func) 68287SN/A#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func) 692188SN/A#define READFILE INST(m5_op, 0, 0, readfile_func) 702188SN/A#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func) 712188SN/A#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func) 722188SN/A#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func) 732188SN/A#define PANIC INST(m5_op, 0, 0, panic_func) 74275SN/A 752188SN/A .set noreorder 76275SN/A 775505Snate@binkert.orgSIMPLE_OP(arm, ARM(16)) 785505Snate@binkert.orgSIMPLE_OP(quiesce, QUIESCE) 795505Snate@binkert.orgSIMPLE_OP(quiesceNs, QUIESCENS(16)) 805505Snate@binkert.orgSIMPLE_OP(quiesceCycle, QUIESCECYC(16)) 815505Snate@binkert.orgSIMPLE_OP(quiesceTime, QUIESCETIME) 825505Snate@binkert.orgSIMPLE_OP(m5_exit, M5EXIT(16)) 835505Snate@binkert.orgSIMPLE_OP(m5_initparam, INITPARAM(0)) 845505Snate@binkert.orgSIMPLE_OP(m5_loadsymbol, LOADSYMBOL(0)) 855505Snate@binkert.orgSIMPLE_OP(m5_reset_stats, RESET_STATS(16, 17)) 865505Snate@binkert.orgSIMPLE_OP(m5_dump_stats, DUMP_STATS(16, 17)) 875505Snate@binkert.orgSIMPLE_OP(m5_dumpreset_stats, DUMPRST_STATS(16, 17)) 885505Snate@binkert.orgSIMPLE_OP(m5_checkpoint, CHECKPOINT(16, 17)) 895505Snate@binkert.orgSIMPLE_OP(m5_readfile, READFILE) 905505Snate@binkert.orgSIMPLE_OP(m5_debugbreak, DEBUGBREAK) 915505Snate@binkert.orgSIMPLE_OP(m5_switchcpu, SWITCHCPU) 925505Snate@binkert.orgSIMPLE_OP(m5_addsymbol, ADDSYMBOL(16, 17)) 935505Snate@binkert.orgSIMPLE_OP(m5_panic, PANIC) 94275SN/A 95