1/*
2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 *          Ali Saidi
30 */
31
32#define m5_op 0x01
33
34#include <gem5/asm/generic/m5ops.h>
35
36#define INST(op, ra, rb, func) \
37        .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func))
38
39#define LEAF(func)    \
40        .align 3;     \
41        .globl  func; \
42        .ent    func; \
43func:
44
45#define RET           \
46        ret     ($26)
47
48#define END(func)     \
49        .end func
50
51#define SIMPLE_OP(_f, _o)       \
52        LEAF(_f)                \
53                _o;             \
54                RET;            \
55        END(_f)
56
57#define ARM(reg) INST(m5_op, reg, 0, M5OP_ARM)
58#define QUIESCE INST(m5_op, 0, 0, M5OP_QUIESCE)
59#define QUIESCENS(r1) INST(m5_op, r1, 0, M5OP_QUIESCE_NS)
60#define QUIESCECYC(r1) INST(m5_op, r1, 0, M5OP_QUIESCE_CYCLE)
61#define QUIESCETIME INST(m5_op, 0, 0, M5OP_QUIESCE_TIME)
62#define RPNS INST(m5_op, 0, 0, M5OP_RPNS)
63#define WAKE_CPU(r1) INST(m5_op, r1, 0, M5OP_WAKE_CPU)
64#define M5EXIT(reg) INST(m5_op, reg, 0, M5OP_EXIT)
65#define INITPARAM(reg) INST(m5_op, reg, 0, M5OP_INIT_PARAM)
66#define LOADSYMBOL(reg) INST(m5_op, reg, 0, M5OP_LOAD_SYMBOL)
67#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, M5OP_RESET_STATS)
68#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, M5OP_DUMP_STATS)
69#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, M5OP_DUMP_RESET_STATS)
70#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, M5OP_CHECKPOINT)
71#define READFILE INST(m5_op, 0, 0, M5OP_READ_FILE)
72#define DEBUGBREAK INST(m5_op, 0, 0, M5OP_DEBUG_BREAK)
73#define SWITCHCPU INST(m5_op, 0, 0, M5OP_SWITCH_CPU)
74#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, M5OP_ADD_SYMBOL)
75#define PANIC INST(m5_op, 0, 0, M5OP_PANIC)
76
77#define AN_BSM INST(m5_op, M5OP_AN_BSM, 0, M5OP_ANNOTATE)
78#define AN_ESM INST(m5_op, M5OP_AN_ESM, 0, M5OP_ANNOTATE)
79#define AN_BEGIN INST(m5_op, M5OP_AN_BEGIN, 0, M5OP_ANNOTATE)
80#define AN_END INST(m5_op, M5OP_AN_END, 0, M5OP_ANNOTATE)
81#define AN_Q INST(m5_op, M5OP_AN_Q, 0, M5OP_ANNOTATE)
82#define AN_RQ INST(m5_op, M5OP_AN_RQ, 0, M5OP_ANNOTATE)
83#define AN_DQ INST(m5_op, M5OP_AN_DQ, 0, M5OP_ANNOTATE)
84#define AN_WF INST(m5_op, M5OP_AN_WF, 0, M5OP_ANNOTATE)
85#define AN_WE INST(m5_op, M5OP_AN_WE, 0, M5OP_ANNOTATE)
86#define AN_WS INST(m5_op, M5OP_AN_WS, 0, M5OP_ANNOTATE)
87#define AN_SQ INST(m5_op, M5OP_AN_SQ, 0, M5OP_ANNOTATE)
88#define AN_AQ INST(m5_op, M5OP_AN_AQ, 0, M5OP_ANNOTATE)
89#define AN_PQ INST(m5_op, M5OP_AN_PQ, 0, M5OP_ANNOTATE)
90#define AN_L INST(m5_op, M5OP_AN_L, 0, M5OP_ANNOTATE)
91#define AN_IDENTIFY INST(m5_op, M5OP_AN_IDENTIFY, 0, M5OP_ANNOTATE)
92#define AN_GETID INST(m5_op, M5OP_AN_GETID, 0, M5OP_ANNOTATE)
93
94
95        .set noreorder
96
97SIMPLE_OP(m5_arm, ARM(16))
98SIMPLE_OP(m5_quiesce, QUIESCE)
99SIMPLE_OP(m5_quiesce_ns, QUIESCENS(16))
100SIMPLE_OP(m5_quiesce_cycle, QUIESCECYC(16))
101SIMPLE_OP(m5_quiesce_time, QUIESCETIME)
102SIMPLE_OP(m5_rpns, RPNS)
103SIMPLE_OP(m5_wake_cpu, WAKE_CPU(16))
104SIMPLE_OP(m5_exit, M5EXIT(16))
105SIMPLE_OP(m5_init_param, INITPARAM(0))
106SIMPLE_OP(m5_load_symbol, LOADSYMBOL(0))
107SIMPLE_OP(m5_reset_stats, RESET_STATS(16, 17))
108SIMPLE_OP(m5_dump_stats, DUMP_STATS(16, 17))
109SIMPLE_OP(m5_dump_reset_stats, DUMPRST_STATS(16, 17))
110SIMPLE_OP(m5_checkpoint, CHECKPOINT(16, 17))
111SIMPLE_OP(m5_read_file, READFILE)
112SIMPLE_OP(m5_debug_break, DEBUGBREAK)
113SIMPLE_OP(m5_switch_cpu, SWITCHCPU)
114SIMPLE_OP(m5_add_symbol, ADDSYMBOL(16, 17))
115SIMPLE_OP(m5_panic, PANIC)
116
117SIMPLE_OP(m5a_bsm, AN_BSM)
118SIMPLE_OP(m5a_esm, AN_ESM)
119SIMPLE_OP(m5a_begin, AN_BEGIN)
120SIMPLE_OP(m5a_end, AN_END)
121SIMPLE_OP(m5a_q, AN_Q)
122SIMPLE_OP(m5a_rq, AN_RQ)
123SIMPLE_OP(m5a_dq, AN_DQ)
124SIMPLE_OP(m5a_wf, AN_WF)
125SIMPLE_OP(m5a_we, AN_WE)
126SIMPLE_OP(m5a_ws, AN_WS)
127SIMPLE_OP(m5a_sq, AN_SQ)
128SIMPLE_OP(m5a_aq, AN_AQ)
129SIMPLE_OP(m5a_pq, AN_PQ)
130SIMPLE_OP(m5a_l, AN_L)
131SIMPLE_OP(m5a_identify, AN_IDENTIFY)
132SIMPLE_OP(m5a_getid, AN_GETID)
133
134