arm-sve.py revision 13759
113759Sgiacomo.gabrielli@arm.comdef upgrader(cpt): 213759Sgiacomo.gabrielli@arm.com """ 313759Sgiacomo.gabrielli@arm.com Update the checkpoint to support initial SVE implemtation. 413759Sgiacomo.gabrielli@arm.com The updater is taking the following steps. 513759Sgiacomo.gabrielli@arm.com 613759Sgiacomo.gabrielli@arm.com 1) Set isa.haveSVE to false 713759Sgiacomo.gabrielli@arm.com 2) Set isa.sveVL to 1 813759Sgiacomo.gabrielli@arm.com 3) Add SVE misc registers in the checkpoint 913759Sgiacomo.gabrielli@arm.com """ 1013759Sgiacomo.gabrielli@arm.com if cpt.get('root','isa') == 'arm': 1113759Sgiacomo.gabrielli@arm.com for sec in cpt.sections(): 1213759Sgiacomo.gabrielli@arm.com import re 1313759Sgiacomo.gabrielli@arm.com # Search for all ISA sections 1413759Sgiacomo.gabrielli@arm.com if re.search('.*sys.*\.cpu.*\.isa$', sec): 1513759Sgiacomo.gabrielli@arm.com 1613759Sgiacomo.gabrielli@arm.com # haveSVE = false 1713759Sgiacomo.gabrielli@arm.com cpt.set(sec, 'haveSVE', 'false') 1813759Sgiacomo.gabrielli@arm.com 1913759Sgiacomo.gabrielli@arm.com # sveVL (sve Vector Length in quadword) = 1 2013759Sgiacomo.gabrielli@arm.com # (This is a dummy value since haveSVE is set to false) 2113759Sgiacomo.gabrielli@arm.com cpt.set(sec, 'sveVL', '1') 2213759Sgiacomo.gabrielli@arm.com 2313759Sgiacomo.gabrielli@arm.com # Updating SVE misc registers (dummy values) 2413759Sgiacomo.gabrielli@arm.com mr = cpt.get(sec, 'miscRegs').split() 2513759Sgiacomo.gabrielli@arm.com if len(mr) == 820: 2613759Sgiacomo.gabrielli@arm.com print "MISCREG_SVE registers already seems to be inserted." 2713759Sgiacomo.gabrielli@arm.com else: 2813759Sgiacomo.gabrielli@arm.com # Replace MISCREG_FREESLOT_1 with MISCREG_ID_AA64ZFR0_EL1 2913759Sgiacomo.gabrielli@arm.com mr[-1] = 0; 3013759Sgiacomo.gabrielli@arm.com 3113759Sgiacomo.gabrielli@arm.com mr.append(0); # Add dummy value for MISCREG_ZCR_EL3 3213759Sgiacomo.gabrielli@arm.com mr.append(0); # Add dummy value for MISCREG_ZCR_EL2 3313759Sgiacomo.gabrielli@arm.com mr.append(0); # Add dummy value for MISCREG_ZCR_EL12 3413759Sgiacomo.gabrielli@arm.com mr.append(0); # Add dummy value for MISCREG_ZCR_EL1 3513759Sgiacomo.gabrielli@arm.com cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr)) 3613759Sgiacomo.gabrielli@arm.com 3713759Sgiacomo.gabrielli@arm.comlegacy_version = 15 38