arm-gicv2-banked-regs.py revision 11941:764760d6c535
15086Sgblack@eecs.umich.edu# Copyright (c) 2016 ARM Limited 25086Sgblack@eecs.umich.edu# All rights reserved 35086Sgblack@eecs.umich.edu# 45086Sgblack@eecs.umich.edu# The license below extends only to copyright in the software and shall 55086Sgblack@eecs.umich.edu# not be construed as granting a license to any other intellectual 65086Sgblack@eecs.umich.edu# property including but not limited to intellectual property relating 75086Sgblack@eecs.umich.edu# to a hardware implementation of the functionality of the software 85086Sgblack@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 95086Sgblack@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 105086Sgblack@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 115086Sgblack@eecs.umich.edu# modified or unmodified, in source code or in binary form. 125086Sgblack@eecs.umich.edu# 135086Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 145086Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 155086Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 165086Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 175086Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 185086Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 195086Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 205086Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 215086Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 225086Sgblack@eecs.umich.edu# this software without specific prior written permission. 235086Sgblack@eecs.umich.edu# 245086Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 255086Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 265086Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 275086Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 285086Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 295086Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 305086Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 315086Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 325086Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 335086Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 345086Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 355086Sgblack@eecs.umich.edu 365086Sgblack@eecs.umich.edu# duplicate banked registers into new per-cpu arrays. 375086Sgblack@eecs.umich.edudef upgrader(cpt): 385086Sgblack@eecs.umich.edu if cpt.get('root','isa') == 'arm': 395086Sgblack@eecs.umich.edu for sec in cpt.sections(): 405086Sgblack@eecs.umich.edu import re 415086Sgblack@eecs.umich.edu 425086Sgblack@eecs.umich.edu if not re.search('\.gic$', sec): 435086Sgblack@eecs.umich.edu continue 445086Sgblack@eecs.umich.edu cpuEnabled = cpt.get(sec, 'cpuEnabled' ).split() 455086Sgblack@eecs.umich.edu 465086Sgblack@eecs.umich.edu intEnabled = cpt.get(sec, 'intEnabled' ).split() 475086Sgblack@eecs.umich.edu pendingInt = cpt.get(sec, 'pendingInt' ).split() 485086Sgblack@eecs.umich.edu activeInt = cpt.get(sec, 'activeInt' ).split() 495086Sgblack@eecs.umich.edu intPriority = cpt.get(sec, 'intPriority').split() 505086Sgblack@eecs.umich.edu cpuTarget = cpt.get(sec, 'cpuTarget' ).split() 515086Sgblack@eecs.umich.edu 525086Sgblack@eecs.umich.edu b_intEnabled = intEnabled[0] 535086Sgblack@eecs.umich.edu b_pendingInt = pendingInt[0] 545086Sgblack@eecs.umich.edu b_activeInt = activeInt[0] 555086Sgblack@eecs.umich.edu 565086Sgblack@eecs.umich.edu del intEnabled[0] 575086Sgblack@eecs.umich.edu del pendingInt[0] 585135Sgblack@eecs.umich.edu del activeInt[0] 595135Sgblack@eecs.umich.edu del intPriority[0:32] # unused; overlapped with bankedIntPriority 605135Sgblack@eecs.umich.edu del cpuTarget[0:32] 615086Sgblack@eecs.umich.edu 625135Sgblack@eecs.umich.edu cpt.set(sec, 'intEnabled', ' '.join(intEnabled)) 635234Sgblack@eecs.umich.edu cpt.set(sec, 'pendingInt', ' '.join(pendingInt)) 645086Sgblack@eecs.umich.edu cpt.set(sec, 'activeInt', ' '.join(activeInt)) 655086Sgblack@eecs.umich.edu cpt.set(sec, 'intPriority',' '.join(intPriority)) 665086Sgblack@eecs.umich.edu cpt.set(sec, 'cpuTarget', ' '.join(cpuTarget)) 675086Sgblack@eecs.umich.edu 685086Sgblack@eecs.umich.edu b_intPriority = cpt.get(sec, '*bankedIntPriority').split() 695086Sgblack@eecs.umich.edu cpt.remove_option(sec, '*bankedIntPriority') 705086Sgblack@eecs.umich.edu 715086Sgblack@eecs.umich.edu for cpu in xrange(0, 255): 725086Sgblack@eecs.umich.edu if cpuEnabled[cpu] == 'true': 735086Sgblack@eecs.umich.edu intPriority = b_intPriority[cpu*32 : (cpu+1)*32] 745086Sgblack@eecs.umich.edu new_sec = "%s.bankedRegs%u" % (sec, cpu) 755135Sgblack@eecs.umich.edu cpt.add_section(new_sec) 765135Sgblack@eecs.umich.edu cpt.set(new_sec, 'intEnabled', b_intEnabled) 775135Sgblack@eecs.umich.edu cpt.set(new_sec, 'pendingInt', b_pendingInt) 785135Sgblack@eecs.umich.edu cpt.set(new_sec, 'activeInt', b_activeInt) 795135Sgblack@eecs.umich.edu cpt.set(new_sec, 'intPriority',' '.join(intPriority)) 805135Sgblack@eecs.umich.edu