config.ini revision 11440:76b5639162af
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu dvfs_handler membus monitor physmem 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 38work_end_ckpt_count=0 39work_end_exit_count=0 40work_item_id=-1 41system_port=system.membus.slave[1] 42 43[system.clk_domain] 44type=SrcClockDomain 45children=voltage_domain 46clock=1000 47domain_id=-1 48eventq_index=0 49init_perf_level=0 50voltage_domain=system.clk_domain.voltage_domain 51 52[system.clk_domain.voltage_domain] 53type=VoltageDomain 54eventq_index=0 55voltage=1.000000 56 57[system.cpu] 58type=TrafficGen 59clk_domain=system.clk_domain 60config_file=tests/quick/se/70.tgen/tgen-dram-ctrl.cfg 61elastic_req=false 62eventq_index=0 63system=system 64port=system.monitor.slave 65 66[system.dvfs_handler] 67type=DVFSHandler 68domains= 69enable=false 70eventq_index=0 71sys_clk_domain=system.clk_domain 72transition_latency=100000000 73 74[system.membus] 75type=NoncoherentXBar 76clk_domain=system.clk_domain 77eventq_index=0 78forward_latency=1 79frontend_latency=2 80response_latency=2 81use_default_range=false 82width=16 83master=system.physmem.port 84slave=system.monitor.master system.system_port 85 86[system.monitor] 87type=CommMonitor 88bandwidth_bins=20 89burst_length_bins=20 90clk_domain=system.clk_domain 91disable_addr_dists=true 92disable_bandwidth_hists=false 93disable_burst_length_hists=false 94disable_itt_dists=false 95disable_latency_hists=false 96disable_outstanding_hists=false 97disable_transaction_hists=false 98eventq_index=0 99itt_bins=20 100itt_max_bin=100000 101latency_bins=20 102outstanding_bins=20 103read_addr_mask=18446744073709551615 104sample_period=1000000000 105system=system 106transaction_bins=20 107write_addr_mask=18446744073709551615 108master=system.membus.slave[0] 109slave=system.cpu.port 110 111[system.physmem] 112type=DRAMCtrl 113IDD0=0.075000 114IDD02=0.000000 115IDD2N=0.050000 116IDD2N2=0.000000 117IDD2P0=0.000000 118IDD2P02=0.000000 119IDD2P1=0.000000 120IDD2P12=0.000000 121IDD3N=0.057000 122IDD3N2=0.000000 123IDD3P0=0.000000 124IDD3P02=0.000000 125IDD3P1=0.000000 126IDD3P12=0.000000 127IDD4R=0.187000 128IDD4R2=0.000000 129IDD4W=0.165000 130IDD4W2=0.000000 131IDD5=0.220000 132IDD52=0.000000 133IDD6=0.000000 134IDD62=0.000000 135VDD=1.500000 136VDD2=0.000000 137activation_limit=4 138addr_mapping=RoRaBaCoCh 139bank_groups_per_rank=0 140banks_per_rank=8 141burst_length=8 142channels=1 143clk_domain=system.clk_domain 144conf_table_reported=true 145device_bus_width=8 146device_rowbuffer_size=1024 147device_size=536870912 148devices_per_rank=8 149dll=true 150eventq_index=0 151in_addr_map=true 152max_accesses_per_row=16 153mem_sched_policy=frfcfs 154min_writes_per_switch=16 155null=false 156page_policy=open_adaptive 157range=0:134217727 158ranks_per_channel=2 159read_buffer_size=32 160static_backend_latency=10000 161static_frontend_latency=10000 162tBURST=5000 163tCCD_L=0 164tCK=1250 165tCL=13750 166tCS=2500 167tRAS=35000 168tRCD=13750 169tREFI=7800000 170tRFC=260000 171tRP=13750 172tRRD=6000 173tRRD_L=0 174tRTP=7500 175tRTW=2500 176tWR=15000 177tWTR=7500 178tXAW=30000 179tXP=0 180tXPDLL=0 181tXS=0 182tXSDLL=0 183write_buffer_size=64 184write_high_thresh_perc=85 185write_low_thresh_perc=50 186port=system.membus.master[0] 187 188