1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=System
13children=clk_domain cpu dvfs_handler membus monitor physmem
14boot_osflags=a
15cache_line_size=64
16clk_domain=system.clk_domain
17default_p_state=UNDEFINED
18eventq_index=0
19exit_on_work_items=false
20init_param=0
21kernel=
22kernel_addr_check=true
23load_addr_mask=1099511627775
24load_offset=0
25mem_mode=timing
26mem_ranges=
27memories=system.physmem
28mmap_using_noreserve=false
29multi_thread=false
30num_work_ids=16
31p_state_clk_gate_bins=20
32p_state_clk_gate_max=1000000000000
33p_state_clk_gate_min=1000
34power_model=Null
35readfile=
36symbolfile=
37thermal_components=
38thermal_model=Null
39work_begin_ckpt_count=0
40work_begin_cpu_id_exit=-1
41work_begin_exit_count=0
42work_cpus_ckpt_count=0
43work_end_ckpt_count=0
44work_end_exit_count=0
45work_item_id=-1
46system_port=system.membus.slave[1]
47
48[system.clk_domain]
49type=SrcClockDomain
50children=voltage_domain
51clock=1000
52domain_id=-1
53eventq_index=0
54init_perf_level=0
55voltage_domain=system.clk_domain.voltage_domain
56
57[system.clk_domain.voltage_domain]
58type=VoltageDomain
59eventq_index=0
60voltage=1.0
61
62[system.cpu]
63type=TrafficGen
64clk_domain=system.clk_domain
65config_file=/work/andsan01/outgoing/gem5/tests/testing/../../tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
66default_p_state=UNDEFINED
67elastic_req=false
68eventq_index=0
69p_state_clk_gate_bins=20
70p_state_clk_gate_max=1000000000000
71p_state_clk_gate_min=1000
72power_model=Null
73progress_check=1000000000
74system=system
75port=system.monitor.slave
76
77[system.dvfs_handler]
78type=DVFSHandler
79domains=
80enable=false
81eventq_index=0
82sys_clk_domain=system.clk_domain
83transition_latency=100000000
84
85[system.membus]
86type=NoncoherentXBar
87clk_domain=system.clk_domain
88default_p_state=UNDEFINED
89eventq_index=0
90forward_latency=1
91frontend_latency=2
92p_state_clk_gate_bins=20
93p_state_clk_gate_max=1000000000000
94p_state_clk_gate_min=1000
95power_model=Null
96response_latency=2
97use_default_range=false
98width=16
99master=system.physmem.port
100slave=system.monitor.master system.system_port
101
102[system.monitor]
103type=CommMonitor
104bandwidth_bins=20
105burst_length_bins=20
106clk_domain=system.clk_domain
107default_p_state=UNDEFINED
108disable_addr_dists=true
109disable_bandwidth_hists=false
110disable_burst_length_hists=false
111disable_itt_dists=false
112disable_latency_hists=false
113disable_outstanding_hists=false
114disable_transaction_hists=false
115eventq_index=0
116itt_bins=20
117itt_max_bin=100000
118latency_bins=20
119outstanding_bins=20
120p_state_clk_gate_bins=20
121p_state_clk_gate_max=1000000000000
122p_state_clk_gate_min=1000
123power_model=Null
124read_addr_mask=18446744073709551615
125sample_period=1000000000
126system=system
127transaction_bins=20
128write_addr_mask=18446744073709551615
129master=system.membus.slave[0]
130slave=system.cpu.port
131
132[system.physmem]
133type=DRAMCtrl
134IDD0=0.055
135IDD02=0.0
136IDD2N=0.032
137IDD2N2=0.0
138IDD2P0=0.0
139IDD2P02=0.0
140IDD2P1=0.032
141IDD2P12=0.0
142IDD3N=0.038
143IDD3N2=0.0
144IDD3P0=0.0
145IDD3P02=0.0
146IDD3P1=0.038
147IDD3P12=0.0
148IDD4R=0.157
149IDD4R2=0.0
150IDD4W=0.125
151IDD4W2=0.0
152IDD5=0.235
153IDD52=0.0
154IDD6=0.02
155IDD62=0.0
156VDD=1.5
157VDD2=0.0
158activation_limit=4
159addr_mapping=RoRaBaCoCh
160bank_groups_per_rank=0
161banks_per_rank=8
162burst_length=8
163channels=1
164clk_domain=system.clk_domain
165conf_table_reported=true
166default_p_state=UNDEFINED
167device_bus_width=8
168device_rowbuffer_size=1024
169device_size=536870912
170devices_per_rank=8
171dll=true
172eventq_index=0
173in_addr_map=true
174kvm_map=true
175max_accesses_per_row=16
176mem_sched_policy=frfcfs
177min_writes_per_switch=16
178null=false
179p_state_clk_gate_bins=20
180p_state_clk_gate_max=1000000000000
181p_state_clk_gate_min=1000
182page_policy=open_adaptive
183power_model=Null
184range=0:134217727:0:0:0:0
185ranks_per_channel=2
186read_buffer_size=32
187static_backend_latency=10000
188static_frontend_latency=10000
189tBURST=5000
190tCCD_L=0
191tCK=1250
192tCL=13750
193tCS=2500
194tRAS=35000
195tRCD=13750
196tREFI=7800000
197tRFC=260000
198tRP=13750
199tRRD=6000
200tRRD_L=0
201tRTP=7500
202tRTW=2500
203tWR=15000
204tWTR=7500
205tXAW=30000
206tXP=6000
207tXPDLL=0
208tXS=270000
209tXSDLL=0
210write_buffer_size=64
211write_high_thresh_perc=85
212write_low_thresh_perc=50
213port=system.membus.master[0]
214
215