config.ini revision 11312
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu dvfs_handler membus monitor physmem 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[1] 40 41[system.clk_domain] 42type=SrcClockDomain 43children=voltage_domain 44clock=1000 45domain_id=-1 46eventq_index=0 47init_perf_level=0 48voltage_domain=system.clk_domain.voltage_domain 49 50[system.clk_domain.voltage_domain] 51type=VoltageDomain 52eventq_index=0 53voltage=1.000000 54 55[system.cpu] 56type=TrafficGen 57clk_domain=system.clk_domain 58config_file=tests/quick/se/70.tgen/tgen-dram-ctrl.cfg 59elastic_req=false 60eventq_index=0 61system=system 62port=system.monitor.slave 63 64[system.dvfs_handler] 65type=DVFSHandler 66domains= 67enable=false 68eventq_index=0 69sys_clk_domain=system.clk_domain 70transition_latency=100000000 71 72[system.membus] 73type=NoncoherentXBar 74clk_domain=system.clk_domain 75eventq_index=0 76forward_latency=1 77frontend_latency=2 78response_latency=2 79use_default_range=false 80width=16 81master=system.physmem.port 82slave=system.monitor.master system.system_port 83 84[system.monitor] 85type=CommMonitor 86bandwidth_bins=20 87burst_length_bins=20 88clk_domain=system.clk_domain 89disable_addr_dists=true 90disable_bandwidth_hists=false 91disable_burst_length_hists=false 92disable_itt_dists=false 93disable_latency_hists=false 94disable_outstanding_hists=false 95disable_transaction_hists=false 96eventq_index=0 97itt_bins=20 98itt_max_bin=100000 99latency_bins=20 100outstanding_bins=20 101read_addr_mask=18446744073709551615 102sample_period=1000000000 103system=system 104transaction_bins=20 105write_addr_mask=18446744073709551615 106master=system.membus.slave[0] 107slave=system.cpu.port 108 109[system.physmem] 110type=DRAMCtrl 111IDD0=0.075000 112IDD02=0.000000 113IDD2N=0.050000 114IDD2N2=0.000000 115IDD2P0=0.000000 116IDD2P02=0.000000 117IDD2P1=0.000000 118IDD2P12=0.000000 119IDD3N=0.057000 120IDD3N2=0.000000 121IDD3P0=0.000000 122IDD3P02=0.000000 123IDD3P1=0.000000 124IDD3P12=0.000000 125IDD4R=0.187000 126IDD4R2=0.000000 127IDD4W=0.165000 128IDD4W2=0.000000 129IDD5=0.220000 130IDD52=0.000000 131IDD6=0.000000 132IDD62=0.000000 133VDD=1.500000 134VDD2=0.000000 135activation_limit=4 136addr_mapping=RoRaBaCoCh 137bank_groups_per_rank=0 138banks_per_rank=8 139burst_length=8 140channels=1 141clk_domain=system.clk_domain 142conf_table_reported=true 143device_bus_width=8 144device_rowbuffer_size=1024 145device_size=536870912 146devices_per_rank=8 147dll=true 148eventq_index=0 149in_addr_map=true 150max_accesses_per_row=16 151mem_sched_policy=frfcfs 152min_writes_per_switch=16 153null=false 154page_policy=open_adaptive 155range=0:134217727 156ranks_per_channel=2 157read_buffer_size=32 158static_backend_latency=10000 159static_frontend_latency=10000 160tBURST=5000 161tCCD_L=0 162tCK=1250 163tCL=13750 164tCS=2500 165tRAS=35000 166tRCD=13750 167tREFI=7800000 168tRFC=260000 169tRP=13750 170tRRD=6000 171tRRD_L=0 172tRTP=7500 173tRTW=2500 174tWR=15000 175tWTR=7500 176tXAW=30000 177tXP=0 178tXPDLL=0 179tXS=0 180tXSDLL=0 181write_buffer_size=64 182write_high_thresh_perc=85 183write_low_thresh_perc=50 184port=system.membus.master[0] 185 186