config.ini revision 11219
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu dvfs_handler membus monitor physmem 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27multi_thread=false 28num_work_ids=16 29readfile= 30symbolfile= 31work_begin_ckpt_count=0 32work_begin_cpu_id_exit=-1 33work_begin_exit_count=0 34work_cpus_ckpt_count=0 35work_end_ckpt_count=0 36work_end_exit_count=0 37work_item_id=-1 38system_port=system.membus.slave[1] 39 40[system.clk_domain] 41type=SrcClockDomain 42children=voltage_domain 43clock=1000 44domain_id=-1 45eventq_index=0 46init_perf_level=0 47voltage_domain=system.clk_domain.voltage_domain 48 49[system.clk_domain.voltage_domain] 50type=VoltageDomain 51eventq_index=0 52voltage=1.000000 53 54[system.cpu] 55type=TrafficGen 56clk_domain=system.clk_domain 57config_file=tests/quick/se/70.tgen/tgen-dram-ctrl.cfg 58elastic_req=false 59eventq_index=0 60system=system 61port=system.monitor.slave 62 63[system.dvfs_handler] 64type=DVFSHandler 65domains= 66enable=false 67eventq_index=0 68sys_clk_domain=system.clk_domain 69transition_latency=100000000 70 71[system.membus] 72type=NoncoherentXBar 73clk_domain=system.clk_domain 74eventq_index=0 75forward_latency=1 76frontend_latency=2 77response_latency=2 78use_default_range=false 79width=16 80master=system.physmem.port 81slave=system.monitor.master system.system_port 82 83[system.monitor] 84type=CommMonitor 85bandwidth_bins=20 86burst_length_bins=20 87clk_domain=system.clk_domain 88disable_addr_dists=true 89disable_bandwidth_hists=false 90disable_burst_length_hists=false 91disable_itt_dists=false 92disable_latency_hists=false 93disable_outstanding_hists=false 94disable_transaction_hists=false 95eventq_index=0 96itt_bins=20 97itt_max_bin=100000 98latency_bins=20 99outstanding_bins=20 100read_addr_mask=18446744073709551615 101sample_period=1000000000 102system=system 103transaction_bins=20 104write_addr_mask=18446744073709551615 105master=system.membus.slave[0] 106slave=system.cpu.port 107 108[system.physmem] 109type=DRAMCtrl 110IDD0=0.075000 111IDD02=0.000000 112IDD2N=0.050000 113IDD2N2=0.000000 114IDD2P0=0.000000 115IDD2P02=0.000000 116IDD2P1=0.000000 117IDD2P12=0.000000 118IDD3N=0.057000 119IDD3N2=0.000000 120IDD3P0=0.000000 121IDD3P02=0.000000 122IDD3P1=0.000000 123IDD3P12=0.000000 124IDD4R=0.187000 125IDD4R2=0.000000 126IDD4W=0.165000 127IDD4W2=0.000000 128IDD5=0.220000 129IDD52=0.000000 130IDD6=0.000000 131IDD62=0.000000 132VDD=1.500000 133VDD2=0.000000 134activation_limit=4 135addr_mapping=RoRaBaCoCh 136bank_groups_per_rank=0 137banks_per_rank=8 138burst_length=8 139channels=1 140clk_domain=system.clk_domain 141conf_table_reported=true 142device_bus_width=8 143device_rowbuffer_size=1024 144device_size=536870912 145devices_per_rank=8 146dll=true 147eventq_index=0 148in_addr_map=true 149max_accesses_per_row=16 150mem_sched_policy=frfcfs 151min_writes_per_switch=16 152null=false 153page_policy=open_adaptive 154range=0:134217727 155ranks_per_channel=2 156read_buffer_size=32 157static_backend_latency=10000 158static_frontend_latency=10000 159tBURST=5000 160tCCD_L=0 161tCK=1250 162tCL=13750 163tCS=2500 164tRAS=35000 165tRCD=13750 166tREFI=7800000 167tRFC=260000 168tRP=13750 169tRRD=6000 170tRRD_L=0 171tRTP=7500 172tRTW=2500 173tWR=15000 174tWTR=7500 175tXAW=30000 176tXP=0 177tXPDLL=0 178tXS=0 179tXSDLL=0 180write_buffer_size=64 181write_high_thresh_perc=85 182write_low_thresh_perc=50 183port=system.membus.master[0] 184 185