config.ini revision 10451
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu dvfs_handler membus monitor physmem 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[1] 37 38[system.clk_domain] 39type=SrcClockDomain 40children=voltage_domain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.clk_domain.voltage_domain 46 47[system.clk_domain.voltage_domain] 48type=VoltageDomain 49eventq_index=0 50voltage=1.000000 51 52[system.cpu] 53type=TrafficGen 54clk_domain=system.clk_domain 55config_file=tests/quick/se/70.tgen/tgen-dram-ctrl.cfg 56elastic_req=false 57eventq_index=0 58system=system 59port=system.monitor.slave 60 61[system.dvfs_handler] 62type=DVFSHandler 63domains= 64enable=false 65eventq_index=0 66sys_clk_domain=system.clk_domain 67transition_latency=100000000 68 69[system.membus] 70type=NoncoherentXBar 71clk_domain=system.clk_domain 72eventq_index=0 73header_cycles=1 74use_default_range=false 75width=16 76master=system.physmem.port 77slave=system.monitor.master system.system_port 78 79[system.monitor] 80type=CommMonitor 81bandwidth_bins=20 82burst_length_bins=20 83clk_domain=system.clk_domain 84disable_addr_dists=true 85disable_bandwidth_hists=false 86disable_burst_length_hists=false 87disable_itt_dists=false 88disable_latency_hists=false 89disable_outstanding_hists=false 90disable_transaction_hists=false 91eventq_index=0 92itt_bins=20 93itt_max_bin=100000 94latency_bins=20 95outstanding_bins=20 96read_addr_mask=18446744073709551615 97sample_period=1000000000 98system=system 99trace_compress=true 100trace_enable=false 101trace_file= 102transaction_bins=20 103write_addr_mask=18446744073709551615 104master=system.membus.slave[0] 105slave=system.cpu.port 106 107[system.physmem] 108type=DRAMCtrl 109IDD0=0.075000 110IDD02=0.000000 111IDD2N=0.050000 112IDD2N2=0.000000 113IDD2P0=0.000000 114IDD2P02=0.000000 115IDD2P1=0.000000 116IDD2P12=0.000000 117IDD3N=0.057000 118IDD3N2=0.000000 119IDD3P0=0.000000 120IDD3P02=0.000000 121IDD3P1=0.000000 122IDD3P12=0.000000 123IDD4R=0.187000 124IDD4R2=0.000000 125IDD4W=0.165000 126IDD4W2=0.000000 127IDD5=0.220000 128IDD52=0.000000 129IDD6=0.000000 130IDD62=0.000000 131VDD=1.500000 132VDD2=0.000000 133activation_limit=4 134addr_mapping=RoRaBaChCo 135bank_groups_per_rank=0 136banks_per_rank=8 137burst_length=8 138channels=1 139clk_domain=system.clk_domain 140conf_table_reported=true 141device_bus_width=8 142device_rowbuffer_size=1024 143devices_per_rank=8 144dll=true 145eventq_index=0 146in_addr_map=true 147max_accesses_per_row=16 148mem_sched_policy=frfcfs 149min_writes_per_switch=16 150null=false 151page_policy=open_adaptive 152range=0:134217727 153ranks_per_channel=2 154read_buffer_size=32 155static_backend_latency=10000 156static_frontend_latency=10000 157tBURST=5000 158tCCD_L=0 159tCK=1250 160tCL=13750 161tCS=2500 162tRAS=35000 163tRCD=13750 164tREFI=7800000 165tRFC=260000 166tRP=13750 167tRRD=6000 168tRRD_L=0 169tRTP=7500 170tRTW=2500 171tWR=15000 172tWTR=7500 173tXAW=30000 174tXP=0 175tXPDLL=0 176tXS=0 177tXSDLL=0 178write_buffer_size=64 179write_high_thresh_perc=85 180write_low_thresh_perc=50 181port=system.membus.master[0] 182 183