config.ini revision 9885
12391SN/A[root] 22391SN/Atype=Root 32391SN/Achildren=system 42391SN/Afull_system=false 52391SN/Atime_sync_enable=false 62391SN/Atime_sync_period=100000000000 72391SN/Atime_sync_spin_threshold=100000000 82391SN/A 92391SN/A[system] 102391SN/Atype=System 112391SN/Achildren=clk_domain cpu membus monitor physmem 122391SN/Aboot_osflags=a 132391SN/Acache_line_size=64 142391SN/Aclk_domain=system.clk_domain 152391SN/Ainit_param=0 162391SN/Akernel= 172391SN/Aload_addr_mask=1099511627775 182391SN/Amem_mode=timing 192391SN/Amem_ranges= 202391SN/Amemories=system.physmem 212391SN/Anum_work_ids=16 222391SN/Areadfile= 232391SN/Asymbolfile= 242391SN/Awork_begin_ckpt_count=0 252391SN/Awork_begin_cpu_id_exit=-1 262391SN/Awork_begin_exit_count=0 272665Ssaidi@eecs.umich.eduwork_cpus_ckpt_count=0 282665Ssaidi@eecs.umich.eduwork_end_ckpt_count=0 292914Ssaidi@eecs.umich.eduwork_end_exit_count=0 302391SN/Awork_item_id=-1 312391SN/Asystem_port=system.membus.slave[1] 322391SN/A 332391SN/A[system.clk_domain] 342391SN/Atype=SrcClockDomain 352391SN/Achildren=voltage_domain 362391SN/Aclock=1000 372391SN/Avoltage_domain=system.clk_domain.voltage_domain 382391SN/A 392391SN/A[system.clk_domain.voltage_domain] 402391SN/Atype=VoltageDomain 412391SN/Avoltage=1.000000 423348Sbinkertn@umich.edu 432391SN/A[system.cpu] 442391SN/Atype=TrafficGen 453879Ssaidi@eecs.umich.educlk_domain=system.clk_domain 462394SN/Aconfig_file=tests/quick/se/70.tgen/tgen-simple-dram.cfg 472391SN/Aelastic_req=false 482415SN/Asystem=system 493348Sbinkertn@umich.eduport=system.monitor.slave 502394SN/A 512391SN/A[system.membus] 522423SN/Atype=NoncoherentBus 532391SN/Aclk_domain=system.clk_domain 543012Ssaidi@eecs.umich.eduheader_cycles=1 553012Ssaidi@eecs.umich.eduuse_default_range=false 562391SN/Awidth=16 573012Ssaidi@eecs.umich.edumaster=system.physmem.port 582391SN/Aslave=system.monitor.master system.system_port 592391SN/A 602391SN/A[system.monitor] 613012Ssaidi@eecs.umich.edutype=CommMonitor 623918Ssaidi@eecs.umich.edubandwidth_bins=20 632391SN/Aburst_length_bins=20 643012Ssaidi@eecs.umich.educlk_domain=system.clk_domain 652391SN/Adisable_addr_dists=true 662391SN/Adisable_bandwidth_hists=false 672391SN/Adisable_burst_length_hists=false 682391SN/Adisable_itt_dists=false 693751Sgblack@eecs.umich.edudisable_latency_hists=false 703751Sgblack@eecs.umich.edudisable_outstanding_hists=false 713751Sgblack@eecs.umich.edudisable_transaction_hists=false 723751Sgblack@eecs.umich.eduitt_bins=20 733012Ssaidi@eecs.umich.eduitt_max_bin=100000 742391SN/Alatency_bins=20 752391SN/Aoutstanding_bins=20 762541SN/Aread_addr_mask=18446744073709551615 772541SN/Asample_period=1000000000 782541SN/Atrace_file= 792541SN/Atransaction_bins=20 802541SN/Awrite_addr_mask=18446744073709551615 812541SN/Amaster=system.membus.slave[0] 822541SN/Aslave=system.cpu.port 832541SN/A 842391SN/A[system.physmem] 852391SN/Atype=SimpleDRAM 863012Ssaidi@eecs.umich.eduactivation_limit=4 873918Ssaidi@eecs.umich.eduaddr_mapping=RaBaChCo 882416SN/Abanks_per_rank=8 892391SN/Aburst_length=8 902391SN/Achannels=1 912391SN/Aclk_domain=system.clk_domain 922391SN/Aconf_table_reported=true 932391SN/Adevice_bus_width=8 943012Ssaidi@eecs.umich.edudevice_rowbuffer_size=1024 953012Ssaidi@eecs.umich.edudevices_per_rank=8 962391SN/Ain_addr_map=true 973012Ssaidi@eecs.umich.edumem_sched_policy=frfcfs 982391SN/Anull=false 992391SN/Apage_policy=open 1002391SN/Arange=0:134217727 1012408SN/Aranks_per_channel=2 1022408SN/Aread_buffer_size=32 1032408SN/Astatic_backend_latency=10000 1042409SN/Astatic_frontend_latency=10000 1052409SN/AtBURST=5000 1062408SN/AtCL=13750 1072408SN/AtRCD=13750 1083012Ssaidi@eecs.umich.edutREFI=7800000 1093349Sbinkertn@umich.edutRFC=300000 1103012Ssaidi@eecs.umich.edutRP=13750 1113012Ssaidi@eecs.umich.edutWTR=7500 1123012Ssaidi@eecs.umich.edutXAW=40000 1132413SN/Awrite_buffer_size=32 1143170Sstever@eecs.umich.eduwrite_thresh_perc=70 1153170Sstever@eecs.umich.eduport=system.membus.master[0] 1163170Sstever@eecs.umich.edu 1173170Sstever@eecs.umich.edu