config.ini revision 10315 
19885SN/A[root]
29885SN/Atype=Root
39885SN/Achildren=system
410036SN/Aeventq_index=0
59885SN/Afull_system=false
610036SN/Asim_quantum=0
79885SN/Atime_sync_enable=false
89885SN/Atime_sync_period=100000000000
99885SN/Atime_sync_spin_threshold=100000000
109885SN/A
119885SN/A[system]
129885SN/Atype=System
1310315Snilay@cs.wisc.educhildren=clk_domain cpu dvfs_handler membus monitor physmem
149885SN/Aboot_osflags=a
159885SN/Acache_line_size=64
169885SN/Aclk_domain=system.clk_domain
1710036SN/Aeventq_index=0
189885SN/Ainit_param=0
199885SN/Akernel=
2010315Snilay@cs.wisc.edukernel_addr_check=true
219885SN/Aload_addr_mask=1099511627775
2210315Snilay@cs.wisc.eduload_offset=0
239885SN/Amem_mode=timing
249885SN/Amem_ranges=
259885SN/Amemories=system.physmem
269885SN/Anum_work_ids=16
279885SN/Areadfile=
289885SN/Asymbolfile=
299885SN/Awork_begin_ckpt_count=0
309885SN/Awork_begin_cpu_id_exit=-1
319885SN/Awork_begin_exit_count=0
329885SN/Awork_cpus_ckpt_count=0
339885SN/Awork_end_ckpt_count=0
349885SN/Awork_end_exit_count=0
359885SN/Awork_item_id=-1
369885SN/Asystem_port=system.membus.slave[1]
379885SN/A
389885SN/A[system.clk_domain]
399885SN/Atype=SrcClockDomain
409885SN/Achildren=voltage_domain
419885SN/Aclock=1000
4210315Snilay@cs.wisc.edudomain_id=-1
4310036SN/Aeventq_index=0
4410315Snilay@cs.wisc.eduinit_perf_level=0
459885SN/Avoltage_domain=system.clk_domain.voltage_domain
469885SN/A
479885SN/A[system.clk_domain.voltage_domain]
489885SN/Atype=VoltageDomain
4910036SN/Aeventq_index=0
509885SN/Avoltage=1.000000
519885SN/A
529885SN/A[system.cpu]
539885SN/Atype=TrafficGen
549885SN/Aclk_domain=system.clk_domain
5510315Snilay@cs.wisc.educonfig_file=tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
569885SN/Aelastic_req=false
5710036SN/Aeventq_index=0
589885SN/Asystem=system
599885SN/Aport=system.monitor.slave
609885SN/A
6110315Snilay@cs.wisc.edu[system.dvfs_handler]
6210315Snilay@cs.wisc.edutype=DVFSHandler
6310315Snilay@cs.wisc.edudomains=
6410315Snilay@cs.wisc.eduenable=false
6510315Snilay@cs.wisc.edueventq_index=0
6610315Snilay@cs.wisc.edusys_clk_domain=system.clk_domain
6710315Snilay@cs.wisc.edutransition_latency=100000000
6810315Snilay@cs.wisc.edu
699885SN/A[system.membus]
709885SN/Atype=NoncoherentBus
719885SN/Aclk_domain=system.clk_domain
7210036SN/Aeventq_index=0
739885SN/Aheader_cycles=1
749885SN/Ause_default_range=false
759885SN/Awidth=16
769885SN/Amaster=system.physmem.port
779885SN/Aslave=system.monitor.master system.system_port
789885SN/A
799885SN/A[system.monitor]
809885SN/Atype=CommMonitor
819885SN/Abandwidth_bins=20
829885SN/Aburst_length_bins=20
839885SN/Aclk_domain=system.clk_domain
849885SN/Adisable_addr_dists=true
859885SN/Adisable_bandwidth_hists=false
869885SN/Adisable_burst_length_hists=false
879885SN/Adisable_itt_dists=false
889885SN/Adisable_latency_hists=false
899885SN/Adisable_outstanding_hists=false
909885SN/Adisable_transaction_hists=false
9110036SN/Aeventq_index=0
929885SN/Aitt_bins=20
939885SN/Aitt_max_bin=100000
949885SN/Alatency_bins=20
959885SN/Aoutstanding_bins=20
969885SN/Aread_addr_mask=18446744073709551615
979885SN/Asample_period=1000000000
9810315Snilay@cs.wisc.edusystem=system
9910315Snilay@cs.wisc.edutrace_compress=true
10010315Snilay@cs.wisc.edutrace_enable=false
1019885SN/Atrace_file=
1029885SN/Atransaction_bins=20
1039885SN/Awrite_addr_mask=18446744073709551615
1049885SN/Amaster=system.membus.slave[0]
1059885SN/Aslave=system.cpu.port
1069885SN/A
1079885SN/A[system.physmem]
10810315Snilay@cs.wisc.edutype=DRAMCtrl
1099885SN/Aactivation_limit=4
11010315Snilay@cs.wisc.eduaddr_mapping=RoRaBaChCo
1119885SN/Abanks_per_rank=8
1129885SN/Aburst_length=8
1139885SN/Achannels=1
1149885SN/Aclk_domain=system.clk_domain
1159885SN/Aconf_table_reported=true
1169885SN/Adevice_bus_width=8
1179885SN/Adevice_rowbuffer_size=1024
1189885SN/Adevices_per_rank=8
11910036SN/Aeventq_index=0
1209885SN/Ain_addr_map=true
12110315Snilay@cs.wisc.edumax_accesses_per_row=16
1229885SN/Amem_sched_policy=frfcfs
12310315Snilay@cs.wisc.edumin_writes_per_switch=16
1249885SN/Anull=false
12510315Snilay@cs.wisc.edupage_policy=open_adaptive
1269885SN/Arange=0:134217727
1279885SN/Aranks_per_channel=2
1289885SN/Aread_buffer_size=32
1299885SN/Astatic_backend_latency=10000
1309885SN/Astatic_frontend_latency=10000
1319885SN/AtBURST=5000
13210315Snilay@cs.wisc.edutCK=1250
1339885SN/AtCL=13750
13410036SN/AtRAS=35000
1359885SN/AtRCD=13750
1369885SN/AtREFI=7800000
13710315Snilay@cs.wisc.edutRFC=260000
1389885SN/AtRP=13750
13910315Snilay@cs.wisc.edutRRD=6000
14010315Snilay@cs.wisc.edutRTP=7500
14110315Snilay@cs.wisc.edutRTW=2500
14210315Snilay@cs.wisc.edutWR=15000
1439885SN/AtWTR=7500
14410315Snilay@cs.wisc.edutXAW=30000
14510315Snilay@cs.wisc.eduwrite_buffer_size=64
14610315Snilay@cs.wisc.eduwrite_high_thresh_perc=85
14710315Snilay@cs.wisc.eduwrite_low_thresh_perc=50
1489885SN/Aport=system.membus.master[0]
1499885SN/A
150