config.ini revision 10036
14202Sbinkertn@umich.edu[root] 24202Sbinkertn@umich.edutype=Root 34202Sbinkertn@umich.educhildren=system 44202Sbinkertn@umich.edueventq_index=0 54202Sbinkertn@umich.edufull_system=false 64202Sbinkertn@umich.edusim_quantum=0 74202Sbinkertn@umich.edutime_sync_enable=false 84202Sbinkertn@umich.edutime_sync_period=100000000000 94202Sbinkertn@umich.edutime_sync_spin_threshold=100000000 104202Sbinkertn@umich.edu 114202Sbinkertn@umich.edu[system] 124202Sbinkertn@umich.edutype=System 134202Sbinkertn@umich.educhildren=clk_domain cpu membus monitor physmem 144202Sbinkertn@umich.eduboot_osflags=a 154202Sbinkertn@umich.educache_line_size=64 164202Sbinkertn@umich.educlk_domain=system.clk_domain 174202Sbinkertn@umich.edueventq_index=0 184202Sbinkertn@umich.eduinit_param=0 194202Sbinkertn@umich.edukernel= 204202Sbinkertn@umich.eduload_addr_mask=1099511627775 214202Sbinkertn@umich.edumem_mode=timing 224202Sbinkertn@umich.edumem_ranges= 234202Sbinkertn@umich.edumemories=system.physmem 244202Sbinkertn@umich.edunum_work_ids=16 254202Sbinkertn@umich.edureadfile= 264202Sbinkertn@umich.edusymbolfile= 274202Sbinkertn@umich.eduwork_begin_ckpt_count=0 284202Sbinkertn@umich.eduwork_begin_cpu_id_exit=-1 294202Sbinkertn@umich.eduwork_begin_exit_count=0 304202Sbinkertn@umich.eduwork_cpus_ckpt_count=0 314202Sbinkertn@umich.eduwork_end_ckpt_count=0 324202Sbinkertn@umich.eduwork_end_exit_count=0 334486Sbinkertn@umich.eduwork_item_id=-1 344486Sbinkertn@umich.edusystem_port=system.membus.slave[1] 354486Sbinkertn@umich.edu 364486Sbinkertn@umich.edu[system.clk_domain] 374486Sbinkertn@umich.edutype=SrcClockDomain 384202Sbinkertn@umich.educhildren=voltage_domain 394202Sbinkertn@umich.educlock=1000 404202Sbinkertn@umich.edueventq_index=0 414202Sbinkertn@umich.eduvoltage_domain=system.clk_domain.voltage_domain 424202Sbinkertn@umich.edu 434202Sbinkertn@umich.edu[system.clk_domain.voltage_domain] 444202Sbinkertn@umich.edutype=VoltageDomain 454202Sbinkertn@umich.edueventq_index=0 464202Sbinkertn@umich.eduvoltage=1.000000 474202Sbinkertn@umich.edu 484202Sbinkertn@umich.edu[system.cpu] 494202Sbinkertn@umich.edutype=TrafficGen 504202Sbinkertn@umich.educlk_domain=system.clk_domain 514202Sbinkertn@umich.educonfig_file=tests/quick/se/70.tgen/tgen-simple-dram.cfg 525192Ssaidi@eecs.umich.eduelastic_req=false 535192Ssaidi@eecs.umich.edueventq_index=0 545192Ssaidi@eecs.umich.edusystem=system 555192Ssaidi@eecs.umich.eduport=system.monitor.slave 565192Ssaidi@eecs.umich.edu 575192Ssaidi@eecs.umich.edu[system.membus] 585192Ssaidi@eecs.umich.edutype=NoncoherentBus 59clk_domain=system.clk_domain 60eventq_index=0 61header_cycles=1 62use_default_range=false 63width=16 64master=system.physmem.port 65slave=system.monitor.master system.system_port 66 67[system.monitor] 68type=CommMonitor 69bandwidth_bins=20 70burst_length_bins=20 71clk_domain=system.clk_domain 72disable_addr_dists=true 73disable_bandwidth_hists=false 74disable_burst_length_hists=false 75disable_itt_dists=false 76disable_latency_hists=false 77disable_outstanding_hists=false 78disable_transaction_hists=false 79eventq_index=0 80itt_bins=20 81itt_max_bin=100000 82latency_bins=20 83outstanding_bins=20 84read_addr_mask=18446744073709551615 85sample_period=1000000000 86trace_file= 87transaction_bins=20 88write_addr_mask=18446744073709551615 89master=system.membus.slave[0] 90slave=system.cpu.port 91 92[system.physmem] 93type=SimpleDRAM 94activation_limit=4 95addr_mapping=RaBaChCo 96banks_per_rank=8 97burst_length=8 98channels=1 99clk_domain=system.clk_domain 100conf_table_reported=true 101device_bus_width=8 102device_rowbuffer_size=1024 103devices_per_rank=8 104eventq_index=0 105in_addr_map=true 106mem_sched_policy=frfcfs 107null=false 108page_policy=open 109range=0:134217727 110ranks_per_channel=2 111read_buffer_size=32 112static_backend_latency=10000 113static_frontend_latency=10000 114tBURST=5000 115tCL=13750 116tRAS=35000 117tRCD=13750 118tREFI=7800000 119tRFC=300000 120tRP=13750 121tRRD=6250 122tWTR=7500 123tXAW=40000 124write_buffer_size=32 125write_high_thresh_perc=70 126write_low_thresh_perc=0 127port=system.membus.master[0] 128 129