1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=System
13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
14boot_osflags=a
15cache_line_size=64
16clk_domain=system.clk_domain
17default_p_state=UNDEFINED
18eventq_index=0
19exit_on_work_items=false
20init_param=0
21kernel=
22kernel_addr_check=true
23load_addr_mask=1099511627775
24load_offset=0
25mem_mode=timing
26mem_ranges=
27memories=system.physmem
28mmap_using_noreserve=false
29multi_thread=false
30num_work_ids=16
31p_state_clk_gate_bins=20
32p_state_clk_gate_max=1000000000000
33p_state_clk_gate_min=1000
34power_model=Null
35readfile=
36symbolfile=
37thermal_components=
38thermal_model=Null
39work_begin_ckpt_count=0
40work_begin_cpu_id_exit=-1
41work_begin_exit_count=0
42work_cpus_ckpt_count=0
43work_end_ckpt_count=0
44work_end_exit_count=0
45work_item_id=-1
46system_port=system.membus.slave[0]
47
48[system.clk_domain]
49type=SrcClockDomain
50clock=1000
51domain_id=-1
52eventq_index=0
53init_perf_level=0
54voltage_domain=system.voltage_domain
55
56[system.cpu]
57type=TimingSimpleCPU
58children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
59branchPred=Null
60checker=Null
61clk_domain=system.cpu_clk_domain
62cpu_id=0
63default_p_state=UNDEFINED
64do_checkpoint_insts=true
65do_quiesce=true
66do_statistics_insts=true
67dtb=system.cpu.dtb
68eventq_index=0
69function_trace=false
70function_trace_start=0
71interrupts=system.cpu.interrupts
72isa=system.cpu.isa
73itb=system.cpu.itb
74max_insts_all_threads=0
75max_insts_any_thread=0
76max_loads_all_threads=0
77max_loads_any_thread=0
78numThreads=1
79p_state_clk_gate_bins=20
80p_state_clk_gate_max=1000000000000
81p_state_clk_gate_min=1000
82power_model=Null
83profile=0
84progress_interval=0
85simpoint_start_insts=
86socket_id=0
87switched_out=false
88syscallRetryLatency=10000
89system=system
90tracer=system.cpu.tracer
91workload=system.cpu.workload
92dcache_port=system.cpu.dcache.cpu_side
93icache_port=system.cpu.icache.cpu_side
94
95[system.cpu.dcache]
96type=Cache
97children=tags
98addr_ranges=0:18446744073709551615:0:0:0:0
99assoc=2
100clk_domain=system.cpu_clk_domain
101clusivity=mostly_incl
102data_latency=2
103default_p_state=UNDEFINED
104demand_mshr_reserve=1
105eventq_index=0
106is_read_only=false
107max_miss_count=0
108mshrs=4
109p_state_clk_gate_bins=20
110p_state_clk_gate_max=1000000000000
111p_state_clk_gate_min=1000
112power_model=Null
113prefetch_on_access=false
114prefetcher=Null
115response_latency=2
116sequential_access=false
117size=262144
118system=system
119tag_latency=2
120tags=system.cpu.dcache.tags
121tgts_per_mshr=20
122write_buffers=8
123writeback_clean=false
124cpu_side=system.cpu.dcache_port
125mem_side=system.cpu.toL2Bus.slave[1]
126
127[system.cpu.dcache.tags]
128type=LRU
129assoc=2
130block_size=64
131clk_domain=system.cpu_clk_domain
132data_latency=2
133default_p_state=UNDEFINED
134eventq_index=0
135p_state_clk_gate_bins=20
136p_state_clk_gate_max=1000000000000
137p_state_clk_gate_min=1000
138power_model=Null
139sequential_access=false
140size=262144
141tag_latency=2
142
143[system.cpu.dtb]
144type=SparcTLB
145eventq_index=0
146size=64
147
148[system.cpu.icache]
149type=Cache
150children=tags
151addr_ranges=0:18446744073709551615:0:0:0:0
152assoc=2
153clk_domain=system.cpu_clk_domain
154clusivity=mostly_incl
155data_latency=2
156default_p_state=UNDEFINED
157demand_mshr_reserve=1
158eventq_index=0
159is_read_only=true
160max_miss_count=0
161mshrs=4
162p_state_clk_gate_bins=20
163p_state_clk_gate_max=1000000000000
164p_state_clk_gate_min=1000
165power_model=Null
166prefetch_on_access=false
167prefetcher=Null
168response_latency=2
169sequential_access=false
170size=131072
171system=system
172tag_latency=2
173tags=system.cpu.icache.tags
174tgts_per_mshr=20
175write_buffers=8
176writeback_clean=true
177cpu_side=system.cpu.icache_port
178mem_side=system.cpu.toL2Bus.slave[0]
179
180[system.cpu.icache.tags]
181type=LRU
182assoc=2
183block_size=64
184clk_domain=system.cpu_clk_domain
185data_latency=2
186default_p_state=UNDEFINED
187eventq_index=0
188p_state_clk_gate_bins=20
189p_state_clk_gate_max=1000000000000
190p_state_clk_gate_min=1000
191power_model=Null
192sequential_access=false
193size=131072
194tag_latency=2
195
196[system.cpu.interrupts]
197type=SparcInterrupts
198eventq_index=0
199
200[system.cpu.isa]
201type=SparcISA
202eventq_index=0
203
204[system.cpu.itb]
205type=SparcTLB
206eventq_index=0
207size=64
208
209[system.cpu.l2cache]
210type=Cache
211children=tags
212addr_ranges=0:18446744073709551615:0:0:0:0
213assoc=8
214clk_domain=system.cpu_clk_domain
215clusivity=mostly_incl
216data_latency=20
217default_p_state=UNDEFINED
218demand_mshr_reserve=1
219eventq_index=0
220is_read_only=false
221max_miss_count=0
222mshrs=20
223p_state_clk_gate_bins=20
224p_state_clk_gate_max=1000000000000
225p_state_clk_gate_min=1000
226power_model=Null
227prefetch_on_access=false
228prefetcher=Null
229response_latency=20
230sequential_access=false
231size=2097152
232system=system
233tag_latency=20
234tags=system.cpu.l2cache.tags
235tgts_per_mshr=12
236write_buffers=8
237writeback_clean=false
238cpu_side=system.cpu.toL2Bus.master[0]
239mem_side=system.membus.slave[1]
240
241[system.cpu.l2cache.tags]
242type=LRU
243assoc=8
244block_size=64
245clk_domain=system.cpu_clk_domain
246data_latency=20
247default_p_state=UNDEFINED
248eventq_index=0
249p_state_clk_gate_bins=20
250p_state_clk_gate_max=1000000000000
251p_state_clk_gate_min=1000
252power_model=Null
253sequential_access=false
254size=2097152
255tag_latency=20
256
257[system.cpu.toL2Bus]
258type=CoherentXBar
259children=snoop_filter
260clk_domain=system.cpu_clk_domain
261default_p_state=UNDEFINED
262eventq_index=0
263forward_latency=0
264frontend_latency=1
265p_state_clk_gate_bins=20
266p_state_clk_gate_max=1000000000000
267p_state_clk_gate_min=1000
268point_of_coherency=false
269power_model=Null
270response_latency=1
271snoop_filter=system.cpu.toL2Bus.snoop_filter
272snoop_response_latency=1
273system=system
274use_default_range=false
275width=32
276master=system.cpu.l2cache.cpu_side
277slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
278
279[system.cpu.toL2Bus.snoop_filter]
280type=SnoopFilter
281eventq_index=0
282lookup_latency=0
283max_capacity=8388608
284system=system
285
286[system.cpu.tracer]
287type=ExeTracer
288eventq_index=0
289
290[system.cpu.workload]
291type=Process
292cmd=vortex bendian.raw
293cwd=build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing
294drivers=
295egid=100
296env=
297errout=cerr
298euid=100
299eventq_index=0
300executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/vortex
301gid=100
302input=cin
303kvmInSE=false
304maxStackSize=67108864
305output=cout
306pgid=100
307pid=100
308ppid=0
309simpoint=0
310system=system
311uid=100
312useArchPT=false
313
314[system.cpu_clk_domain]
315type=SrcClockDomain
316clock=500
317domain_id=-1
318eventq_index=0
319init_perf_level=0
320voltage_domain=system.voltage_domain
321
322[system.dvfs_handler]
323type=DVFSHandler
324domains=
325enable=false
326eventq_index=0
327sys_clk_domain=system.clk_domain
328transition_latency=100000000
329
330[system.membus]
331type=CoherentXBar
332children=snoop_filter
333clk_domain=system.clk_domain
334default_p_state=UNDEFINED
335eventq_index=0
336forward_latency=4
337frontend_latency=3
338p_state_clk_gate_bins=20
339p_state_clk_gate_max=1000000000000
340p_state_clk_gate_min=1000
341point_of_coherency=true
342power_model=Null
343response_latency=2
344snoop_filter=system.membus.snoop_filter
345snoop_response_latency=4
346system=system
347use_default_range=false
348width=16
349master=system.physmem.port
350slave=system.system_port system.cpu.l2cache.mem_side
351
352[system.membus.snoop_filter]
353type=SnoopFilter
354eventq_index=0
355lookup_latency=1
356max_capacity=8388608
357system=system
358
359[system.physmem]
360type=SimpleMemory
361bandwidth=73.000000
362clk_domain=system.clk_domain
363conf_table_reported=true
364default_p_state=UNDEFINED
365eventq_index=0
366in_addr_map=true
367kvm_map=true
368latency=30000
369latency_var=0
370null=false
371p_state_clk_gate_bins=20
372p_state_clk_gate_max=1000000000000
373p_state_clk_gate_min=1000
374power_model=Null
375range=0:134217727:0:0:0:0
376port=system.membus.master[0]
377
378[system.voltage_domain]
379type=VoltageDomain
380eventq_index=0
381voltage=1.000000
382
383