stats.txt revision 11507
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311507SCurtis.Dunham@arm.comsim_seconds 0.000125 # Number of seconds simulated 411507SCurtis.Dunham@arm.comsim_ticks 124523000 # Number of ticks simulated 511507SCurtis.Dunham@arm.comfinal_tick 124523000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711507SCurtis.Dunham@arm.comhost_inst_rate 139641 # Simulator instruction rate (inst/s) 811507SCurtis.Dunham@arm.comhost_op_rate 139640 # Simulator op (including micro ops) rate (op/s) 911507SCurtis.Dunham@arm.comhost_tick_rate 15068671 # Simulator tick rate (ticks/s) 1011507SCurtis.Dunham@arm.comhost_mem_usage 262532 # Number of bytes of host memory used 1111507SCurtis.Dunham@arm.comhost_seconds 8.26 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 1153943 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 1153943 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.inst 5888 # Number of bytes read from this memory 1911507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu2.inst 896 # Number of bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu3.inst 704 # Number of bytes read from this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu3.data 896 # Number of bytes read from this memory 2411507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 45632 # Number of bytes read from this memory 2511507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 24000 # Number of instructions bytes read from this memory 2611507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 5888 # Number of instructions bytes read from this memory 2711507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu2.inst 896 # Number of instructions bytes read from this memory 2811507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu3.inst 704 # Number of instructions bytes read from this memory 2911507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 31488 # Number of instructions bytes read from this memory 3011507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.inst 375 # Number of read requests responded to by this memory 3111507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.data 170 # Number of read requests responded to by this memory 3211507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.inst 92 # Number of read requests responded to by this memory 3311507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory 3411507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu2.inst 14 # Number of read requests responded to by this memory 3511507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory 3611507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu3.inst 11 # Number of read requests responded to by this memory 3711507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu3.data 14 # Number of read requests responded to by this memory 3811507SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 713 # Number of read requests responded to by this memory 3911507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.inst 192735479 # Total read bandwidth from this memory (bytes/s) 4011507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.data 87373417 # Total read bandwidth from this memory (bytes/s) 4111507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.inst 47284437 # Total read bandwidth from this memory (bytes/s) 4211507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.data 11307148 # Total read bandwidth from this memory (bytes/s) 4311507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu2.inst 7195458 # Total read bandwidth from this memory (bytes/s) 4411507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu2.data 7709419 # Total read bandwidth from this memory (bytes/s) 4511507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu3.inst 5653574 # Total read bandwidth from this memory (bytes/s) 4611507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu3.data 7195458 # Total read bandwidth from this memory (bytes/s) 4711507SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 366454390 # Total read bandwidth from this memory (bytes/s) 4811507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu0.inst 192735479 # Instruction read bandwidth from this memory (bytes/s) 4911507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu1.inst 47284437 # Instruction read bandwidth from this memory (bytes/s) 5011507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu2.inst 7195458 # Instruction read bandwidth from this memory (bytes/s) 5111507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu3.inst 5653574 # Instruction read bandwidth from this memory (bytes/s) 5211507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 252868948 # Instruction read bandwidth from this memory (bytes/s) 5311507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.inst 192735479 # Total bandwidth to/from this memory (bytes/s) 5411507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.data 87373417 # Total bandwidth to/from this memory (bytes/s) 5511507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.inst 47284437 # Total bandwidth to/from this memory (bytes/s) 5611507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.data 11307148 # Total bandwidth to/from this memory (bytes/s) 5711507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu2.inst 7195458 # Total bandwidth to/from this memory (bytes/s) 5811507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu2.data 7709419 # Total bandwidth to/from this memory (bytes/s) 5911507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu3.inst 5653574 # Total bandwidth to/from this memory (bytes/s) 6011507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu3.data 7195458 # Total bandwidth to/from this memory (bytes/s) 6111507SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 366454390 # Total bandwidth to/from this memory (bytes/s) 6211507SCurtis.Dunham@arm.comsystem.physmem.readReqs 713 # Number of read requests accepted 6311507SCurtis.Dunham@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 6411507SCurtis.Dunham@arm.comsystem.physmem.readBursts 713 # Number of DRAM read bursts, including those serviced by the write queue 6511507SCurtis.Dunham@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 6611507SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 45632 # Total number of bytes read from DRAM 6711507SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 6811507SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 6911507SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 45632 # Total read bytes from the system interface side 7011507SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 7111507SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 7211507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 7311507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 7411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 120 # Per bank write bursts 7511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 45 # Per bank write bursts 7611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 31 # Per bank write bursts 7711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 62 # Per bank write bursts 7811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 69 # Per bank write bursts 7911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 28 # Per bank write bursts 8011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 19 # Per bank write bursts 8111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 28 # Per bank write bursts 8211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 7 # Per bank write bursts 8311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 31 # Per bank write bursts 8411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 23 # Per bank write bursts 8511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 13 # Per bank write bursts 8611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 70 # Per bank write bursts 8711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 47 # Per bank write bursts 8811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 19 # Per bank write bursts 8911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 101 # Per bank write bursts 9011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 9111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 9211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 9311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 9411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 9511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 9611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 9711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 9811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 9911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 10011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 10111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 10211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 10311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 10411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 10511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 10611507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 10711507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 10811507SCurtis.Dunham@arm.comsystem.physmem.totGap 124288000 # Total gap between requests 10911507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 11011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 11111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 11211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 11311507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 11411507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 11511507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 713 # Read request sizes (log2) 11611507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 11711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 11811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 11911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 12011507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 12111507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 12211507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 433 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 204 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 14811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 14911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 15011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 15111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 15211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 15311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 15411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 15511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 15611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 15711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 15811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 15911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 16011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 16111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 16211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 16311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 16411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 16511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 16611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 16711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 16811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 16911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 17011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 17111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 19011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 19111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 19211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 19311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 19411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 19511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 19611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 19711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 19811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 19911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 20011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 20111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 20211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 20311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 20411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 20511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 20611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 20711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 20811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 20911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 21011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 21111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 21211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 21311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 21411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 21511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 21611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 21711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 21811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 21911507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 171 # Bytes accessed per row activation 22011507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 249.637427 # Bytes accessed per row activation 22111507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 165.941235 # Bytes accessed per row activation 22211507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 244.016459 # Bytes accessed per row activation 22311507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 63 36.84% 36.84% # Bytes accessed per row activation 22411507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 41 23.98% 60.82% # Bytes accessed per row activation 22511507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 28 16.37% 77.19% # Bytes accessed per row activation 22611507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 13 7.60% 84.80% # Bytes accessed per row activation 22711507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 8 4.68% 89.47% # Bytes accessed per row activation 22811507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 8 4.68% 94.15% # Bytes accessed per row activation 22911507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 3 1.75% 95.91% # Bytes accessed per row activation 23011507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 1 0.58% 96.49% # Bytes accessed per row activation 23111507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 6 3.51% 100.00% # Bytes accessed per row activation 23211507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 171 # Bytes accessed per row activation 23311507SCurtis.Dunham@arm.comsystem.physmem.totQLat 6387250 # Total ticks spent queuing 23411507SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 19756000 # Total ticks spent from burst creation until serviced by the DRAM 23511507SCurtis.Dunham@arm.comsystem.physmem.totBusLat 3565000 # Total ticks spent in databus transfers 23611507SCurtis.Dunham@arm.comsystem.physmem.avgQLat 8958.27 # Average queueing delay per DRAM burst 23711507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 23811507SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 27708.27 # Average memory access latency per DRAM burst 23911507SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 366.45 # Average DRAM read bandwidth in MiByte/s 24011507SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 24111507SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 366.45 # Average system read bandwidth in MiByte/s 24211507SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 24311507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 24411507SCurtis.Dunham@arm.comsystem.physmem.busUtil 2.86 # Data bus utilization in percentage 24511507SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 2.86 # Data bus utilization in percentage for reads 24611507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 24711507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing 24811507SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 24911507SCurtis.Dunham@arm.comsystem.physmem.readRowHits 530 # Number of row buffer hits during reads 25011507SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 25111507SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 74.33 # Row buffer hit rate for reads 25211507SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 25311507SCurtis.Dunham@arm.comsystem.physmem.avgGap 174316.97 # Average gap between requests 25411507SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 74.33 # Row buffer hit rate, read and write combined 25511507SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 816480 # Energy for activate commands per rank (pJ) 25611507SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 445500 # Energy for precharge commands per rank (pJ) 25711507SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 2917200 # Energy for read commands per rank (pJ) 25811507SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 25911507SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) 26011507SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 46677870 # Energy for active background per rank (pJ) 26111507SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 29286750 # Energy for precharge background per rank (pJ) 26211507SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 87772200 # Total energy per rank (pJ) 26311507SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 749.845263 # Core power per rank (mW) 26411507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 50196500 # Time in different power states 26511507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 3900000 # Time in different power states 26611507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 26711507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 64717500 # Time in different power states 26811507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 26911507SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 430920 # Energy for activate commands per rank (pJ) 27011507SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 235125 # Energy for precharge commands per rank (pJ) 27111507SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 2215200 # Energy for read commands per rank (pJ) 27211507SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 27311507SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) 27411507SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 50794695 # Energy for active background per rank (pJ) 27511507SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 25675500 # Energy for precharge background per rank (pJ) 27611507SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 86979840 # Total energy per rank (pJ) 27711507SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 743.076065 # Core power per rank (mW) 27811507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 46915750 # Time in different power states 27911507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 3900000 # Time in different power states 28011507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 28111507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 70805750 # Time in different power states 28211507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 28311507SCurtis.Dunham@arm.comsystem.cpu0.branchPred.lookups 98739 # Number of BP lookups 28411507SCurtis.Dunham@arm.comsystem.cpu0.branchPred.condPredicted 94242 # Number of conditional branches predicted 28511507SCurtis.Dunham@arm.comsystem.cpu0.branchPred.condIncorrect 1562 # Number of conditional branches incorrect 28611507SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBLookups 96047 # Number of BTB lookups 28711507SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBHits 0 # Number of BTB hits 28811507SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 28911507SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 29011507SCurtis.Dunham@arm.comsystem.cpu0.branchPred.usedRAS 1131 # Number of times the RAS was used to get a target. 29111507SCurtis.Dunham@arm.comsystem.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. 29211507SCurtis.Dunham@arm.comsystem.cpu0.branchPred.indirectLookups 96047 # Number of indirect predictor lookups. 29311507SCurtis.Dunham@arm.comsystem.cpu0.branchPred.indirectHits 88694 # Number of indirect target hits. 29411507SCurtis.Dunham@arm.comsystem.cpu0.branchPred.indirectMisses 7353 # Number of indirect misses. 29511507SCurtis.Dunham@arm.comsystem.cpu0.branchPredindirectMispredicted 1035 # Number of mispredicted indirect branches. 29611507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 29711507SCurtis.Dunham@arm.comsystem.cpu0.workload.num_syscalls 89 # Number of system calls 29811507SCurtis.Dunham@arm.comsystem.cpu0.numCycles 249047 # number of cpu cycles simulated 29911507SCurtis.Dunham@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 30011507SCurtis.Dunham@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 30111507SCurtis.Dunham@arm.comsystem.cpu0.fetch.icacheStallCycles 23160 # Number of cycles fetch is stalled on an Icache miss 30211507SCurtis.Dunham@arm.comsystem.cpu0.fetch.Insts 582455 # Number of instructions fetch has processed 30311507SCurtis.Dunham@arm.comsystem.cpu0.fetch.Branches 98739 # Number of branches that fetch encountered 30411507SCurtis.Dunham@arm.comsystem.cpu0.fetch.predictedBranches 89825 # Number of branches that fetch has predicted taken 30511507SCurtis.Dunham@arm.comsystem.cpu0.fetch.Cycles 194593 # Number of cycles fetch has run and was not squashing or blocked 30611507SCurtis.Dunham@arm.comsystem.cpu0.fetch.SquashCycles 3423 # Number of cycles fetch has spent squashing 30711507SCurtis.Dunham@arm.comsystem.cpu0.fetch.TlbCycles 66 # Number of cycles fetch has spent waiting for tlb 30811507SCurtis.Dunham@arm.comsystem.cpu0.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 30911507SCurtis.Dunham@arm.comsystem.cpu0.fetch.PendingTrapStallCycles 2218 # Number of stall cycles due to pending traps 31011507SCurtis.Dunham@arm.comsystem.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR 31111507SCurtis.Dunham@arm.comsystem.cpu0.fetch.CacheLines 7952 # Number of cache lines fetched 31211507SCurtis.Dunham@arm.comsystem.cpu0.fetch.IcacheSquashes 853 # Number of outstanding Icache misses that were squashed 31311507SCurtis.Dunham@arm.comsystem.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 31411507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::samples 221760 # Number of instructions fetched each cycle (Total) 31511507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::mean 2.626511 # Number of instructions fetched each cycle (Total) 31611507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::stdev 2.263155 # Number of instructions fetched each cycle (Total) 31711507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 31811507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::0 34377 15.50% 15.50% # Number of instructions fetched each cycle (Total) 31911507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::1 91683 41.34% 56.85% # Number of instructions fetched each cycle (Total) 32011507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::2 679 0.31% 57.15% # Number of instructions fetched each cycle (Total) 32111507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::3 1006 0.45% 57.61% # Number of instructions fetched each cycle (Total) 32211507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::4 517 0.23% 57.84% # Number of instructions fetched each cycle (Total) 32311507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::5 87238 39.34% 97.18% # Number of instructions fetched each cycle (Total) 32411507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::6 730 0.33% 97.51% # Number of instructions fetched each cycle (Total) 32511507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::7 482 0.22% 97.72% # Number of instructions fetched each cycle (Total) 32611507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::8 5048 2.28% 100.00% # Number of instructions fetched each cycle (Total) 32711507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 32811507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 32911507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 33011507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rateDist::total 221760 # Number of instructions fetched each cycle (Total) 33111507SCurtis.Dunham@arm.comsystem.cpu0.fetch.branchRate 0.396467 # Number of branch fetches per cycle 33211507SCurtis.Dunham@arm.comsystem.cpu0.fetch.rate 2.338735 # Number of inst fetches per cycle 33311507SCurtis.Dunham@arm.comsystem.cpu0.decode.IdleCycles 17619 # Number of cycles decode is idle 33411507SCurtis.Dunham@arm.comsystem.cpu0.decode.BlockedCycles 19820 # Number of cycles decode is blocked 33511507SCurtis.Dunham@arm.comsystem.cpu0.decode.RunCycles 181778 # Number of cycles decode is running 33611507SCurtis.Dunham@arm.comsystem.cpu0.decode.UnblockCycles 832 # Number of cycles decode is unblocking 33711507SCurtis.Dunham@arm.comsystem.cpu0.decode.SquashCycles 1711 # Number of cycles decode is squashing 33811507SCurtis.Dunham@arm.comsystem.cpu0.decode.DecodedInsts 564879 # Number of instructions handled by decode 33911507SCurtis.Dunham@arm.comsystem.cpu0.rename.SquashCycles 1711 # Number of cycles rename is squashing 34011507SCurtis.Dunham@arm.comsystem.cpu0.rename.IdleCycles 18296 # Number of cycles rename is idle 34111507SCurtis.Dunham@arm.comsystem.cpu0.rename.BlockCycles 2376 # Number of cycles rename is blocking 34211507SCurtis.Dunham@arm.comsystem.cpu0.rename.serializeStallCycles 16107 # count of cycles rename stalled for serializing inst 34311507SCurtis.Dunham@arm.comsystem.cpu0.rename.RunCycles 181922 # Number of cycles rename is running 34411507SCurtis.Dunham@arm.comsystem.cpu0.rename.UnblockCycles 1348 # Number of cycles rename is unblocking 34511507SCurtis.Dunham@arm.comsystem.cpu0.rename.RenamedInsts 559910 # Number of instructions processed by rename 34611507SCurtis.Dunham@arm.comsystem.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full 34711507SCurtis.Dunham@arm.comsystem.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full 34811507SCurtis.Dunham@arm.comsystem.cpu0.rename.SQFullEvents 869 # Number of times rename has blocked due to SQ full 34911507SCurtis.Dunham@arm.comsystem.cpu0.rename.RenamedOperands 383145 # Number of destination operands rename has renamed 35011507SCurtis.Dunham@arm.comsystem.cpu0.rename.RenameLookups 1115796 # Number of register rename lookups that rename has made 35111507SCurtis.Dunham@arm.comsystem.cpu0.rename.int_rename_lookups 842870 # Number of integer rename lookups 35211507SCurtis.Dunham@arm.comsystem.cpu0.rename.CommittedMaps 364171 # Number of HB maps that are committed 35311507SCurtis.Dunham@arm.comsystem.cpu0.rename.UndoneMaps 18974 # Number of HB maps that are undone due to squashing 35411507SCurtis.Dunham@arm.comsystem.cpu0.rename.serializingInsts 1067 # count of serializing insts renamed 35511507SCurtis.Dunham@arm.comsystem.cpu0.rename.tempSerializingInsts 1095 # count of temporary serializing insts renamed 35611507SCurtis.Dunham@arm.comsystem.cpu0.rename.skidInsts 5253 # count of insts added to the skid buffer 35711507SCurtis.Dunham@arm.comsystem.cpu0.memDep0.insertedLoads 178633 # Number of loads inserted to the mem dependence unit. 35811507SCurtis.Dunham@arm.comsystem.cpu0.memDep0.insertedStores 90222 # Number of stores inserted to the mem dependence unit. 35911507SCurtis.Dunham@arm.comsystem.cpu0.memDep0.conflictingLoads 87104 # Number of conflicting loads. 36011507SCurtis.Dunham@arm.comsystem.cpu0.memDep0.conflictingStores 86835 # Number of conflicting stores. 36111507SCurtis.Dunham@arm.comsystem.cpu0.iq.iqInstsAdded 467056 # Number of instructions added to the IQ (excludes non-spec) 36211507SCurtis.Dunham@arm.comsystem.cpu0.iq.iqNonSpecInstsAdded 1095 # Number of non-speculative instructions added to the IQ 36311507SCurtis.Dunham@arm.comsystem.cpu0.iq.iqInstsIssued 463006 # Number of instructions issued 36411507SCurtis.Dunham@arm.comsystem.cpu0.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued 36511507SCurtis.Dunham@arm.comsystem.cpu0.iq.iqSquashedInstsExamined 16506 # Number of squashed instructions iterated over during squash; mainly for profiling 36611507SCurtis.Dunham@arm.comsystem.cpu0.iq.iqSquashedOperandsExamined 13395 # Number of squashed operands that are examined and possibly removed from graph 36711507SCurtis.Dunham@arm.comsystem.cpu0.iq.iqSquashedNonSpecRemoved 536 # Number of squashed non-spec instructions that were removed 36811507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::samples 221760 # Number of insts issued each cycle 36911507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::mean 2.087870 # Number of insts issued each cycle 37011507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::stdev 1.110825 # Number of insts issued each cycle 37111507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 37211507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::0 37234 16.79% 16.79% # Number of insts issued each cycle 37311507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::1 4446 2.00% 18.80% # Number of insts issued each cycle 37411507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::2 88426 39.87% 58.67% # Number of insts issued each cycle 37511507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::3 88102 39.73% 98.40% # Number of insts issued each cycle 37611507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::4 1676 0.76% 99.15% # Number of insts issued each cycle 37711507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::5 983 0.44% 99.60% # Number of insts issued each cycle 37811507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::6 568 0.26% 99.85% # Number of insts issued each cycle 37911507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::7 225 0.10% 99.95% # Number of insts issued each cycle 38011507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::8 100 0.05% 100.00% # Number of insts issued each cycle 38111507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 38211507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 38311507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 38411507SCurtis.Dunham@arm.comsystem.cpu0.iq.issued_per_cycle::total 221760 # Number of insts issued each cycle 38511507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 38611507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::IntAlu 134 40.48% 40.48% # attempts to use FU when none available 38711507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::IntMult 0 0.00% 40.48% # attempts to use FU when none available 38811507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::IntDiv 0 0.00% 40.48% # attempts to use FU when none available 38911507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.48% # attempts to use FU when none available 39011507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.48% # attempts to use FU when none available 39111507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.48% # attempts to use FU when none available 39211507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::FloatMult 0 0.00% 40.48% # attempts to use FU when none available 39311507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.48% # attempts to use FU when none available 39411507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.48% # attempts to use FU when none available 39511507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.48% # attempts to use FU when none available 39611507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.48% # attempts to use FU when none available 39711507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.48% # attempts to use FU when none available 39811507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.48% # attempts to use FU when none available 39911507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.48% # attempts to use FU when none available 40011507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.48% # attempts to use FU when none available 40111507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdMult 0 0.00% 40.48% # attempts to use FU when none available 40211507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.48% # attempts to use FU when none available 40311507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdShift 0 0.00% 40.48% # attempts to use FU when none available 40411507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.48% # attempts to use FU when none available 40511507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.48% # attempts to use FU when none available 40611507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.48% # attempts to use FU when none available 40711507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.48% # attempts to use FU when none available 40811507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.48% # attempts to use FU when none available 40911507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.48% # attempts to use FU when none available 41011507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.48% # attempts to use FU when none available 41111507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.48% # attempts to use FU when none available 41211507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.48% # attempts to use FU when none available 41311507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.48% # attempts to use FU when none available 41411507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.48% # attempts to use FU when none available 41511507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::MemRead 76 22.96% 63.44% # attempts to use FU when none available 41611507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::MemWrite 121 36.56% 100.00% # attempts to use FU when none available 41711507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 41811507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 41911507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 42011507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::IntAlu 195503 42.22% 42.22% # Type of FU issued 42111507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.22% # Type of FU issued 42211507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.22% # Type of FU issued 42311507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.22% # Type of FU issued 42411507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.22% # Type of FU issued 42511507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.22% # Type of FU issued 42611507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.22% # Type of FU issued 42711507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.22% # Type of FU issued 42811507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.22% # Type of FU issued 42911507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.22% # Type of FU issued 43011507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.22% # Type of FU issued 43111507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.22% # Type of FU issued 43211507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.22% # Type of FU issued 43311507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.22% # Type of FU issued 43411507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.22% # Type of FU issued 43511507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.22% # Type of FU issued 43611507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.22% # Type of FU issued 43711507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.22% # Type of FU issued 43811507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.22% # Type of FU issued 43911507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.22% # Type of FU issued 44011507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.22% # Type of FU issued 44111507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.22% # Type of FU issued 44211507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.22% # Type of FU issued 44311507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.22% # Type of FU issued 44411507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.22% # Type of FU issued 44511507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.22% # Type of FU issued 44611507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.22% # Type of FU issued 44711507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.22% # Type of FU issued 44811507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.22% # Type of FU issued 44911507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::MemRead 178044 38.45% 80.68% # Type of FU issued 45011507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::MemWrite 89459 19.32% 100.00% # Type of FU issued 45111507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 45211507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 45311507SCurtis.Dunham@arm.comsystem.cpu0.iq.FU_type_0::total 463006 # Type of FU issued 45411507SCurtis.Dunham@arm.comsystem.cpu0.iq.rate 1.859111 # Inst issue rate 45511507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_busy_cnt 331 # FU busy when requested 45611507SCurtis.Dunham@arm.comsystem.cpu0.iq.fu_busy_rate 0.000715 # FU busy rate (busy events/executed inst) 45711507SCurtis.Dunham@arm.comsystem.cpu0.iq.int_inst_queue_reads 1148221 # Number of integer instruction queue reads 45811507SCurtis.Dunham@arm.comsystem.cpu0.iq.int_inst_queue_writes 484707 # Number of integer instruction queue writes 45911507SCurtis.Dunham@arm.comsystem.cpu0.iq.int_inst_queue_wakeup_accesses 460421 # Number of integer instruction queue wakeup accesses 46011507SCurtis.Dunham@arm.comsystem.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 46111507SCurtis.Dunham@arm.comsystem.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 46211507SCurtis.Dunham@arm.comsystem.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 46311507SCurtis.Dunham@arm.comsystem.cpu0.iq.int_alu_accesses 463337 # Number of integer alu accesses 46411507SCurtis.Dunham@arm.comsystem.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses 46511507SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.forwLoads 86583 # Number of loads that had data forwarded from stores 46611507SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 46711507SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.squashedLoads 2958 # Number of loads squashed 46811507SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed 46911507SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.memOrderViolation 52 # Number of memory ordering violations 47011507SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.squashedStores 1878 # Number of stores squashed 47111507SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 47211507SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 47311507SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 47411507SCurtis.Dunham@arm.comsystem.cpu0.iew.lsq.thread0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked 47511507SCurtis.Dunham@arm.comsystem.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 47611507SCurtis.Dunham@arm.comsystem.cpu0.iew.iewSquashCycles 1711 # Number of cycles IEW is squashing 47711507SCurtis.Dunham@arm.comsystem.cpu0.iew.iewBlockCycles 2375 # Number of cycles IEW is blocking 47811507SCurtis.Dunham@arm.comsystem.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking 47911507SCurtis.Dunham@arm.comsystem.cpu0.iew.iewDispatchedInsts 555874 # Number of instructions dispatched to IQ 48011507SCurtis.Dunham@arm.comsystem.cpu0.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch 48111507SCurtis.Dunham@arm.comsystem.cpu0.iew.iewDispLoadInsts 178633 # Number of dispatched load instructions 48211507SCurtis.Dunham@arm.comsystem.cpu0.iew.iewDispStoreInsts 90222 # Number of dispatched store instructions 48311507SCurtis.Dunham@arm.comsystem.cpu0.iew.iewDispNonSpecInsts 980 # Number of dispatched non-speculative instructions 48411507SCurtis.Dunham@arm.comsystem.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall 48511507SCurtis.Dunham@arm.comsystem.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 48611507SCurtis.Dunham@arm.comsystem.cpu0.iew.memOrderViolationEvents 52 # Number of memory order violations 48711507SCurtis.Dunham@arm.comsystem.cpu0.iew.predictedTakenIncorrect 232 # Number of branches that were predicted taken incorrectly 48811507SCurtis.Dunham@arm.comsystem.cpu0.iew.predictedNotTakenIncorrect 1679 # Number of branches that were predicted not taken incorrectly 48911507SCurtis.Dunham@arm.comsystem.cpu0.iew.branchMispredicts 1911 # Number of branch mispredicts detected at execute 49011507SCurtis.Dunham@arm.comsystem.cpu0.iew.iewExecutedInsts 461536 # Number of executed instructions 49111507SCurtis.Dunham@arm.comsystem.cpu0.iew.iewExecLoadInsts 177679 # Number of load instructions executed 49211507SCurtis.Dunham@arm.comsystem.cpu0.iew.iewExecSquashedInsts 1470 # Number of squashed instructions skipped in execute 49311507SCurtis.Dunham@arm.comsystem.cpu0.iew.exec_swp 0 # number of swp insts executed 49411507SCurtis.Dunham@arm.comsystem.cpu0.iew.exec_nop 87723 # number of nop insts executed 49511507SCurtis.Dunham@arm.comsystem.cpu0.iew.exec_refs 266935 # number of memory reference insts executed 49611507SCurtis.Dunham@arm.comsystem.cpu0.iew.exec_branches 91696 # Number of branches executed 49711507SCurtis.Dunham@arm.comsystem.cpu0.iew.exec_stores 89256 # Number of stores executed 49811507SCurtis.Dunham@arm.comsystem.cpu0.iew.exec_rate 1.853208 # Inst execution rate 49911507SCurtis.Dunham@arm.comsystem.cpu0.iew.wb_sent 460886 # cumulative count of insts sent to commit 50011507SCurtis.Dunham@arm.comsystem.cpu0.iew.wb_count 460421 # cumulative count of insts written-back 50111507SCurtis.Dunham@arm.comsystem.cpu0.iew.wb_producers 273043 # num instructions producing a value 50211507SCurtis.Dunham@arm.comsystem.cpu0.iew.wb_consumers 276596 # num instructions consuming a value 50311507SCurtis.Dunham@arm.comsystem.cpu0.iew.wb_rate 1.848731 # insts written-back per cycle 50411507SCurtis.Dunham@arm.comsystem.cpu0.iew.wb_fanout 0.987155 # average fanout of values written-back 50511507SCurtis.Dunham@arm.comsystem.cpu0.commit.commitSquashedInsts 17182 # The number of squashed insts skipped by commit 50611507SCurtis.Dunham@arm.comsystem.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards 50711507SCurtis.Dunham@arm.comsystem.cpu0.commit.branchMispredicts 1562 # The number of times a branch was mispredicted 50811507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::samples 218398 # Number of insts commited each cycle 50911507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::mean 2.466176 # Number of insts commited each cycle 51011507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::stdev 2.142349 # Number of insts commited each cycle 51111507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 51211507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::0 37197 17.03% 17.03% # Number of insts commited each cycle 51311507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::1 90473 41.43% 58.46% # Number of insts commited each cycle 51411507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::2 2051 0.94% 59.40% # Number of insts commited each cycle 51511507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::3 612 0.28% 59.68% # Number of insts commited each cycle 51611507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::4 499 0.23% 59.91% # Number of insts commited each cycle 51711507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::5 86381 39.55% 99.46% # Number of insts commited each cycle 51811507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::6 448 0.21% 99.66% # Number of insts commited each cycle 51911507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::7 288 0.13% 99.79% # Number of insts commited each cycle 52011507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::8 449 0.21% 100.00% # Number of insts commited each cycle 52111507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 52211507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 52311507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 52411507SCurtis.Dunham@arm.comsystem.cpu0.commit.committed_per_cycle::total 218398 # Number of insts commited each cycle 52511507SCurtis.Dunham@arm.comsystem.cpu0.commit.committedInsts 538608 # Number of instructions committed 52611507SCurtis.Dunham@arm.comsystem.cpu0.commit.committedOps 538608 # Number of ops (including micro ops) committed 52711507SCurtis.Dunham@arm.comsystem.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 52811507SCurtis.Dunham@arm.comsystem.cpu0.commit.refs 264019 # Number of memory references committed 52911507SCurtis.Dunham@arm.comsystem.cpu0.commit.loads 175675 # Number of loads committed 53011507SCurtis.Dunham@arm.comsystem.cpu0.commit.membars 84 # Number of memory barriers committed 53111507SCurtis.Dunham@arm.comsystem.cpu0.commit.branches 90231 # Number of branches committed 53211507SCurtis.Dunham@arm.comsystem.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. 53311507SCurtis.Dunham@arm.comsystem.cpu0.commit.int_insts 362502 # Number of committed integer instructions. 53411507SCurtis.Dunham@arm.comsystem.cpu0.commit.function_calls 223 # Number of function calls committed. 53511507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::No_OpClass 86963 16.15% 16.15% # Class of committed instruction 53611507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::IntAlu 187542 34.82% 50.97% # Class of committed instruction 53711507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::IntMult 0 0.00% 50.97% # Class of committed instruction 53811507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.97% # Class of committed instruction 53911507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.97% # Class of committed instruction 54011507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.97% # Class of committed instruction 54111507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.97% # Class of committed instruction 54211507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.97% # Class of committed instruction 54311507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.97% # Class of committed instruction 54411507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.97% # Class of committed instruction 54511507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.97% # Class of committed instruction 54611507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.97% # Class of committed instruction 54711507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.97% # Class of committed instruction 54811507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.97% # Class of committed instruction 54911507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.97% # Class of committed instruction 55011507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.97% # Class of committed instruction 55111507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.97% # Class of committed instruction 55211507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.97% # Class of committed instruction 55311507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.97% # Class of committed instruction 55411507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.97% # Class of committed instruction 55511507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.97% # Class of committed instruction 55611507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.97% # Class of committed instruction 55711507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.97% # Class of committed instruction 55811507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.97% # Class of committed instruction 55911507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.97% # Class of committed instruction 56011507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.97% # Class of committed instruction 56111507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.97% # Class of committed instruction 56211507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.97% # Class of committed instruction 56311507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.97% # Class of committed instruction 56411507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.97% # Class of committed instruction 56511507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::MemRead 175759 32.63% 83.60% # Class of committed instruction 56611507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::MemWrite 88344 16.40% 100.00% # Class of committed instruction 56711507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 56811507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 56911507SCurtis.Dunham@arm.comsystem.cpu0.commit.op_class_0::total 538608 # Class of committed instruction 57011507SCurtis.Dunham@arm.comsystem.cpu0.commit.bw_lim_events 449 # number cycles where commit BW limit reached 57111507SCurtis.Dunham@arm.comsystem.cpu0.rob.rob_reads 772578 # The number of ROB reads 57211507SCurtis.Dunham@arm.comsystem.cpu0.rob.rob_writes 1114998 # The number of ROB writes 57311507SCurtis.Dunham@arm.comsystem.cpu0.timesIdled 315 # Number of times that the entire CPU went into an idle state and unscheduled itself 57411507SCurtis.Dunham@arm.comsystem.cpu0.idleCycles 27287 # Total number of cycles that the CPU has spent unscheduled due to idling 57511507SCurtis.Dunham@arm.comsystem.cpu0.committedInsts 451561 # Number of Instructions Simulated 57611507SCurtis.Dunham@arm.comsystem.cpu0.committedOps 451561 # Number of Ops (including micro ops) Simulated 57711507SCurtis.Dunham@arm.comsystem.cpu0.cpi 0.551525 # CPI: Cycles Per Instruction 57811507SCurtis.Dunham@arm.comsystem.cpu0.cpi_total 0.551525 # CPI: Total CPI of All Threads 57911507SCurtis.Dunham@arm.comsystem.cpu0.ipc 1.813156 # IPC: Instructions Per Cycle 58011507SCurtis.Dunham@arm.comsystem.cpu0.ipc_total 1.813156 # IPC: Total IPC of All Threads 58111507SCurtis.Dunham@arm.comsystem.cpu0.int_regfile_reads 825039 # number of integer regfile reads 58211507SCurtis.Dunham@arm.comsystem.cpu0.int_regfile_writes 371919 # number of integer regfile writes 58311507SCurtis.Dunham@arm.comsystem.cpu0.fp_regfile_reads 192 # number of floating regfile reads 58411507SCurtis.Dunham@arm.comsystem.cpu0.misc_regfile_reads 269052 # number of misc regfile reads 58511507SCurtis.Dunham@arm.comsystem.cpu0.misc_regfile_writes 564 # number of misc regfile writes 58611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 2 # number of replacements 58711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tagsinuse 142.724931 # Cycle average of tags in use 58811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.total_refs 178078 # Total number of references to valid blocks. 58911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks. 59011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.avg_refs 1035.337209 # Average number of references to valid blocks. 59111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 59211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 142.724931 # Average occupied blocks per requestor 59311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.278760 # Average percentage of cache occupancy 59411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.278760 # Average percentage of cache occupancy 59511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id 59611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 59711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 59811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id 59911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id 60011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tag_accesses 717658 # Number of tag accesses 60111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 717658 # Number of data accesses 60211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 90413 # number of ReadReq hits 60311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 90413 # number of ReadReq hits 60411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 87748 # number of WriteReq hits 60511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::total 87748 # number of WriteReq hits 60611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_hits::cpu0.data 23 # number of SwapReq hits 60711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_hits::total 23 # number of SwapReq hits 60811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 178161 # number of demand (read+write) hits 60911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::total 178161 # number of demand (read+write) hits 61011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 178161 # number of overall hits 61111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::total 178161 # number of overall hits 61211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 578 # number of ReadReq misses 61311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 578 # number of ReadReq misses 61411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 554 # number of WriteReq misses 61511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::total 554 # number of WriteReq misses 61611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_misses::cpu0.data 19 # number of SwapReq misses 61711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_misses::total 19 # number of SwapReq misses 61811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 1132 # number of demand (read+write) misses 61911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::total 1132 # number of demand (read+write) misses 62011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 1132 # number of overall misses 62111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::total 1132 # number of overall misses 62211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 18168000 # number of ReadReq miss cycles 62311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 18168000 # number of ReadReq miss cycles 62411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36152490 # number of WriteReq miss cycles 62511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 36152490 # number of WriteReq miss cycles 62611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_miss_latency::cpu0.data 521000 # number of SwapReq miss cycles 62711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_miss_latency::total 521000 # number of SwapReq miss cycles 62811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 54320490 # number of demand (read+write) miss cycles 62911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::total 54320490 # number of demand (read+write) miss cycles 63011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 54320490 # number of overall miss cycles 63111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::total 54320490 # number of overall miss cycles 63211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 90991 # number of ReadReq accesses(hits+misses) 63311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 90991 # number of ReadReq accesses(hits+misses) 63411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 88302 # number of WriteReq accesses(hits+misses) 63511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 88302 # number of WriteReq accesses(hits+misses) 63611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) 63711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) 63811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 179293 # number of demand (read+write) accesses 63911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::total 179293 # number of demand (read+write) accesses 64011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 179293 # number of overall (read+write) accesses 64111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::total 179293 # number of overall (read+write) accesses 64211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006352 # miss rate for ReadReq accesses 64311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.006352 # miss rate for ReadReq accesses 64411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006274 # miss rate for WriteReq accesses 64511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.006274 # miss rate for WriteReq accesses 64611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.452381 # miss rate for SwapReq accesses 64711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_miss_rate::total 0.452381 # miss rate for SwapReq accesses 64811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.006314 # miss rate for demand accesses 64911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.006314 # miss rate for demand accesses 65011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.006314 # miss rate for overall accesses 65111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.006314 # miss rate for overall accesses 65211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31432.525952 # average ReadReq miss latency 65311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 31432.525952 # average ReadReq miss latency 65411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65257.202166 # average WriteReq miss latency 65511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 65257.202166 # average WriteReq miss latency 65611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27421.052632 # average SwapReq miss latency 65711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_avg_miss_latency::total 27421.052632 # average SwapReq miss latency 65811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47986.298587 # average overall miss latency 65911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 47986.298587 # average overall miss latency 66011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47986.298587 # average overall miss latency 66111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 47986.298587 # average overall miss latency 66211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 832 # number of cycles access was blocked 66311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 66411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked 66511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 66611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.818182 # average number of cycles each access was blocked 66711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 66811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::writebacks 1 # number of writebacks 66911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::total 1 # number of writebacks 67011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 385 # number of ReadReq MSHR hits 67111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 385 # number of ReadReq MSHR hits 67211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 387 # number of WriteReq MSHR hits 67311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 387 # number of WriteReq MSHR hits 67411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 772 # number of demand (read+write) MSHR hits 67511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 772 # number of demand (read+write) MSHR hits 67611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 772 # number of overall MSHR hits 67711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 772 # number of overall MSHR hits 67811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 193 # number of ReadReq MSHR misses 67911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 193 # number of ReadReq MSHR misses 68011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 167 # number of WriteReq MSHR misses 68111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 167 # number of WriteReq MSHR misses 68211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 19 # number of SwapReq MSHR misses 68311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_misses::total 19 # number of SwapReq MSHR misses 68411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses 68511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses 68611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses 68711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses 68811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7230000 # number of ReadReq MSHR miss cycles 68911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 7230000 # number of ReadReq MSHR miss cycles 69011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8425000 # number of WriteReq MSHR miss cycles 69111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 8425000 # number of WriteReq MSHR miss cycles 69211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 502000 # number of SwapReq MSHR miss cycles 69311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_miss_latency::total 502000 # number of SwapReq MSHR miss cycles 69411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15655000 # number of demand (read+write) MSHR miss cycles 69511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 15655000 # number of demand (read+write) MSHR miss cycles 69611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15655000 # number of overall MSHR miss cycles 69711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 15655000 # number of overall MSHR miss cycles 69811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002121 # mshr miss rate for ReadReq accesses 69911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002121 # mshr miss rate for ReadReq accesses 70011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001891 # mshr miss rate for WriteReq accesses 70111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001891 # mshr miss rate for WriteReq accesses 70211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.452381 # mshr miss rate for SwapReq accesses 70311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.452381 # mshr miss rate for SwapReq accesses 70411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002008 # mshr miss rate for demand accesses 70511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.002008 # mshr miss rate for demand accesses 70611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002008 # mshr miss rate for overall accesses 70711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.002008 # mshr miss rate for overall accesses 70811507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37461.139896 # average ReadReq mshr miss latency 70911507SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37461.139896 # average ReadReq mshr miss latency 71011507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 50449.101796 # average WriteReq mshr miss latency 71111507SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 50449.101796 # average WriteReq mshr miss latency 71211507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26421.052632 # average SwapReq mshr miss latency 71311507SCurtis.Dunham@arm.comsystem.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26421.052632 # average SwapReq mshr miss latency 71411507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 43486.111111 # average overall mshr miss latency 71511507SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 43486.111111 # average overall mshr miss latency 71611507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 43486.111111 # average overall mshr miss latency 71711507SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 43486.111111 # average overall mshr miss latency 71811507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 394 # number of replacements 71911507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tagsinuse 248.905102 # Cycle average of tags in use 72011507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.total_refs 7041 # Total number of references to valid blocks. 72111507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 695 # Sample count of references to valid blocks. 72211507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.avg_refs 10.130935 # Average number of references to valid blocks. 72311507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 72411507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 248.905102 # Average occupied blocks per requestor 72511507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.486143 # Average percentage of cache occupancy 72611507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.486143 # Average percentage of cache occupancy 72711507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id 72811507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 72911507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id 73011507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id 73111507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 0.587891 # Percentage of cache occupancy per task id 73211507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tag_accesses 8647 # Number of tag accesses 73311507SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.data_accesses 8647 # Number of data accesses 73411507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 7041 # number of ReadReq hits 73511507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::total 7041 # number of ReadReq hits 73611507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 7041 # number of demand (read+write) hits 73711507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::total 7041 # number of demand (read+write) hits 73811507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 7041 # number of overall hits 73911507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::total 7041 # number of overall hits 74011507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 911 # number of ReadReq misses 74111507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::total 911 # number of ReadReq misses 74211507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 911 # number of demand (read+write) misses 74311507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 911 # number of demand (read+write) misses 74411507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 911 # number of overall misses 74511507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 911 # number of overall misses 74611507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 43691000 # number of ReadReq miss cycles 74711507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 43691000 # number of ReadReq miss cycles 74811507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 43691000 # number of demand (read+write) miss cycles 74911507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::total 43691000 # number of demand (read+write) miss cycles 75011507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 43691000 # number of overall miss cycles 75111507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::total 43691000 # number of overall miss cycles 75211507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 7952 # number of ReadReq accesses(hits+misses) 75311507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 7952 # number of ReadReq accesses(hits+misses) 75411507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 7952 # number of demand (read+write) accesses 75511507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 7952 # number of demand (read+write) accesses 75611507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 7952 # number of overall (read+write) accesses 75711507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 7952 # number of overall (read+write) accesses 75811507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114562 # miss rate for ReadReq accesses 75911507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.114562 # miss rate for ReadReq accesses 76011507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.114562 # miss rate for demand accesses 76111507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.114562 # miss rate for demand accesses 76211507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.114562 # miss rate for overall accesses 76311507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.114562 # miss rate for overall accesses 76411507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47959.385291 # average ReadReq miss latency 76511507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 47959.385291 # average ReadReq miss latency 76611507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47959.385291 # average overall miss latency 76711507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 47959.385291 # average overall miss latency 76811507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47959.385291 # average overall miss latency 76911507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 47959.385291 # average overall miss latency 77011507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked 77111507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 77211507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked 77311507SCurtis.Dunham@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 77411507SCurtis.Dunham@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs 29.250000 # average number of cycles each access was blocked 77511507SCurtis.Dunham@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 77611507SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::writebacks 394 # number of writebacks 77711507SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::total 394 # number of writebacks 77811507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 215 # number of ReadReq MSHR hits 77911507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits 78011507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_hits::cpu0.inst 215 # number of demand (read+write) MSHR hits 78111507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits 78211507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_hits::cpu0.inst 215 # number of overall MSHR hits 78311507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_hits::total 215 # number of overall MSHR hits 78411507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 696 # number of ReadReq MSHR misses 78511507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 696 # number of ReadReq MSHR misses 78611507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 696 # number of demand (read+write) MSHR misses 78711507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::total 696 # number of demand (read+write) MSHR misses 78811507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 696 # number of overall MSHR misses 78911507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::total 696 # number of overall MSHR misses 79011507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 33693000 # number of ReadReq MSHR miss cycles 79111507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 33693000 # number of ReadReq MSHR miss cycles 79211507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 33693000 # number of demand (read+write) MSHR miss cycles 79311507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 33693000 # number of demand (read+write) MSHR miss cycles 79411507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 33693000 # number of overall MSHR miss cycles 79511507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 33693000 # number of overall MSHR miss cycles 79611507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for ReadReq accesses 79711507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087525 # mshr miss rate for ReadReq accesses 79811507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for demand accesses 79911507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.087525 # mshr miss rate for demand accesses 80011507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for overall accesses 80111507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.087525 # mshr miss rate for overall accesses 80211507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average ReadReq mshr miss latency 80311507SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48409.482759 # average ReadReq mshr miss latency 80411507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average overall mshr miss latency 80511507SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 48409.482759 # average overall mshr miss latency 80611507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average overall mshr miss latency 80711507SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 48409.482759 # average overall mshr miss latency 80811507SCurtis.Dunham@arm.comsystem.cpu1.branchPred.lookups 70381 # Number of BP lookups 80911507SCurtis.Dunham@arm.comsystem.cpu1.branchPred.condPredicted 62763 # Number of conditional branches predicted 81011507SCurtis.Dunham@arm.comsystem.cpu1.branchPred.condIncorrect 2321 # Number of conditional branches incorrect 81111507SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBLookups 62113 # Number of BTB lookups 81211507SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBHits 0 # Number of BTB hits 81311507SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 81411507SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 81511507SCurtis.Dunham@arm.comsystem.cpu1.branchPred.usedRAS 1978 # Number of times the RAS was used to get a target. 81611507SCurtis.Dunham@arm.comsystem.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. 81711507SCurtis.Dunham@arm.comsystem.cpu1.branchPred.indirectLookups 62113 # Number of indirect predictor lookups. 81811507SCurtis.Dunham@arm.comsystem.cpu1.branchPred.indirectHits 52196 # Number of indirect target hits. 81911507SCurtis.Dunham@arm.comsystem.cpu1.branchPred.indirectMisses 9917 # Number of indirect misses. 82011507SCurtis.Dunham@arm.comsystem.cpu1.branchPredindirectMispredicted 1232 # Number of mispredicted indirect branches. 82111507SCurtis.Dunham@arm.comsystem.cpu1.numCycles 193493 # number of cpu cycles simulated 82211507SCurtis.Dunham@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 82311507SCurtis.Dunham@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 82411507SCurtis.Dunham@arm.comsystem.cpu1.fetch.icacheStallCycles 35625 # Number of cycles fetch is stalled on an Icache miss 82511507SCurtis.Dunham@arm.comsystem.cpu1.fetch.Insts 388406 # Number of instructions fetch has processed 82611507SCurtis.Dunham@arm.comsystem.cpu1.fetch.Branches 70381 # Number of branches that fetch encountered 82711507SCurtis.Dunham@arm.comsystem.cpu1.fetch.predictedBranches 54174 # Number of branches that fetch has predicted taken 82811507SCurtis.Dunham@arm.comsystem.cpu1.fetch.Cycles 147522 # Number of cycles fetch has run and was not squashing or blocked 82911507SCurtis.Dunham@arm.comsystem.cpu1.fetch.SquashCycles 4799 # Number of cycles fetch has spent squashing 83011507SCurtis.Dunham@arm.comsystem.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 83111507SCurtis.Dunham@arm.comsystem.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from 83211507SCurtis.Dunham@arm.comsystem.cpu1.fetch.PendingTrapStallCycles 1696 # Number of stall cycles due to pending traps 83311507SCurtis.Dunham@arm.comsystem.cpu1.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR 83411507SCurtis.Dunham@arm.comsystem.cpu1.fetch.CacheLines 23532 # Number of cache lines fetched 83511507SCurtis.Dunham@arm.comsystem.cpu1.fetch.IcacheSquashes 933 # Number of outstanding Icache misses that were squashed 83611507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::samples 187271 # Number of instructions fetched each cycle (Total) 83711507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::mean 2.074032 # Number of instructions fetched each cycle (Total) 83811507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::stdev 2.377312 # Number of instructions fetched each cycle (Total) 83911507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 84011507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::0 61181 32.67% 32.67% # Number of instructions fetched each cycle (Total) 84111507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::1 61333 32.75% 65.42% # Number of instructions fetched each cycle (Total) 84211507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::2 6091 3.25% 68.67% # Number of instructions fetched each cycle (Total) 84311507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::3 3354 1.79% 70.46% # Number of instructions fetched each cycle (Total) 84411507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::4 663 0.35% 70.82% # Number of instructions fetched each cycle (Total) 84511507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::5 43826 23.40% 94.22% # Number of instructions fetched each cycle (Total) 84611507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::6 1093 0.58% 94.80% # Number of instructions fetched each cycle (Total) 84711507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::7 1351 0.72% 95.53% # Number of instructions fetched each cycle (Total) 84811507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::8 8379 4.47% 100.00% # Number of instructions fetched each cycle (Total) 84911507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 85011507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 85111507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 85211507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rateDist::total 187271 # Number of instructions fetched each cycle (Total) 85311507SCurtis.Dunham@arm.comsystem.cpu1.fetch.branchRate 0.363739 # Number of branch fetches per cycle 85411507SCurtis.Dunham@arm.comsystem.cpu1.fetch.rate 2.007339 # Number of inst fetches per cycle 85511507SCurtis.Dunham@arm.comsystem.cpu1.decode.IdleCycles 22629 # Number of cycles decode is idle 85611507SCurtis.Dunham@arm.comsystem.cpu1.decode.BlockedCycles 55115 # Number of cycles decode is blocked 85711507SCurtis.Dunham@arm.comsystem.cpu1.decode.RunCycles 103585 # Number of cycles decode is running 85811507SCurtis.Dunham@arm.comsystem.cpu1.decode.UnblockCycles 3533 # Number of cycles decode is unblocking 85911507SCurtis.Dunham@arm.comsystem.cpu1.decode.SquashCycles 2399 # Number of cycles decode is squashing 86011507SCurtis.Dunham@arm.comsystem.cpu1.decode.DecodedInsts 358317 # Number of instructions handled by decode 86111507SCurtis.Dunham@arm.comsystem.cpu1.rename.SquashCycles 2399 # Number of cycles rename is squashing 86211507SCurtis.Dunham@arm.comsystem.cpu1.rename.IdleCycles 23637 # Number of cycles rename is idle 86311507SCurtis.Dunham@arm.comsystem.cpu1.rename.BlockCycles 25102 # Number of cycles rename is blocking 86411507SCurtis.Dunham@arm.comsystem.cpu1.rename.serializeStallCycles 14378 # count of cycles rename stalled for serializing inst 86511507SCurtis.Dunham@arm.comsystem.cpu1.rename.RunCycles 104390 # Number of cycles rename is running 86611507SCurtis.Dunham@arm.comsystem.cpu1.rename.UnblockCycles 17355 # Number of cycles rename is unblocking 86711507SCurtis.Dunham@arm.comsystem.cpu1.rename.RenamedInsts 351725 # Number of instructions processed by rename 86811507SCurtis.Dunham@arm.comsystem.cpu1.rename.IQFullEvents 14900 # Number of times rename has blocked due to IQ full 86911507SCurtis.Dunham@arm.comsystem.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full 87011507SCurtis.Dunham@arm.comsystem.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers 87111507SCurtis.Dunham@arm.comsystem.cpu1.rename.RenamedOperands 247787 # Number of destination operands rename has renamed 87211507SCurtis.Dunham@arm.comsystem.cpu1.rename.RenameLookups 679105 # Number of register rename lookups that rename has made 87311507SCurtis.Dunham@arm.comsystem.cpu1.rename.int_rename_lookups 526513 # Number of integer rename lookups 87411507SCurtis.Dunham@arm.comsystem.cpu1.rename.fp_rename_lookups 34 # Number of floating rename lookups 87511507SCurtis.Dunham@arm.comsystem.cpu1.rename.CommittedMaps 220167 # Number of HB maps that are committed 87611507SCurtis.Dunham@arm.comsystem.cpu1.rename.UndoneMaps 27620 # Number of HB maps that are undone due to squashing 87711507SCurtis.Dunham@arm.comsystem.cpu1.rename.serializingInsts 1612 # count of serializing insts renamed 87811507SCurtis.Dunham@arm.comsystem.cpu1.rename.tempSerializingInsts 1735 # count of temporary serializing insts renamed 87911507SCurtis.Dunham@arm.comsystem.cpu1.rename.skidInsts 22764 # count of insts added to the skid buffer 88011507SCurtis.Dunham@arm.comsystem.cpu1.memDep0.insertedLoads 99432 # Number of loads inserted to the mem dependence unit. 88111507SCurtis.Dunham@arm.comsystem.cpu1.memDep0.insertedStores 48003 # Number of stores inserted to the mem dependence unit. 88211507SCurtis.Dunham@arm.comsystem.cpu1.memDep0.conflictingLoads 46782 # Number of conflicting loads. 88311507SCurtis.Dunham@arm.comsystem.cpu1.memDep0.conflictingStores 41727 # Number of conflicting stores. 88411507SCurtis.Dunham@arm.comsystem.cpu1.iq.iqInstsAdded 289849 # Number of instructions added to the IQ (excludes non-spec) 88511507SCurtis.Dunham@arm.comsystem.cpu1.iq.iqNonSpecInstsAdded 6510 # Number of non-speculative instructions added to the IQ 88611507SCurtis.Dunham@arm.comsystem.cpu1.iq.iqInstsIssued 288395 # Number of instructions issued 88711507SCurtis.Dunham@arm.comsystem.cpu1.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued 88811507SCurtis.Dunham@arm.comsystem.cpu1.iq.iqSquashedInstsExamined 24134 # Number of squashed instructions iterated over during squash; mainly for profiling 88911507SCurtis.Dunham@arm.comsystem.cpu1.iq.iqSquashedOperandsExamined 20047 # Number of squashed operands that are examined and possibly removed from graph 89011507SCurtis.Dunham@arm.comsystem.cpu1.iq.iqSquashedNonSpecRemoved 1135 # Number of squashed non-spec instructions that were removed 89111507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::samples 187271 # Number of insts issued each cycle 89211507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::mean 1.539988 # Number of insts issued each cycle 89311507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::stdev 1.388620 # Number of insts issued each cycle 89411507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 89511507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::0 65886 35.18% 35.18% # Number of insts issued each cycle 89611507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::1 21449 11.45% 46.64% # Number of insts issued each cycle 89711507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::2 46526 24.84% 71.48% # Number of insts issued each cycle 89811507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::3 46214 24.68% 96.16% # Number of insts issued each cycle 89911507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::4 3599 1.92% 98.08% # Number of insts issued each cycle 90011507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::5 1752 0.94% 99.01% # Number of insts issued each cycle 90111507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::6 1124 0.60% 99.61% # Number of insts issued each cycle 90211507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::7 416 0.22% 99.84% # Number of insts issued each cycle 90311507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::8 305 0.16% 100.00% # Number of insts issued each cycle 90411507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 90511507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 90611507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 90711507SCurtis.Dunham@arm.comsystem.cpu1.iq.issued_per_cycle::total 187271 # Number of insts issued each cycle 90811507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 90911507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::IntAlu 198 39.68% 39.68% # attempts to use FU when none available 91011507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::IntMult 0 0.00% 39.68% # attempts to use FU when none available 91111507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::IntDiv 0 0.00% 39.68% # attempts to use FU when none available 91211507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::FloatAdd 0 0.00% 39.68% # attempts to use FU when none available 91311507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::FloatCmp 0 0.00% 39.68% # attempts to use FU when none available 91411507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::FloatCvt 0 0.00% 39.68% # attempts to use FU when none available 91511507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::FloatMult 0 0.00% 39.68% # attempts to use FU when none available 91611507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::FloatDiv 0 0.00% 39.68% # attempts to use FU when none available 91711507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::FloatSqrt 0 0.00% 39.68% # attempts to use FU when none available 91811507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdAdd 0 0.00% 39.68% # attempts to use FU when none available 91911507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 39.68% # attempts to use FU when none available 92011507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdAlu 0 0.00% 39.68% # attempts to use FU when none available 92111507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdCmp 0 0.00% 39.68% # attempts to use FU when none available 92211507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdCvt 0 0.00% 39.68% # attempts to use FU when none available 92311507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdMisc 0 0.00% 39.68% # attempts to use FU when none available 92411507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdMult 0 0.00% 39.68% # attempts to use FU when none available 92511507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 39.68% # attempts to use FU when none available 92611507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdShift 0 0.00% 39.68% # attempts to use FU when none available 92711507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 39.68% # attempts to use FU when none available 92811507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdSqrt 0 0.00% 39.68% # attempts to use FU when none available 92911507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 39.68% # attempts to use FU when none available 93011507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 39.68% # attempts to use FU when none available 93111507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 39.68% # attempts to use FU when none available 93211507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 39.68% # attempts to use FU when none available 93311507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 39.68% # attempts to use FU when none available 93411507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 39.68% # attempts to use FU when none available 93511507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 39.68% # attempts to use FU when none available 93611507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.68% # attempts to use FU when none available 93711507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 39.68% # attempts to use FU when none available 93811507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::MemRead 73 14.63% 54.31% # attempts to use FU when none available 93911507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::MemWrite 228 45.69% 100.00% # attempts to use FU when none available 94011507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 94111507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 94211507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 94311507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::IntAlu 138505 48.03% 48.03% # Type of FU issued 94411507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.03% # Type of FU issued 94511507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.03% # Type of FU issued 94611507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.03% # Type of FU issued 94711507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.03% # Type of FU issued 94811507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.03% # Type of FU issued 94911507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.03% # Type of FU issued 95011507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.03% # Type of FU issued 95111507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.03% # Type of FU issued 95211507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.03% # Type of FU issued 95311507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.03% # Type of FU issued 95411507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.03% # Type of FU issued 95511507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.03% # Type of FU issued 95611507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.03% # Type of FU issued 95711507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.03% # Type of FU issued 95811507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.03% # Type of FU issued 95911507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.03% # Type of FU issued 96011507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.03% # Type of FU issued 96111507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.03% # Type of FU issued 96211507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.03% # Type of FU issued 96311507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.03% # Type of FU issued 96411507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.03% # Type of FU issued 96511507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.03% # Type of FU issued 96611507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.03% # Type of FU issued 96711507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.03% # Type of FU issued 96811507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.03% # Type of FU issued 96911507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.03% # Type of FU issued 97011507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.03% # Type of FU issued 97111507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.03% # Type of FU issued 97211507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::MemRead 102963 35.70% 83.73% # Type of FU issued 97311507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::MemWrite 46927 16.27% 100.00% # Type of FU issued 97411507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 97511507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 97611507SCurtis.Dunham@arm.comsystem.cpu1.iq.FU_type_0::total 288395 # Type of FU issued 97711507SCurtis.Dunham@arm.comsystem.cpu1.iq.rate 1.490467 # Inst issue rate 97811507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_busy_cnt 499 # FU busy when requested 97911507SCurtis.Dunham@arm.comsystem.cpu1.iq.fu_busy_rate 0.001730 # FU busy rate (busy events/executed inst) 98011507SCurtis.Dunham@arm.comsystem.cpu1.iq.int_inst_queue_reads 764671 # Number of integer instruction queue reads 98111507SCurtis.Dunham@arm.comsystem.cpu1.iq.int_inst_queue_writes 320465 # Number of integer instruction queue writes 98211507SCurtis.Dunham@arm.comsystem.cpu1.iq.int_inst_queue_wakeup_accesses 284383 # Number of integer instruction queue wakeup accesses 98311507SCurtis.Dunham@arm.comsystem.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 98411507SCurtis.Dunham@arm.comsystem.cpu1.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes 98511507SCurtis.Dunham@arm.comsystem.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 98611507SCurtis.Dunham@arm.comsystem.cpu1.iq.int_alu_accesses 288894 # Number of integer alu accesses 98711507SCurtis.Dunham@arm.comsystem.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses 98811507SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.forwLoads 41593 # Number of loads that had data forwarded from stores 98911507SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 99011507SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.squashedLoads 4579 # Number of loads squashed 99111507SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.ignoredResponses 38 # Number of memory responses ignored because the instruction is squashed 99211507SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations 99311507SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.squashedStores 2647 # Number of stores squashed 99411507SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 99511507SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 99611507SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 99711507SCurtis.Dunham@arm.comsystem.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 99811507SCurtis.Dunham@arm.comsystem.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 99911507SCurtis.Dunham@arm.comsystem.cpu1.iew.iewSquashCycles 2399 # Number of cycles IEW is squashing 100011507SCurtis.Dunham@arm.comsystem.cpu1.iew.iewBlockCycles 8044 # Number of cycles IEW is blocking 100111507SCurtis.Dunham@arm.comsystem.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking 100211507SCurtis.Dunham@arm.comsystem.cpu1.iew.iewDispatchedInsts 344307 # Number of instructions dispatched to IQ 100311507SCurtis.Dunham@arm.comsystem.cpu1.iew.iewDispSquashedInsts 270 # Number of squashed instructions skipped by dispatch 100411507SCurtis.Dunham@arm.comsystem.cpu1.iew.iewDispLoadInsts 99432 # Number of dispatched load instructions 100511507SCurtis.Dunham@arm.comsystem.cpu1.iew.iewDispStoreInsts 48003 # Number of dispatched store instructions 100611507SCurtis.Dunham@arm.comsystem.cpu1.iew.iewDispNonSpecInsts 1487 # Number of dispatched non-speculative instructions 100711507SCurtis.Dunham@arm.comsystem.cpu1.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall 100811507SCurtis.Dunham@arm.comsystem.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 100911507SCurtis.Dunham@arm.comsystem.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations 101011507SCurtis.Dunham@arm.comsystem.cpu1.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly 101111507SCurtis.Dunham@arm.comsystem.cpu1.iew.predictedNotTakenIncorrect 2454 # Number of branches that were predicted not taken incorrectly 101211507SCurtis.Dunham@arm.comsystem.cpu1.iew.branchMispredicts 2900 # Number of branch mispredicts detected at execute 101311507SCurtis.Dunham@arm.comsystem.cpu1.iew.iewExecutedInsts 285809 # Number of executed instructions 101411507SCurtis.Dunham@arm.comsystem.cpu1.iew.iewExecLoadInsts 97701 # Number of load instructions executed 101511507SCurtis.Dunham@arm.comsystem.cpu1.iew.iewExecSquashedInsts 2586 # Number of squashed instructions skipped in execute 101611507SCurtis.Dunham@arm.comsystem.cpu1.iew.exec_swp 0 # number of swp insts executed 101711507SCurtis.Dunham@arm.comsystem.cpu1.iew.exec_nop 47948 # number of nop insts executed 101811507SCurtis.Dunham@arm.comsystem.cpu1.iew.exec_refs 144318 # number of memory reference insts executed 101911507SCurtis.Dunham@arm.comsystem.cpu1.iew.exec_branches 58093 # Number of branches executed 102011507SCurtis.Dunham@arm.comsystem.cpu1.iew.exec_stores 46617 # Number of stores executed 102111507SCurtis.Dunham@arm.comsystem.cpu1.iew.exec_rate 1.477103 # Inst execution rate 102211507SCurtis.Dunham@arm.comsystem.cpu1.iew.wb_sent 284919 # cumulative count of insts sent to commit 102311507SCurtis.Dunham@arm.comsystem.cpu1.iew.wb_count 284383 # cumulative count of insts written-back 102411507SCurtis.Dunham@arm.comsystem.cpu1.iew.wb_producers 161989 # num instructions producing a value 102511507SCurtis.Dunham@arm.comsystem.cpu1.iew.wb_consumers 169394 # num instructions consuming a value 102611507SCurtis.Dunham@arm.comsystem.cpu1.iew.wb_rate 1.469733 # insts written-back per cycle 102711507SCurtis.Dunham@arm.comsystem.cpu1.iew.wb_fanout 0.956285 # average fanout of values written-back 102811507SCurtis.Dunham@arm.comsystem.cpu1.commit.commitSquashedInsts 25278 # The number of squashed insts skipped by commit 102911507SCurtis.Dunham@arm.comsystem.cpu1.commit.commitNonSpecStalls 5375 # The number of times commit has been forced to stall to communicate backwards 103011507SCurtis.Dunham@arm.comsystem.cpu1.commit.branchMispredicts 2321 # The number of times a branch was mispredicted 103111507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::samples 182469 # Number of insts commited each cycle 103211507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::mean 1.748204 # Number of insts commited each cycle 103311507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::stdev 2.087021 # Number of insts commited each cycle 103411507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 103511507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::0 70580 38.68% 38.68% # Number of insts commited each cycle 103611507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::1 54368 29.80% 68.48% # Number of insts commited each cycle 103711507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::2 5362 2.94% 71.41% # Number of insts commited each cycle 103811507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::3 6062 3.32% 74.74% # Number of insts commited each cycle 103911507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::4 1316 0.72% 75.46% # Number of insts commited each cycle 104011507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::5 41726 22.87% 98.33% # Number of insts commited each cycle 104111507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::6 809 0.44% 98.77% # Number of insts commited each cycle 104211507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::7 1001 0.55% 99.32% # Number of insts commited each cycle 104311507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::8 1245 0.68% 100.00% # Number of insts commited each cycle 104411507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 104511507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 104611507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 104711507SCurtis.Dunham@arm.comsystem.cpu1.commit.committed_per_cycle::total 182469 # Number of insts commited each cycle 104811507SCurtis.Dunham@arm.comsystem.cpu1.commit.committedInsts 318993 # Number of instructions committed 104911507SCurtis.Dunham@arm.comsystem.cpu1.commit.committedOps 318993 # Number of ops (including micro ops) committed 105011507SCurtis.Dunham@arm.comsystem.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 105111507SCurtis.Dunham@arm.comsystem.cpu1.commit.refs 140209 # Number of memory references committed 105211507SCurtis.Dunham@arm.comsystem.cpu1.commit.loads 94853 # Number of loads committed 105311507SCurtis.Dunham@arm.comsystem.cpu1.commit.membars 4659 # Number of memory barriers committed 105411507SCurtis.Dunham@arm.comsystem.cpu1.commit.branches 55980 # Number of branches committed 105511507SCurtis.Dunham@arm.comsystem.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. 105611507SCurtis.Dunham@arm.comsystem.cpu1.commit.int_insts 218308 # Number of committed integer instructions. 105711507SCurtis.Dunham@arm.comsystem.cpu1.commit.function_calls 322 # Number of function calls committed. 105811507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::No_OpClass 46768 14.66% 14.66% # Class of committed instruction 105911507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::IntAlu 127357 39.92% 54.59% # Class of committed instruction 106011507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::IntMult 0 0.00% 54.59% # Class of committed instruction 106111507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.59% # Class of committed instruction 106211507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.59% # Class of committed instruction 106311507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.59% # Class of committed instruction 106411507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.59% # Class of committed instruction 106511507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.59% # Class of committed instruction 106611507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.59% # Class of committed instruction 106711507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.59% # Class of committed instruction 106811507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.59% # Class of committed instruction 106911507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.59% # Class of committed instruction 107011507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.59% # Class of committed instruction 107111507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.59% # Class of committed instruction 107211507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.59% # Class of committed instruction 107311507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.59% # Class of committed instruction 107411507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.59% # Class of committed instruction 107511507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.59% # Class of committed instruction 107611507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.59% # Class of committed instruction 107711507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.59% # Class of committed instruction 107811507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.59% # Class of committed instruction 107911507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.59% # Class of committed instruction 108011507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.59% # Class of committed instruction 108111507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.59% # Class of committed instruction 108211507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.59% # Class of committed instruction 108311507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.59% # Class of committed instruction 108411507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.59% # Class of committed instruction 108511507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.59% # Class of committed instruction 108611507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.59% # Class of committed instruction 108711507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.59% # Class of committed instruction 108811507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::MemRead 99512 31.20% 85.78% # Class of committed instruction 108911507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::MemWrite 45356 14.22% 100.00% # Class of committed instruction 109011507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 109111507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 109211507SCurtis.Dunham@arm.comsystem.cpu1.commit.op_class_0::total 318993 # Class of committed instruction 109311507SCurtis.Dunham@arm.comsystem.cpu1.commit.bw_lim_events 1245 # number cycles where commit BW limit reached 109411507SCurtis.Dunham@arm.comsystem.cpu1.rob.rob_reads 524909 # The number of ROB reads 109511507SCurtis.Dunham@arm.comsystem.cpu1.rob.rob_writes 693389 # The number of ROB writes 109611507SCurtis.Dunham@arm.comsystem.cpu1.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself 109711507SCurtis.Dunham@arm.comsystem.cpu1.idleCycles 6222 # Total number of cycles that the CPU has spent unscheduled due to idling 109811507SCurtis.Dunham@arm.comsystem.cpu1.quiesceCycles 47433 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 109911507SCurtis.Dunham@arm.comsystem.cpu1.committedInsts 267566 # Number of Instructions Simulated 110011507SCurtis.Dunham@arm.comsystem.cpu1.committedOps 267566 # Number of Ops (including micro ops) Simulated 110111507SCurtis.Dunham@arm.comsystem.cpu1.cpi 0.723160 # CPI: Cycles Per Instruction 110211507SCurtis.Dunham@arm.comsystem.cpu1.cpi_total 0.723160 # CPI: Total CPI of All Threads 110311507SCurtis.Dunham@arm.comsystem.cpu1.ipc 1.382820 # IPC: Instructions Per Cycle 110411507SCurtis.Dunham@arm.comsystem.cpu1.ipc_total 1.382820 # IPC: Total IPC of All Threads 110511507SCurtis.Dunham@arm.comsystem.cpu1.int_regfile_reads 496242 # number of integer regfile reads 110611507SCurtis.Dunham@arm.comsystem.cpu1.int_regfile_writes 230976 # number of integer regfile writes 110711507SCurtis.Dunham@arm.comsystem.cpu1.fp_regfile_writes 64 # number of floating regfile writes 110811507SCurtis.Dunham@arm.comsystem.cpu1.misc_regfile_reads 146210 # number of misc regfile reads 110911507SCurtis.Dunham@arm.comsystem.cpu1.misc_regfile_writes 648 # number of misc regfile writes 111011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.replacements 0 # number of replacements 111111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tagsinuse 26.604916 # Cycle average of tags in use 111211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.total_refs 52484 # Total number of references to valid blocks. 111311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks. 111411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.avg_refs 1693.032258 # Average number of references to valid blocks. 111511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 111611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 26.604916 # Average occupied blocks per requestor 111711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.051963 # Average percentage of cache occupancy 111811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.051963 # Average percentage of cache occupancy 111911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id 112011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 112111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 112211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 112311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id 112411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tag_accesses 405985 # Number of tag accesses 112511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.data_accesses 405985 # Number of data accesses 112611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 55568 # number of ReadReq hits 112711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::total 55568 # number of ReadReq hits 112811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 45140 # number of WriteReq hits 112911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::total 45140 # number of WriteReq hits 113011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits 113111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits 113211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 100708 # number of demand (read+write) hits 113311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::total 100708 # number of demand (read+write) hits 113411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 100708 # number of overall hits 113511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::total 100708 # number of overall hits 113611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 507 # number of ReadReq misses 113711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::total 507 # number of ReadReq misses 113811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 146 # number of WriteReq misses 113911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::total 146 # number of WriteReq misses 114011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses 114111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses 114211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 653 # number of demand (read+write) misses 114311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::total 653 # number of demand (read+write) misses 114411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 653 # number of overall misses 114511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::total 653 # number of overall misses 114611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9264000 # number of ReadReq miss cycles 114711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 9264000 # number of ReadReq miss cycles 114811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3726500 # number of WriteReq miss cycles 114911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 3726500 # number of WriteReq miss cycles 115011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_miss_latency::cpu1.data 796000 # number of SwapReq miss cycles 115111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_miss_latency::total 796000 # number of SwapReq miss cycles 115211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 12990500 # number of demand (read+write) miss cycles 115311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::total 12990500 # number of demand (read+write) miss cycles 115411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 12990500 # number of overall miss cycles 115511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::total 12990500 # number of overall miss cycles 115611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 56075 # number of ReadReq accesses(hits+misses) 115711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 56075 # number of ReadReq accesses(hits+misses) 115811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 45286 # number of WriteReq accesses(hits+misses) 115911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 45286 # number of WriteReq accesses(hits+misses) 116011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) 116111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) 116211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 101361 # number of demand (read+write) accesses 116311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::total 101361 # number of demand (read+write) accesses 116411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 101361 # number of overall (read+write) accesses 116511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::total 101361 # number of overall (read+write) accesses 116611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009041 # miss rate for ReadReq accesses 116711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.009041 # miss rate for ReadReq accesses 116811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003224 # miss rate for WriteReq accesses 116911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.003224 # miss rate for WriteReq accesses 117011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.828571 # miss rate for SwapReq accesses 117111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_miss_rate::total 0.828571 # miss rate for SwapReq accesses 117211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.006442 # miss rate for demand accesses 117311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.006442 # miss rate for demand accesses 117411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.006442 # miss rate for overall accesses 117511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.006442 # miss rate for overall accesses 117611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18272.189349 # average ReadReq miss latency 117711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 18272.189349 # average ReadReq miss latency 117811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25523.972603 # average WriteReq miss latency 117911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 25523.972603 # average WriteReq miss latency 118011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13724.137931 # average SwapReq miss latency 118111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_avg_miss_latency::total 13724.137931 # average SwapReq miss latency 118211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19893.568147 # average overall miss latency 118311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 19893.568147 # average overall miss latency 118411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19893.568147 # average overall miss latency 118511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 19893.568147 # average overall miss latency 118611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 118711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 118811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 118911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 119011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 119111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 119211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 341 # number of ReadReq MSHR hits 119311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 341 # number of ReadReq MSHR hits 119411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 40 # number of WriteReq MSHR hits 119511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits 119611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_mshr_hits::cpu1.data 2 # number of SwapReq MSHR hits 119711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_mshr_hits::total 2 # number of SwapReq MSHR hits 119811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 381 # number of demand (read+write) MSHR hits 119911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 381 # number of demand (read+write) MSHR hits 120011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 381 # number of overall MSHR hits 120111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 381 # number of overall MSHR hits 120211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses 120311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses 120411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses 120511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 120611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses 120711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses 120811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses 120911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses 121011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 272 # number of overall MSHR misses 121111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses 121211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2098000 # number of ReadReq MSHR miss cycles 121311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 2098000 # number of ReadReq MSHR miss cycles 121411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1657500 # number of WriteReq MSHR miss cycles 121511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 1657500 # number of WriteReq MSHR miss cycles 121611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 738000 # number of SwapReq MSHR miss cycles 121711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_mshr_miss_latency::total 738000 # number of SwapReq MSHR miss cycles 121811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3755500 # number of demand (read+write) MSHR miss cycles 121911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 3755500 # number of demand (read+write) MSHR miss cycles 122011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3755500 # number of overall MSHR miss cycles 122111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 3755500 # number of overall MSHR miss cycles 122211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002960 # mshr miss rate for ReadReq accesses 122311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002960 # mshr miss rate for ReadReq accesses 122411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002341 # mshr miss rate for WriteReq accesses 122511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002341 # mshr miss rate for WriteReq accesses 122611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses 122711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses 122811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002683 # mshr miss rate for demand accesses 122911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.002683 # mshr miss rate for demand accesses 123011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002683 # mshr miss rate for overall accesses 123111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.002683 # mshr miss rate for overall accesses 123211507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12638.554217 # average ReadReq mshr miss latency 123311507SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12638.554217 # average ReadReq mshr miss latency 123411507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15636.792453 # average WriteReq mshr miss latency 123511507SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15636.792453 # average WriteReq mshr miss latency 123611507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 13178.571429 # average SwapReq mshr miss latency 123711507SCurtis.Dunham@arm.comsystem.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 13178.571429 # average SwapReq mshr miss latency 123811507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13806.985294 # average overall mshr miss latency 123911507SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 13806.985294 # average overall mshr miss latency 124011507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13806.985294 # average overall mshr miss latency 124111507SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 13806.985294 # average overall mshr miss latency 124211507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.replacements 579 # number of replacements 124311507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tagsinuse 98.515696 # Cycle average of tags in use 124411507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.total_refs 22662 # Total number of references to valid blocks. 124511507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.sampled_refs 713 # Sample count of references to valid blocks. 124611507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 31.784011 # Average number of references to valid blocks. 124711507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 124811507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 98.515696 # Average occupied blocks per requestor 124911507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.192413 # Average percentage of cache occupancy 125011507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.192413 # Average percentage of cache occupancy 125111507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id 125211507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 125311507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id 125411507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 8 # Occupied blocks per task id 125511507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 0.261719 # Percentage of cache occupancy per task id 125611507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 24245 # Number of tag accesses 125711507SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 24245 # Number of data accesses 125811507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 22662 # number of ReadReq hits 125911507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::total 22662 # number of ReadReq hits 126011507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 22662 # number of demand (read+write) hits 126111507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 22662 # number of demand (read+write) hits 126211507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 22662 # number of overall hits 126311507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::total 22662 # number of overall hits 126411507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 870 # number of ReadReq misses 126511507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 870 # number of ReadReq misses 126611507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 870 # number of demand (read+write) misses 126711507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 870 # number of demand (read+write) misses 126811507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 870 # number of overall misses 126911507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 870 # number of overall misses 127011507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 19533000 # number of ReadReq miss cycles 127111507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 19533000 # number of ReadReq miss cycles 127211507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 19533000 # number of demand (read+write) miss cycles 127311507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::total 19533000 # number of demand (read+write) miss cycles 127411507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 19533000 # number of overall miss cycles 127511507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::total 19533000 # number of overall miss cycles 127611507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 23532 # number of ReadReq accesses(hits+misses) 127711507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::total 23532 # number of ReadReq accesses(hits+misses) 127811507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 23532 # number of demand (read+write) accesses 127911507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 23532 # number of demand (read+write) accesses 128011507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 23532 # number of overall (read+write) accesses 128111507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 23532 # number of overall (read+write) accesses 128211507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.036971 # miss rate for ReadReq accesses 128311507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.036971 # miss rate for ReadReq accesses 128411507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.036971 # miss rate for demand accesses 128511507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.036971 # miss rate for demand accesses 128611507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.036971 # miss rate for overall accesses 128711507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.036971 # miss rate for overall accesses 128811507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22451.724138 # average ReadReq miss latency 128911507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 22451.724138 # average ReadReq miss latency 129011507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22451.724138 # average overall miss latency 129111507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 22451.724138 # average overall miss latency 129211507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22451.724138 # average overall miss latency 129311507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 22451.724138 # average overall miss latency 129411507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 141 # number of cycles access was blocked 129511507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 129611507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked::no_mshrs 4 # number of cycles access was blocked 129711507SCurtis.Dunham@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 129811507SCurtis.Dunham@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs 35.250000 # average number of cycles each access was blocked 129911507SCurtis.Dunham@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 130011507SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::writebacks 579 # number of writebacks 130111507SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::total 579 # number of writebacks 130211507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 157 # number of ReadReq MSHR hits 130311507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::total 157 # number of ReadReq MSHR hits 130411507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_hits::cpu1.inst 157 # number of demand (read+write) MSHR hits 130511507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_hits::total 157 # number of demand (read+write) MSHR hits 130611507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_hits::cpu1.inst 157 # number of overall MSHR hits 130711507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_hits::total 157 # number of overall MSHR hits 130811507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 713 # number of ReadReq MSHR misses 130911507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 713 # number of ReadReq MSHR misses 131011507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 713 # number of demand (read+write) MSHR misses 131111507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::total 713 # number of demand (read+write) MSHR misses 131211507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 713 # number of overall MSHR misses 131311507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::total 713 # number of overall MSHR misses 131411507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 15250000 # number of ReadReq MSHR miss cycles 131511507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 15250000 # number of ReadReq MSHR miss cycles 131611507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 15250000 # number of demand (read+write) MSHR miss cycles 131711507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 15250000 # number of demand (read+write) MSHR miss cycles 131811507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 15250000 # number of overall MSHR miss cycles 131911507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 15250000 # number of overall MSHR miss cycles 132011507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for ReadReq accesses 132111507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030299 # mshr miss rate for ReadReq accesses 132211507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for demand accesses 132311507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.030299 # mshr miss rate for demand accesses 132411507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for overall accesses 132511507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.030299 # mshr miss rate for overall accesses 132611507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average ReadReq mshr miss latency 132711507SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 21388.499299 # average ReadReq mshr miss latency 132811507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average overall mshr miss latency 132911507SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 21388.499299 # average overall mshr miss latency 133011507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average overall mshr miss latency 133111507SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 21388.499299 # average overall mshr miss latency 133211507SCurtis.Dunham@arm.comsystem.cpu2.branchPred.lookups 63667 # Number of BP lookups 133311507SCurtis.Dunham@arm.comsystem.cpu2.branchPred.condPredicted 55684 # Number of conditional branches predicted 133411507SCurtis.Dunham@arm.comsystem.cpu2.branchPred.condIncorrect 2455 # Number of conditional branches incorrect 133511507SCurtis.Dunham@arm.comsystem.cpu2.branchPred.BTBLookups 55606 # Number of BTB lookups 133611507SCurtis.Dunham@arm.comsystem.cpu2.branchPred.BTBHits 0 # Number of BTB hits 133711507SCurtis.Dunham@arm.comsystem.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 133811507SCurtis.Dunham@arm.comsystem.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 133911507SCurtis.Dunham@arm.comsystem.cpu2.branchPred.usedRAS 2018 # Number of times the RAS was used to get a target. 134011507SCurtis.Dunham@arm.comsystem.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. 134111507SCurtis.Dunham@arm.comsystem.cpu2.branchPred.indirectLookups 55606 # Number of indirect predictor lookups. 134211507SCurtis.Dunham@arm.comsystem.cpu2.branchPred.indirectHits 44645 # Number of indirect target hits. 134311507SCurtis.Dunham@arm.comsystem.cpu2.branchPred.indirectMisses 10961 # Number of indirect misses. 134411507SCurtis.Dunham@arm.comsystem.cpu2.branchPredindirectMispredicted 1342 # Number of mispredicted indirect branches. 134511507SCurtis.Dunham@arm.comsystem.cpu2.numCycles 193104 # number of cpu cycles simulated 134611507SCurtis.Dunham@arm.comsystem.cpu2.numWorkItemsStarted 0 # number of work items this cpu started 134711507SCurtis.Dunham@arm.comsystem.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed 134811507SCurtis.Dunham@arm.comsystem.cpu2.fetch.icacheStallCycles 40968 # Number of cycles fetch is stalled on an Icache miss 134911507SCurtis.Dunham@arm.comsystem.cpu2.fetch.Insts 342539 # Number of instructions fetch has processed 135011507SCurtis.Dunham@arm.comsystem.cpu2.fetch.Branches 63667 # Number of branches that fetch encountered 135111507SCurtis.Dunham@arm.comsystem.cpu2.fetch.predictedBranches 46663 # Number of branches that fetch has predicted taken 135211507SCurtis.Dunham@arm.comsystem.cpu2.fetch.Cycles 146022 # Number of cycles fetch has run and was not squashing or blocked 135311507SCurtis.Dunham@arm.comsystem.cpu2.fetch.SquashCycles 5067 # Number of cycles fetch has spent squashing 135411507SCurtis.Dunham@arm.comsystem.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 135511507SCurtis.Dunham@arm.comsystem.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from 135611507SCurtis.Dunham@arm.comsystem.cpu2.fetch.PendingTrapStallCycles 1848 # Number of stall cycles due to pending traps 135711507SCurtis.Dunham@arm.comsystem.cpu2.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR 135811507SCurtis.Dunham@arm.comsystem.cpu2.fetch.CacheLines 29416 # Number of cache lines fetched 135911507SCurtis.Dunham@arm.comsystem.cpu2.fetch.IcacheSquashes 951 # Number of outstanding Icache misses that were squashed 136011507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::samples 191398 # Number of instructions fetched each cycle (Total) 136111507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::mean 1.789669 # Number of instructions fetched each cycle (Total) 136211507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::stdev 2.326327 # Number of instructions fetched each cycle (Total) 136311507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 136411507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::0 76889 40.17% 40.17% # Number of instructions fetched each cycle (Total) 136511507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::1 56601 29.57% 69.74% # Number of instructions fetched each cycle (Total) 136611507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::2 8825 4.61% 74.36% # Number of instructions fetched each cycle (Total) 136711507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::3 3447 1.80% 76.16% # Number of instructions fetched each cycle (Total) 136811507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::4 694 0.36% 76.52% # Number of instructions fetched each cycle (Total) 136911507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::5 33672 17.59% 94.11% # Number of instructions fetched each cycle (Total) 137011507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::6 980 0.51% 94.62% # Number of instructions fetched each cycle (Total) 137111507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::7 1389 0.73% 95.35% # Number of instructions fetched each cycle (Total) 137211507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::8 8901 4.65% 100.00% # Number of instructions fetched each cycle (Total) 137311507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 137411507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 137511507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 137611507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rateDist::total 191398 # Number of instructions fetched each cycle (Total) 137711507SCurtis.Dunham@arm.comsystem.cpu2.fetch.branchRate 0.329703 # Number of branch fetches per cycle 137811507SCurtis.Dunham@arm.comsystem.cpu2.fetch.rate 1.773858 # Number of inst fetches per cycle 137911507SCurtis.Dunham@arm.comsystem.cpu2.decode.IdleCycles 22836 # Number of cycles decode is idle 138011507SCurtis.Dunham@arm.comsystem.cpu2.decode.BlockedCycles 76803 # Number of cycles decode is blocked 138111507SCurtis.Dunham@arm.comsystem.cpu2.decode.RunCycles 84446 # Number of cycles decode is running 138211507SCurtis.Dunham@arm.comsystem.cpu2.decode.UnblockCycles 4770 # Number of cycles decode is unblocking 138311507SCurtis.Dunham@arm.comsystem.cpu2.decode.SquashCycles 2533 # Number of cycles decode is squashing 138411507SCurtis.Dunham@arm.comsystem.cpu2.decode.DecodedInsts 310490 # Number of instructions handled by decode 138511507SCurtis.Dunham@arm.comsystem.cpu2.rename.SquashCycles 2533 # Number of cycles rename is squashing 138611507SCurtis.Dunham@arm.comsystem.cpu2.rename.IdleCycles 23870 # Number of cycles rename is idle 138711507SCurtis.Dunham@arm.comsystem.cpu2.rename.BlockCycles 37657 # Number of cycles rename is blocking 138811507SCurtis.Dunham@arm.comsystem.cpu2.rename.serializeStallCycles 14813 # count of cycles rename stalled for serializing inst 138911507SCurtis.Dunham@arm.comsystem.cpu2.rename.RunCycles 85216 # Number of cycles rename is running 139011507SCurtis.Dunham@arm.comsystem.cpu2.rename.UnblockCycles 27299 # Number of cycles rename is unblocking 139111507SCurtis.Dunham@arm.comsystem.cpu2.rename.RenamedInsts 303538 # Number of instructions processed by rename 139211507SCurtis.Dunham@arm.comsystem.cpu2.rename.IQFullEvents 23577 # Number of times rename has blocked due to IQ full 139311507SCurtis.Dunham@arm.comsystem.cpu2.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full 139411507SCurtis.Dunham@arm.comsystem.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers 139511507SCurtis.Dunham@arm.comsystem.cpu2.rename.RenamedOperands 211726 # Number of destination operands rename has renamed 139611507SCurtis.Dunham@arm.comsystem.cpu2.rename.RenameLookups 571973 # Number of register rename lookups that rename has made 139711507SCurtis.Dunham@arm.comsystem.cpu2.rename.int_rename_lookups 446566 # Number of integer rename lookups 139811507SCurtis.Dunham@arm.comsystem.cpu2.rename.fp_rename_lookups 26 # Number of floating rename lookups 139911507SCurtis.Dunham@arm.comsystem.cpu2.rename.CommittedMaps 182781 # Number of HB maps that are committed 140011507SCurtis.Dunham@arm.comsystem.cpu2.rename.UndoneMaps 28945 # Number of HB maps that are undone due to squashing 140111507SCurtis.Dunham@arm.comsystem.cpu2.rename.serializingInsts 1674 # count of serializing insts renamed 140211507SCurtis.Dunham@arm.comsystem.cpu2.rename.tempSerializingInsts 1822 # count of temporary serializing insts renamed 140311507SCurtis.Dunham@arm.comsystem.cpu2.rename.skidInsts 33085 # count of insts added to the skid buffer 140411507SCurtis.Dunham@arm.comsystem.cpu2.memDep0.insertedLoads 82000 # Number of loads inserted to the mem dependence unit. 140511507SCurtis.Dunham@arm.comsystem.cpu2.memDep0.insertedStores 37987 # Number of stores inserted to the mem dependence unit. 140611507SCurtis.Dunham@arm.comsystem.cpu2.memDep0.conflictingLoads 39268 # Number of conflicting loads. 140711507SCurtis.Dunham@arm.comsystem.cpu2.memDep0.conflictingStores 31634 # Number of conflicting stores. 140811507SCurtis.Dunham@arm.comsystem.cpu2.iq.iqInstsAdded 245836 # Number of instructions added to the IQ (excludes non-spec) 140911507SCurtis.Dunham@arm.comsystem.cpu2.iq.iqNonSpecInstsAdded 9182 # Number of non-speculative instructions added to the IQ 141011507SCurtis.Dunham@arm.comsystem.cpu2.iq.iqInstsIssued 247097 # Number of instructions issued 141111507SCurtis.Dunham@arm.comsystem.cpu2.iq.iqSquashedInstsIssued 85 # Number of squashed instructions issued 141211507SCurtis.Dunham@arm.comsystem.cpu2.iq.iqSquashedInstsExamined 25038 # Number of squashed instructions iterated over during squash; mainly for profiling 141311507SCurtis.Dunham@arm.comsystem.cpu2.iq.iqSquashedOperandsExamined 19372 # Number of squashed operands that are examined and possibly removed from graph 141411507SCurtis.Dunham@arm.comsystem.cpu2.iq.iqSquashedNonSpecRemoved 1244 # Number of squashed non-spec instructions that were removed 141511507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::samples 191398 # Number of insts issued each cycle 141611507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::mean 1.291011 # Number of insts issued each cycle 141711507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::stdev 1.381781 # Number of insts issued each cycle 141811507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 141911507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::0 81765 42.72% 42.72% # Number of insts issued each cycle 142011507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::1 29268 15.29% 58.01% # Number of insts issued each cycle 142111507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::2 36754 19.20% 77.21% # Number of insts issued each cycle 142211507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::3 36522 19.08% 96.30% # Number of insts issued each cycle 142311507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::4 3555 1.86% 98.15% # Number of insts issued each cycle 142411507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::5 1723 0.90% 99.05% # Number of insts issued each cycle 142511507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::6 1061 0.55% 99.61% # Number of insts issued each cycle 142611507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::7 446 0.23% 99.84% # Number of insts issued each cycle 142711507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::8 304 0.16% 100.00% # Number of insts issued each cycle 142811507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 142911507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 143011507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 143111507SCurtis.Dunham@arm.comsystem.cpu2.iq.issued_per_cycle::total 191398 # Number of insts issued each cycle 143211507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 143311507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::IntAlu 203 40.76% 40.76% # attempts to use FU when none available 143411507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::IntMult 0 0.00% 40.76% # attempts to use FU when none available 143511507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::IntDiv 0 0.00% 40.76% # attempts to use FU when none available 143611507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::FloatAdd 0 0.00% 40.76% # attempts to use FU when none available 143711507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::FloatCmp 0 0.00% 40.76% # attempts to use FU when none available 143811507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::FloatCvt 0 0.00% 40.76% # attempts to use FU when none available 143911507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::FloatMult 0 0.00% 40.76% # attempts to use FU when none available 144011507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::FloatDiv 0 0.00% 40.76% # attempts to use FU when none available 144111507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::FloatSqrt 0 0.00% 40.76% # attempts to use FU when none available 144211507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdAdd 0 0.00% 40.76% # attempts to use FU when none available 144311507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 40.76% # attempts to use FU when none available 144411507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdAlu 0 0.00% 40.76% # attempts to use FU when none available 144511507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdCmp 0 0.00% 40.76% # attempts to use FU when none available 144611507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdCvt 0 0.00% 40.76% # attempts to use FU when none available 144711507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdMisc 0 0.00% 40.76% # attempts to use FU when none available 144811507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdMult 0 0.00% 40.76% # attempts to use FU when none available 144911507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 40.76% # attempts to use FU when none available 145011507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdShift 0 0.00% 40.76% # attempts to use FU when none available 145111507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 40.76% # attempts to use FU when none available 145211507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdSqrt 0 0.00% 40.76% # attempts to use FU when none available 145311507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 40.76% # attempts to use FU when none available 145411507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 40.76% # attempts to use FU when none available 145511507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 40.76% # attempts to use FU when none available 145611507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 40.76% # attempts to use FU when none available 145711507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 40.76% # attempts to use FU when none available 145811507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 40.76% # attempts to use FU when none available 145911507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 40.76% # attempts to use FU when none available 146011507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.76% # attempts to use FU when none available 146111507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 40.76% # attempts to use FU when none available 146211507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::MemRead 64 12.85% 53.61% # attempts to use FU when none available 146311507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::MemWrite 231 46.39% 100.00% # attempts to use FU when none available 146411507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 146511507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 146611507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 146711507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::IntAlu 121951 49.35% 49.35% # Type of FU issued 146811507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.35% # Type of FU issued 146911507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.35% # Type of FU issued 147011507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.35% # Type of FU issued 147111507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.35% # Type of FU issued 147211507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.35% # Type of FU issued 147311507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.35% # Type of FU issued 147411507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.35% # Type of FU issued 147511507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.35% # Type of FU issued 147611507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.35% # Type of FU issued 147711507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.35% # Type of FU issued 147811507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.35% # Type of FU issued 147911507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.35% # Type of FU issued 148011507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.35% # Type of FU issued 148111507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.35% # Type of FU issued 148211507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.35% # Type of FU issued 148311507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.35% # Type of FU issued 148411507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.35% # Type of FU issued 148511507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.35% # Type of FU issued 148611507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.35% # Type of FU issued 148711507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.35% # Type of FU issued 148811507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.35% # Type of FU issued 148911507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.35% # Type of FU issued 149011507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.35% # Type of FU issued 149111507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.35% # Type of FU issued 149211507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.35% # Type of FU issued 149311507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.35% # Type of FU issued 149411507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.35% # Type of FU issued 149511507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.35% # Type of FU issued 149611507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::MemRead 88101 35.65% 85.01% # Type of FU issued 149711507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::MemWrite 37045 14.99% 100.00% # Type of FU issued 149811507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 149911507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 150011507SCurtis.Dunham@arm.comsystem.cpu2.iq.FU_type_0::total 247097 # Type of FU issued 150111507SCurtis.Dunham@arm.comsystem.cpu2.iq.rate 1.279606 # Inst issue rate 150211507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_busy_cnt 498 # FU busy when requested 150311507SCurtis.Dunham@arm.comsystem.cpu2.iq.fu_busy_rate 0.002015 # FU busy rate (busy events/executed inst) 150411507SCurtis.Dunham@arm.comsystem.cpu2.iq.int_inst_queue_reads 686175 # Number of integer instruction queue reads 150511507SCurtis.Dunham@arm.comsystem.cpu2.iq.int_inst_queue_writes 280041 # Number of integer instruction queue writes 150611507SCurtis.Dunham@arm.comsystem.cpu2.iq.int_inst_queue_wakeup_accesses 243170 # Number of integer instruction queue wakeup accesses 150711507SCurtis.Dunham@arm.comsystem.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 150811507SCurtis.Dunham@arm.comsystem.cpu2.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes 150911507SCurtis.Dunham@arm.comsystem.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 151011507SCurtis.Dunham@arm.comsystem.cpu2.iq.int_alu_accesses 247595 # Number of integer alu accesses 151111507SCurtis.Dunham@arm.comsystem.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses 151211507SCurtis.Dunham@arm.comsystem.cpu2.iew.lsq.thread0.forwLoads 31591 # Number of loads that had data forwarded from stores 151311507SCurtis.Dunham@arm.comsystem.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 151411507SCurtis.Dunham@arm.comsystem.cpu2.iew.lsq.thread0.squashedLoads 4554 # Number of loads squashed 151511507SCurtis.Dunham@arm.comsystem.cpu2.iew.lsq.thread0.ignoredResponses 33 # Number of memory responses ignored because the instruction is squashed 151611507SCurtis.Dunham@arm.comsystem.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations 151711507SCurtis.Dunham@arm.comsystem.cpu2.iew.lsq.thread0.squashedStores 2621 # Number of stores squashed 151811507SCurtis.Dunham@arm.comsystem.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 151911507SCurtis.Dunham@arm.comsystem.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 152011507SCurtis.Dunham@arm.comsystem.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 152111507SCurtis.Dunham@arm.comsystem.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 152211507SCurtis.Dunham@arm.comsystem.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle 152311507SCurtis.Dunham@arm.comsystem.cpu2.iew.iewSquashCycles 2533 # Number of cycles IEW is squashing 152411507SCurtis.Dunham@arm.comsystem.cpu2.iew.iewBlockCycles 10681 # Number of cycles IEW is blocking 152511507SCurtis.Dunham@arm.comsystem.cpu2.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking 152611507SCurtis.Dunham@arm.comsystem.cpu2.iew.iewDispatchedInsts 295617 # Number of instructions dispatched to IQ 152711507SCurtis.Dunham@arm.comsystem.cpu2.iew.iewDispSquashedInsts 336 # Number of squashed instructions skipped by dispatch 152811507SCurtis.Dunham@arm.comsystem.cpu2.iew.iewDispLoadInsts 82000 # Number of dispatched load instructions 152911507SCurtis.Dunham@arm.comsystem.cpu2.iew.iewDispStoreInsts 37987 # Number of dispatched store instructions 153011507SCurtis.Dunham@arm.comsystem.cpu2.iew.iewDispNonSpecInsts 1539 # Number of dispatched non-speculative instructions 153111507SCurtis.Dunham@arm.comsystem.cpu2.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall 153211507SCurtis.Dunham@arm.comsystem.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 153311507SCurtis.Dunham@arm.comsystem.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations 153411507SCurtis.Dunham@arm.comsystem.cpu2.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly 153511507SCurtis.Dunham@arm.comsystem.cpu2.iew.predictedNotTakenIncorrect 2642 # Number of branches that were predicted not taken incorrectly 153611507SCurtis.Dunham@arm.comsystem.cpu2.iew.branchMispredicts 3088 # Number of branch mispredicts detected at execute 153711507SCurtis.Dunham@arm.comsystem.cpu2.iew.iewExecutedInsts 244561 # Number of executed instructions 153811507SCurtis.Dunham@arm.comsystem.cpu2.iew.iewExecLoadInsts 80330 # Number of load instructions executed 153911507SCurtis.Dunham@arm.comsystem.cpu2.iew.iewExecSquashedInsts 2536 # Number of squashed instructions skipped in execute 154011507SCurtis.Dunham@arm.comsystem.cpu2.iew.exec_swp 0 # number of swp insts executed 154111507SCurtis.Dunham@arm.comsystem.cpu2.iew.exec_nop 40599 # number of nop insts executed 154211507SCurtis.Dunham@arm.comsystem.cpu2.iew.exec_refs 117071 # number of memory reference insts executed 154311507SCurtis.Dunham@arm.comsystem.cpu2.iew.exec_branches 50931 # Number of branches executed 154411507SCurtis.Dunham@arm.comsystem.cpu2.iew.exec_stores 36741 # Number of stores executed 154511507SCurtis.Dunham@arm.comsystem.cpu2.iew.exec_rate 1.266473 # Inst execution rate 154611507SCurtis.Dunham@arm.comsystem.cpu2.iew.wb_sent 243660 # cumulative count of insts sent to commit 154711507SCurtis.Dunham@arm.comsystem.cpu2.iew.wb_count 243170 # cumulative count of insts written-back 154811507SCurtis.Dunham@arm.comsystem.cpu2.iew.wb_producers 134852 # num instructions producing a value 154911507SCurtis.Dunham@arm.comsystem.cpu2.iew.wb_consumers 142392 # num instructions consuming a value 155011507SCurtis.Dunham@arm.comsystem.cpu2.iew.wb_rate 1.259270 # insts written-back per cycle 155111507SCurtis.Dunham@arm.comsystem.cpu2.iew.wb_fanout 0.947048 # average fanout of values written-back 155211507SCurtis.Dunham@arm.comsystem.cpu2.commit.commitSquashedInsts 26266 # The number of squashed insts skipped by commit 155311507SCurtis.Dunham@arm.comsystem.cpu2.commit.commitNonSpecStalls 7938 # The number of times commit has been forced to stall to communicate backwards 155411507SCurtis.Dunham@arm.comsystem.cpu2.commit.branchMispredicts 2455 # The number of times a branch was mispredicted 155511507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::samples 186363 # Number of insts commited each cycle 155611507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::mean 1.445163 # Number of insts commited each cycle 155711507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::stdev 1.976076 # Number of insts commited each cycle 155811507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 155911507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::0 89147 47.84% 47.84% # Number of insts commited each cycle 156011507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::1 47087 25.27% 73.10% # Number of insts commited each cycle 156111507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::2 5442 2.92% 76.02% # Number of insts commited each cycle 156211507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::3 8636 4.63% 80.66% # Number of insts commited each cycle 156311507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::4 1280 0.69% 81.34% # Number of insts commited each cycle 156411507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::5 31787 17.06% 98.40% # Number of insts commited each cycle 156511507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::6 722 0.39% 98.79% # Number of insts commited each cycle 156611507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::7 1037 0.56% 99.34% # Number of insts commited each cycle 156711507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::8 1225 0.66% 100.00% # Number of insts commited each cycle 156811507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 156911507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 157011507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 157111507SCurtis.Dunham@arm.comsystem.cpu2.commit.committed_per_cycle::total 186363 # Number of insts commited each cycle 157211507SCurtis.Dunham@arm.comsystem.cpu2.commit.committedInsts 269325 # Number of instructions committed 157311507SCurtis.Dunham@arm.comsystem.cpu2.commit.committedOps 269325 # Number of ops (including micro ops) committed 157411507SCurtis.Dunham@arm.comsystem.cpu2.commit.swp_count 0 # Number of s/w prefetches committed 157511507SCurtis.Dunham@arm.comsystem.cpu2.commit.refs 112812 # Number of memory references committed 157611507SCurtis.Dunham@arm.comsystem.cpu2.commit.loads 77446 # Number of loads committed 157711507SCurtis.Dunham@arm.comsystem.cpu2.commit.membars 7225 # Number of memory barriers committed 157811507SCurtis.Dunham@arm.comsystem.cpu2.commit.branches 48554 # Number of branches committed 157911507SCurtis.Dunham@arm.comsystem.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. 158011507SCurtis.Dunham@arm.comsystem.cpu2.commit.int_insts 183489 # Number of committed integer instructions. 158111507SCurtis.Dunham@arm.comsystem.cpu2.commit.function_calls 322 # Number of function calls committed. 158211507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::No_OpClass 39345 14.61% 14.61% # Class of committed instruction 158311507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::IntAlu 109943 40.82% 55.43% # Class of committed instruction 158411507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::IntMult 0 0.00% 55.43% # Class of committed instruction 158511507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.43% # Class of committed instruction 158611507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.43% # Class of committed instruction 158711507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.43% # Class of committed instruction 158811507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.43% # Class of committed instruction 158911507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.43% # Class of committed instruction 159011507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.43% # Class of committed instruction 159111507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.43% # Class of committed instruction 159211507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.43% # Class of committed instruction 159311507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.43% # Class of committed instruction 159411507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.43% # Class of committed instruction 159511507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.43% # Class of committed instruction 159611507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.43% # Class of committed instruction 159711507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.43% # Class of committed instruction 159811507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.43% # Class of committed instruction 159911507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.43% # Class of committed instruction 160011507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.43% # Class of committed instruction 160111507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.43% # Class of committed instruction 160211507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.43% # Class of committed instruction 160311507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.43% # Class of committed instruction 160411507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.43% # Class of committed instruction 160511507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.43% # Class of committed instruction 160611507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.43% # Class of committed instruction 160711507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.43% # Class of committed instruction 160811507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.43% # Class of committed instruction 160911507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.43% # Class of committed instruction 161011507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.43% # Class of committed instruction 161111507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.43% # Class of committed instruction 161211507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::MemRead 84671 31.44% 86.87% # Class of committed instruction 161311507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::MemWrite 35366 13.13% 100.00% # Class of committed instruction 161411507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 161511507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 161611507SCurtis.Dunham@arm.comsystem.cpu2.commit.op_class_0::total 269325 # Class of committed instruction 161711507SCurtis.Dunham@arm.comsystem.cpu2.commit.bw_lim_events 1225 # number cycles where commit BW limit reached 161811507SCurtis.Dunham@arm.comsystem.cpu2.rob.rob_reads 480143 # The number of ROB reads 161911507SCurtis.Dunham@arm.comsystem.cpu2.rob.rob_writes 596277 # The number of ROB writes 162011507SCurtis.Dunham@arm.comsystem.cpu2.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself 162111507SCurtis.Dunham@arm.comsystem.cpu2.idleCycles 1706 # Total number of cycles that the CPU has spent unscheduled due to idling 162211507SCurtis.Dunham@arm.comsystem.cpu2.quiesceCycles 47823 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 162311507SCurtis.Dunham@arm.comsystem.cpu2.committedInsts 222755 # Number of Instructions Simulated 162411507SCurtis.Dunham@arm.comsystem.cpu2.committedOps 222755 # Number of Ops (including micro ops) Simulated 162511507SCurtis.Dunham@arm.comsystem.cpu2.cpi 0.866890 # CPI: Cycles Per Instruction 162611507SCurtis.Dunham@arm.comsystem.cpu2.cpi_total 0.866890 # CPI: Total CPI of All Threads 162711507SCurtis.Dunham@arm.comsystem.cpu2.ipc 1.153549 # IPC: Instructions Per Cycle 162811507SCurtis.Dunham@arm.comsystem.cpu2.ipc_total 1.153549 # IPC: Total IPC of All Threads 162911507SCurtis.Dunham@arm.comsystem.cpu2.int_regfile_reads 415553 # number of integer regfile reads 163011507SCurtis.Dunham@arm.comsystem.cpu2.int_regfile_writes 194388 # number of integer regfile writes 163111507SCurtis.Dunham@arm.comsystem.cpu2.fp_regfile_writes 64 # number of floating regfile writes 163211507SCurtis.Dunham@arm.comsystem.cpu2.misc_regfile_reads 119022 # number of misc regfile reads 163311507SCurtis.Dunham@arm.comsystem.cpu2.misc_regfile_writes 648 # number of misc regfile writes 163411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.replacements 0 # number of replacements 163511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.tagsinuse 25.641689 # Cycle average of tags in use 163611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.total_refs 42500 # Total number of references to valid blocks. 163711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. 163811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.avg_refs 1416.666667 # Average number of references to valid blocks. 163911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 164011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_blocks::cpu2.data 25.641689 # Average occupied blocks per requestor 164111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_percent::cpu2.data 0.050081 # Average percentage of cache occupancy 164211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_percent::total 0.050081 # Average percentage of cache occupancy 164311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id 164411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 164511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id 164611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 164711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id 164811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.tag_accesses 336580 # Number of tag accesses 164911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.tags.data_accesses 336580 # Number of data accesses 165011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_hits::cpu2.data 48215 # number of ReadReq hits 165111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_hits::total 48215 # number of ReadReq hits 165211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_hits::cpu2.data 35154 # number of WriteReq hits 165311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_hits::total 35154 # number of WriteReq hits 165411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits 165511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits 165611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_hits::cpu2.data 83369 # number of demand (read+write) hits 165711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_hits::total 83369 # number of demand (read+write) hits 165811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_hits::cpu2.data 83369 # number of overall hits 165911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_hits::total 83369 # number of overall hits 166011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_misses::cpu2.data 500 # number of ReadReq misses 166111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_misses::total 500 # number of ReadReq misses 166211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_misses::cpu2.data 145 # number of WriteReq misses 166311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_misses::total 145 # number of WriteReq misses 166411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses 166511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses 166611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_misses::cpu2.data 645 # number of demand (read+write) misses 166711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_misses::total 645 # number of demand (read+write) misses 166811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_misses::cpu2.data 645 # number of overall misses 166911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_misses::total 645 # number of overall misses 167011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_miss_latency::cpu2.data 8163500 # number of ReadReq miss cycles 167111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_miss_latency::total 8163500 # number of ReadReq miss cycles 167211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3144500 # number of WriteReq miss cycles 167311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_miss_latency::total 3144500 # number of WriteReq miss cycles 167411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_miss_latency::cpu2.data 806000 # number of SwapReq miss cycles 167511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_miss_latency::total 806000 # number of SwapReq miss cycles 167611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_miss_latency::cpu2.data 11308000 # number of demand (read+write) miss cycles 167711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_miss_latency::total 11308000 # number of demand (read+write) miss cycles 167811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_miss_latency::cpu2.data 11308000 # number of overall miss cycles 167911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_miss_latency::total 11308000 # number of overall miss cycles 168011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_accesses::cpu2.data 48715 # number of ReadReq accesses(hits+misses) 168111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_accesses::total 48715 # number of ReadReq accesses(hits+misses) 168211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_accesses::cpu2.data 35299 # number of WriteReq accesses(hits+misses) 168311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_accesses::total 35299 # number of WriteReq accesses(hits+misses) 168411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_accesses::cpu2.data 67 # number of SwapReq accesses(hits+misses) 168511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) 168611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_accesses::cpu2.data 84014 # number of demand (read+write) accesses 168711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_accesses::total 84014 # number of demand (read+write) accesses 168811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_accesses::cpu2.data 84014 # number of overall (read+write) accesses 168911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_accesses::total 84014 # number of overall (read+write) accesses 169011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010264 # miss rate for ReadReq accesses 169111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_miss_rate::total 0.010264 # miss rate for ReadReq accesses 169211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004108 # miss rate for WriteReq accesses 169311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_miss_rate::total 0.004108 # miss rate for WriteReq accesses 169411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.805970 # miss rate for SwapReq accesses 169511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_miss_rate::total 0.805970 # miss rate for SwapReq accesses 169611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_miss_rate::cpu2.data 0.007677 # miss rate for demand accesses 169711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_miss_rate::total 0.007677 # miss rate for demand accesses 169811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_miss_rate::cpu2.data 0.007677 # miss rate for overall accesses 169911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_miss_rate::total 0.007677 # miss rate for overall accesses 170011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16327 # average ReadReq miss latency 170111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_avg_miss_latency::total 16327 # average ReadReq miss latency 170211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21686.206897 # average WriteReq miss latency 170311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_avg_miss_latency::total 21686.206897 # average WriteReq miss latency 170411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 14925.925926 # average SwapReq miss latency 170511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_avg_miss_latency::total 14925.925926 # average SwapReq miss latency 170611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17531.782946 # average overall miss latency 170711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_avg_miss_latency::total 17531.782946 # average overall miss latency 170811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17531.782946 # average overall miss latency 170911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_avg_miss_latency::total 17531.782946 # average overall miss latency 171011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 171111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 171211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 171311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked 171411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 171511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 171611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 338 # number of ReadReq MSHR hits 171711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_mshr_hits::total 338 # number of ReadReq MSHR hits 171811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 39 # number of WriteReq MSHR hits 171911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_hits::total 39 # number of WriteReq MSHR hits 172011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_mshr_hits::cpu2.data 2 # number of SwapReq MSHR hits 172111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_mshr_hits::total 2 # number of SwapReq MSHR hits 172211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_mshr_hits::cpu2.data 377 # number of demand (read+write) MSHR hits 172311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_mshr_hits::total 377 # number of demand (read+write) MSHR hits 172411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_mshr_hits::cpu2.data 377 # number of overall MSHR hits 172511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_mshr_hits::total 377 # number of overall MSHR hits 172611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses 172711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses 172811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses 172911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses 173011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses 173111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses 173211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses 173311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses 173411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses 173511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses 173611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1730500 # number of ReadReq MSHR miss cycles 173711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_mshr_miss_latency::total 1730500 # number of ReadReq MSHR miss cycles 173811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1679500 # number of WriteReq MSHR miss cycles 173911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_miss_latency::total 1679500 # number of WriteReq MSHR miss cycles 174011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 752000 # number of SwapReq MSHR miss cycles 174111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_mshr_miss_latency::total 752000 # number of SwapReq MSHR miss cycles 174211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3410000 # number of demand (read+write) MSHR miss cycles 174311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_mshr_miss_latency::total 3410000 # number of demand (read+write) MSHR miss cycles 174411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3410000 # number of overall MSHR miss cycles 174511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_mshr_miss_latency::total 3410000 # number of overall MSHR miss cycles 174611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003325 # mshr miss rate for ReadReq accesses 174711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003325 # mshr miss rate for ReadReq accesses 174811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003003 # mshr miss rate for WriteReq accesses 174911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003003 # mshr miss rate for WriteReq accesses 175011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.776119 # mshr miss rate for SwapReq accesses 175111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.776119 # mshr miss rate for SwapReq accesses 175211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003190 # mshr miss rate for demand accesses 175311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_mshr_miss_rate::total 0.003190 # mshr miss rate for demand accesses 175411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003190 # mshr miss rate for overall accesses 175511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_mshr_miss_rate::total 0.003190 # mshr miss rate for overall accesses 175611507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10682.098765 # average ReadReq mshr miss latency 175711507SCurtis.Dunham@arm.comsystem.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10682.098765 # average ReadReq mshr miss latency 175811507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15844.339623 # average WriteReq mshr miss latency 175911507SCurtis.Dunham@arm.comsystem.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15844.339623 # average WriteReq mshr miss latency 176011507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 14461.538462 # average SwapReq mshr miss latency 176111507SCurtis.Dunham@arm.comsystem.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 14461.538462 # average SwapReq mshr miss latency 176211507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12723.880597 # average overall mshr miss latency 176311507SCurtis.Dunham@arm.comsystem.cpu2.dcache.demand_avg_mshr_miss_latency::total 12723.880597 # average overall mshr miss latency 176411507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12723.880597 # average overall mshr miss latency 176511507SCurtis.Dunham@arm.comsystem.cpu2.dcache.overall_avg_mshr_miss_latency::total 12723.880597 # average overall mshr miss latency 176611507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.replacements 598 # number of replacements 176711507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.tagsinuse 95.853337 # Cycle average of tags in use 176811507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.total_refs 28564 # Total number of references to valid blocks. 176911507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.sampled_refs 733 # Sample count of references to valid blocks. 177011507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.avg_refs 38.968622 # Average number of references to valid blocks. 177111507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 177211507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_blocks::cpu2.inst 95.853337 # Average occupied blocks per requestor 177311507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_percent::cpu2.inst 0.187214 # Average percentage of cache occupancy 177411507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_percent::total 0.187214 # Average percentage of cache occupancy 177511507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 177611507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 177711507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id 177811507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id 177911507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id 178011507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.tag_accesses 30149 # Number of tag accesses 178111507SCurtis.Dunham@arm.comsystem.cpu2.icache.tags.data_accesses 30149 # Number of data accesses 178211507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_hits::cpu2.inst 28564 # number of ReadReq hits 178311507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_hits::total 28564 # number of ReadReq hits 178411507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_hits::cpu2.inst 28564 # number of demand (read+write) hits 178511507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_hits::total 28564 # number of demand (read+write) hits 178611507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_hits::cpu2.inst 28564 # number of overall hits 178711507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_hits::total 28564 # number of overall hits 178811507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_misses::cpu2.inst 852 # number of ReadReq misses 178911507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_misses::total 852 # number of ReadReq misses 179011507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_misses::cpu2.inst 852 # number of demand (read+write) misses 179111507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_misses::total 852 # number of demand (read+write) misses 179211507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_misses::cpu2.inst 852 # number of overall misses 179311507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_misses::total 852 # number of overall misses 179411507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12789500 # number of ReadReq miss cycles 179511507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_miss_latency::total 12789500 # number of ReadReq miss cycles 179611507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_miss_latency::cpu2.inst 12789500 # number of demand (read+write) miss cycles 179711507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_miss_latency::total 12789500 # number of demand (read+write) miss cycles 179811507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_miss_latency::cpu2.inst 12789500 # number of overall miss cycles 179911507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_miss_latency::total 12789500 # number of overall miss cycles 180011507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_accesses::cpu2.inst 29416 # number of ReadReq accesses(hits+misses) 180111507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_accesses::total 29416 # number of ReadReq accesses(hits+misses) 180211507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_accesses::cpu2.inst 29416 # number of demand (read+write) accesses 180311507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_accesses::total 29416 # number of demand (read+write) accesses 180411507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_accesses::cpu2.inst 29416 # number of overall (read+write) accesses 180511507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_accesses::total 29416 # number of overall (read+write) accesses 180611507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028964 # miss rate for ReadReq accesses 180711507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_miss_rate::total 0.028964 # miss rate for ReadReq accesses 180811507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_miss_rate::cpu2.inst 0.028964 # miss rate for demand accesses 180911507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_miss_rate::total 0.028964 # miss rate for demand accesses 181011507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_miss_rate::cpu2.inst 0.028964 # miss rate for overall accesses 181111507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_miss_rate::total 0.028964 # miss rate for overall accesses 181211507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15011.150235 # average ReadReq miss latency 181311507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_avg_miss_latency::total 15011.150235 # average ReadReq miss latency 181411507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15011.150235 # average overall miss latency 181511507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_avg_miss_latency::total 15011.150235 # average overall miss latency 181611507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15011.150235 # average overall miss latency 181711507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_avg_miss_latency::total 15011.150235 # average overall miss latency 181811507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked_cycles::no_mshrs 111 # number of cycles access was blocked 181911507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 182011507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked::no_mshrs 5 # number of cycles access was blocked 182111507SCurtis.Dunham@arm.comsystem.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked 182211507SCurtis.Dunham@arm.comsystem.cpu2.icache.avg_blocked_cycles::no_mshrs 22.200000 # average number of cycles each access was blocked 182311507SCurtis.Dunham@arm.comsystem.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 182411507SCurtis.Dunham@arm.comsystem.cpu2.icache.writebacks::writebacks 598 # number of writebacks 182511507SCurtis.Dunham@arm.comsystem.cpu2.icache.writebacks::total 598 # number of writebacks 182611507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 119 # number of ReadReq MSHR hits 182711507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits 182811507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_hits::cpu2.inst 119 # number of demand (read+write) MSHR hits 182911507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_hits::total 119 # number of demand (read+write) MSHR hits 183011507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_hits::cpu2.inst 119 # number of overall MSHR hits 183111507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_hits::total 119 # number of overall MSHR hits 183211507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 733 # number of ReadReq MSHR misses 183311507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses 183411507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_misses::cpu2.inst 733 # number of demand (read+write) MSHR misses 183511507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses 183611507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_misses::cpu2.inst 733 # number of overall MSHR misses 183711507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_misses::total 733 # number of overall MSHR misses 183811507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10899500 # number of ReadReq MSHR miss cycles 183911507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_miss_latency::total 10899500 # number of ReadReq MSHR miss cycles 184011507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10899500 # number of demand (read+write) MSHR miss cycles 184111507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_miss_latency::total 10899500 # number of demand (read+write) MSHR miss cycles 184211507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10899500 # number of overall MSHR miss cycles 184311507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_miss_latency::total 10899500 # number of overall MSHR miss cycles 184411507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024918 # mshr miss rate for ReadReq accesses 184511507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024918 # mshr miss rate for ReadReq accesses 184611507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024918 # mshr miss rate for demand accesses 184711507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses 184811507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024918 # mshr miss rate for overall accesses 184911507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_mshr_miss_rate::total 0.024918 # mshr miss rate for overall accesses 185011507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average ReadReq mshr miss latency 185111507SCurtis.Dunham@arm.comsystem.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 14869.713506 # average ReadReq mshr miss latency 185211507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average overall mshr miss latency 185311507SCurtis.Dunham@arm.comsystem.cpu2.icache.demand_avg_mshr_miss_latency::total 14869.713506 # average overall mshr miss latency 185411507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average overall mshr miss latency 185511507SCurtis.Dunham@arm.comsystem.cpu2.icache.overall_avg_mshr_miss_latency::total 14869.713506 # average overall mshr miss latency 185611507SCurtis.Dunham@arm.comsystem.cpu3.branchPred.lookups 61800 # Number of BP lookups 185711507SCurtis.Dunham@arm.comsystem.cpu3.branchPred.condPredicted 53939 # Number of conditional branches predicted 185811507SCurtis.Dunham@arm.comsystem.cpu3.branchPred.condIncorrect 2339 # Number of conditional branches incorrect 185911507SCurtis.Dunham@arm.comsystem.cpu3.branchPred.BTBLookups 53501 # Number of BTB lookups 186011507SCurtis.Dunham@arm.comsystem.cpu3.branchPred.BTBHits 0 # Number of BTB hits 186111507SCurtis.Dunham@arm.comsystem.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 186211507SCurtis.Dunham@arm.comsystem.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 186311507SCurtis.Dunham@arm.comsystem.cpu3.branchPred.usedRAS 1989 # Number of times the RAS was used to get a target. 186411507SCurtis.Dunham@arm.comsystem.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. 186511507SCurtis.Dunham@arm.comsystem.cpu3.branchPred.indirectLookups 53501 # Number of indirect predictor lookups. 186611507SCurtis.Dunham@arm.comsystem.cpu3.branchPred.indirectHits 43109 # Number of indirect target hits. 186711507SCurtis.Dunham@arm.comsystem.cpu3.branchPred.indirectMisses 10392 # Number of indirect misses. 186811507SCurtis.Dunham@arm.comsystem.cpu3.branchPredindirectMispredicted 1225 # Number of mispredicted indirect branches. 186911507SCurtis.Dunham@arm.comsystem.cpu3.numCycles 192748 # number of cpu cycles simulated 187011507SCurtis.Dunham@arm.comsystem.cpu3.numWorkItemsStarted 0 # number of work items this cpu started 187111507SCurtis.Dunham@arm.comsystem.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed 187211507SCurtis.Dunham@arm.comsystem.cpu3.fetch.icacheStallCycles 41262 # Number of cycles fetch is stalled on an Icache miss 187311507SCurtis.Dunham@arm.comsystem.cpu3.fetch.Insts 329189 # Number of instructions fetch has processed 187411507SCurtis.Dunham@arm.comsystem.cpu3.fetch.Branches 61800 # Number of branches that fetch encountered 187511507SCurtis.Dunham@arm.comsystem.cpu3.fetch.predictedBranches 45098 # Number of branches that fetch has predicted taken 187611507SCurtis.Dunham@arm.comsystem.cpu3.fetch.Cycles 145688 # Number of cycles fetch has run and was not squashing or blocked 187711507SCurtis.Dunham@arm.comsystem.cpu3.fetch.SquashCycles 4833 # Number of cycles fetch has spent squashing 187811507SCurtis.Dunham@arm.comsystem.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 187911507SCurtis.Dunham@arm.comsystem.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from 188011507SCurtis.Dunham@arm.comsystem.cpu3.fetch.PendingTrapStallCycles 1762 # Number of stall cycles due to pending traps 188111507SCurtis.Dunham@arm.comsystem.cpu3.fetch.CacheLines 30337 # Number of cache lines fetched 188211507SCurtis.Dunham@arm.comsystem.cpu3.fetch.IcacheSquashes 926 # Number of outstanding Icache misses that were squashed 188311507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::samples 191141 # Number of instructions fetched each cycle (Total) 188411507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::mean 1.722231 # Number of instructions fetched each cycle (Total) 188511507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::stdev 2.297340 # Number of instructions fetched each cycle (Total) 188611507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 188711507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::0 79632 41.66% 41.66% # Number of instructions fetched each cycle (Total) 188811507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::1 55527 29.05% 70.71% # Number of instructions fetched each cycle (Total) 188911507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::2 9457 4.95% 75.66% # Number of instructions fetched each cycle (Total) 189011507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::3 3401 1.78% 77.44% # Number of instructions fetched each cycle (Total) 189111507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::4 679 0.36% 77.79% # Number of instructions fetched each cycle (Total) 189211507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::5 31347 16.40% 94.19% # Number of instructions fetched each cycle (Total) 189311507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::6 1154 0.60% 94.80% # Number of instructions fetched each cycle (Total) 189411507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::7 1382 0.72% 95.52% # Number of instructions fetched each cycle (Total) 189511507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::8 8562 4.48% 100.00% # Number of instructions fetched each cycle (Total) 189611507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 189711507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 189811507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 189911507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rateDist::total 191141 # Number of instructions fetched each cycle (Total) 190011507SCurtis.Dunham@arm.comsystem.cpu3.fetch.branchRate 0.320626 # Number of branch fetches per cycle 190111507SCurtis.Dunham@arm.comsystem.cpu3.fetch.rate 1.707872 # Number of inst fetches per cycle 190211507SCurtis.Dunham@arm.comsystem.cpu3.decode.IdleCycles 22425 # Number of cycles decode is idle 190311507SCurtis.Dunham@arm.comsystem.cpu3.decode.BlockedCycles 81552 # Number of cycles decode is blocked 190411507SCurtis.Dunham@arm.comsystem.cpu3.decode.RunCycles 79630 # Number of cycles decode is running 190511507SCurtis.Dunham@arm.comsystem.cpu3.decode.UnblockCycles 5108 # Number of cycles decode is unblocking 190611507SCurtis.Dunham@arm.comsystem.cpu3.decode.SquashCycles 2416 # Number of cycles decode is squashing 190711507SCurtis.Dunham@arm.comsystem.cpu3.decode.DecodedInsts 297344 # Number of instructions handled by decode 190811507SCurtis.Dunham@arm.comsystem.cpu3.rename.SquashCycles 2416 # Number of cycles rename is squashing 190911507SCurtis.Dunham@arm.comsystem.cpu3.rename.IdleCycles 23427 # Number of cycles rename is idle 191011507SCurtis.Dunham@arm.comsystem.cpu3.rename.BlockCycles 40476 # Number of cycles rename is blocking 191111507SCurtis.Dunham@arm.comsystem.cpu3.rename.serializeStallCycles 14673 # count of cycles rename stalled for serializing inst 191211507SCurtis.Dunham@arm.comsystem.cpu3.rename.RunCycles 80471 # Number of cycles rename is running 191311507SCurtis.Dunham@arm.comsystem.cpu3.rename.UnblockCycles 29668 # Number of cycles rename is unblocking 191411507SCurtis.Dunham@arm.comsystem.cpu3.rename.RenamedInsts 290876 # Number of instructions processed by rename 191511507SCurtis.Dunham@arm.comsystem.cpu3.rename.IQFullEvents 25659 # Number of times rename has blocked due to IQ full 191611507SCurtis.Dunham@arm.comsystem.cpu3.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full 191711507SCurtis.Dunham@arm.comsystem.cpu3.rename.RenamedOperands 201895 # Number of destination operands rename has renamed 191811507SCurtis.Dunham@arm.comsystem.cpu3.rename.RenameLookups 544124 # Number of register rename lookups that rename has made 191911507SCurtis.Dunham@arm.comsystem.cpu3.rename.int_rename_lookups 425656 # Number of integer rename lookups 192011507SCurtis.Dunham@arm.comsystem.cpu3.rename.fp_rename_lookups 36 # Number of floating rename lookups 192111507SCurtis.Dunham@arm.comsystem.cpu3.rename.CommittedMaps 173837 # Number of HB maps that are committed 192211507SCurtis.Dunham@arm.comsystem.cpu3.rename.UndoneMaps 28058 # Number of HB maps that are undone due to squashing 192311507SCurtis.Dunham@arm.comsystem.cpu3.rename.serializingInsts 1657 # count of serializing insts renamed 192411507SCurtis.Dunham@arm.comsystem.cpu3.rename.tempSerializingInsts 1795 # count of temporary serializing insts renamed 192511507SCurtis.Dunham@arm.comsystem.cpu3.rename.skidInsts 35428 # count of insts added to the skid buffer 192611507SCurtis.Dunham@arm.comsystem.cpu3.memDep0.insertedLoads 77674 # Number of loads inserted to the mem dependence unit. 192711507SCurtis.Dunham@arm.comsystem.cpu3.memDep0.insertedStores 35638 # Number of stores inserted to the mem dependence unit. 192811507SCurtis.Dunham@arm.comsystem.cpu3.memDep0.conflictingLoads 37571 # Number of conflicting loads. 192911507SCurtis.Dunham@arm.comsystem.cpu3.memDep0.conflictingStores 29275 # Number of conflicting stores. 193011507SCurtis.Dunham@arm.comsystem.cpu3.iq.iqInstsAdded 234657 # Number of instructions added to the IQ (excludes non-spec) 193111507SCurtis.Dunham@arm.comsystem.cpu3.iq.iqNonSpecInstsAdded 9848 # Number of non-speculative instructions added to the IQ 193211507SCurtis.Dunham@arm.comsystem.cpu3.iq.iqInstsIssued 236528 # Number of instructions issued 193311507SCurtis.Dunham@arm.comsystem.cpu3.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued 193411507SCurtis.Dunham@arm.comsystem.cpu3.iq.iqSquashedInstsExamined 24579 # Number of squashed instructions iterated over during squash; mainly for profiling 193511507SCurtis.Dunham@arm.comsystem.cpu3.iq.iqSquashedOperandsExamined 19470 # Number of squashed operands that are examined and possibly removed from graph 193611507SCurtis.Dunham@arm.comsystem.cpu3.iq.iqSquashedNonSpecRemoved 1266 # Number of squashed non-spec instructions that were removed 193711507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::samples 191141 # Number of insts issued each cycle 193811507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::mean 1.237453 # Number of insts issued each cycle 193911507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::stdev 1.372875 # Number of insts issued each cycle 194011507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 194111507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::0 84630 44.28% 44.28% # Number of insts issued each cycle 194211507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::1 31019 16.23% 60.50% # Number of insts issued each cycle 194311507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::2 34273 17.93% 78.44% # Number of insts issued each cycle 194411507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::3 34156 17.87% 96.30% # Number of insts issued each cycle 194511507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::4 3613 1.89% 98.20% # Number of insts issued each cycle 194611507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::5 1675 0.88% 99.07% # Number of insts issued each cycle 194711507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::6 1066 0.56% 99.63% # Number of insts issued each cycle 194811507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::7 400 0.21% 99.84% # Number of insts issued each cycle 194911507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::8 309 0.16% 100.00% # Number of insts issued each cycle 195011507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 195111507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 195211507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 195311507SCurtis.Dunham@arm.comsystem.cpu3.iq.issued_per_cycle::total 191141 # Number of insts issued each cycle 195411507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 195511507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::IntAlu 176 38.18% 38.18% # attempts to use FU when none available 195611507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::IntMult 0 0.00% 38.18% # attempts to use FU when none available 195711507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::IntDiv 0 0.00% 38.18% # attempts to use FU when none available 195811507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::FloatAdd 0 0.00% 38.18% # attempts to use FU when none available 195911507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::FloatCmp 0 0.00% 38.18% # attempts to use FU when none available 196011507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::FloatCvt 0 0.00% 38.18% # attempts to use FU when none available 196111507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::FloatMult 0 0.00% 38.18% # attempts to use FU when none available 196211507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::FloatDiv 0 0.00% 38.18% # attempts to use FU when none available 196311507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::FloatSqrt 0 0.00% 38.18% # attempts to use FU when none available 196411507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdAdd 0 0.00% 38.18% # attempts to use FU when none available 196511507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 38.18% # attempts to use FU when none available 196611507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdAlu 0 0.00% 38.18% # attempts to use FU when none available 196711507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdCmp 0 0.00% 38.18% # attempts to use FU when none available 196811507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdCvt 0 0.00% 38.18% # attempts to use FU when none available 196911507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdMisc 0 0.00% 38.18% # attempts to use FU when none available 197011507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdMult 0 0.00% 38.18% # attempts to use FU when none available 197111507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 38.18% # attempts to use FU when none available 197211507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdShift 0 0.00% 38.18% # attempts to use FU when none available 197311507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 38.18% # attempts to use FU when none available 197411507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdSqrt 0 0.00% 38.18% # attempts to use FU when none available 197511507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 38.18% # attempts to use FU when none available 197611507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 38.18% # attempts to use FU when none available 197711507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 38.18% # attempts to use FU when none available 197811507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 38.18% # attempts to use FU when none available 197911507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 38.18% # attempts to use FU when none available 198011507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 38.18% # attempts to use FU when none available 198111507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 38.18% # attempts to use FU when none available 198211507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.18% # attempts to use FU when none available 198311507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 38.18% # attempts to use FU when none available 198411507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::MemRead 50 10.85% 49.02% # attempts to use FU when none available 198511507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::MemWrite 235 50.98% 100.00% # attempts to use FU when none available 198611507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 198711507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 198811507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 198911507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::IntAlu 117496 49.68% 49.68% # Type of FU issued 199011507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.68% # Type of FU issued 199111507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.68% # Type of FU issued 199211507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.68% # Type of FU issued 199311507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.68% # Type of FU issued 199411507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.68% # Type of FU issued 199511507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.68% # Type of FU issued 199611507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.68% # Type of FU issued 199711507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.68% # Type of FU issued 199811507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.68% # Type of FU issued 199911507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.68% # Type of FU issued 200011507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.68% # Type of FU issued 200111507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.68% # Type of FU issued 200211507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.68% # Type of FU issued 200311507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.68% # Type of FU issued 200411507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.68% # Type of FU issued 200511507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.68% # Type of FU issued 200611507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.68% # Type of FU issued 200711507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.68% # Type of FU issued 200811507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.68% # Type of FU issued 200911507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.68% # Type of FU issued 201011507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.68% # Type of FU issued 201111507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.68% # Type of FU issued 201211507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.68% # Type of FU issued 201311507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.68% # Type of FU issued 201411507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.68% # Type of FU issued 201511507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.68% # Type of FU issued 201611507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.68% # Type of FU issued 201711507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.68% # Type of FU issued 201811507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::MemRead 84415 35.69% 85.36% # Type of FU issued 201911507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::MemWrite 34617 14.64% 100.00% # Type of FU issued 202011507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 202111507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 202211507SCurtis.Dunham@arm.comsystem.cpu3.iq.FU_type_0::total 236528 # Type of FU issued 202311507SCurtis.Dunham@arm.comsystem.cpu3.iq.rate 1.227136 # Inst issue rate 202411507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_busy_cnt 461 # FU busy when requested 202511507SCurtis.Dunham@arm.comsystem.cpu3.iq.fu_busy_rate 0.001949 # FU busy rate (busy events/executed inst) 202611507SCurtis.Dunham@arm.comsystem.cpu3.iq.int_inst_queue_reads 664726 # Number of integer instruction queue reads 202711507SCurtis.Dunham@arm.comsystem.cpu3.iq.int_inst_queue_writes 269047 # Number of integer instruction queue writes 202811507SCurtis.Dunham@arm.comsystem.cpu3.iq.int_inst_queue_wakeup_accesses 232596 # Number of integer instruction queue wakeup accesses 202911507SCurtis.Dunham@arm.comsystem.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 203011507SCurtis.Dunham@arm.comsystem.cpu3.iq.fp_inst_queue_writes 72 # Number of floating instruction queue writes 203111507SCurtis.Dunham@arm.comsystem.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 203211507SCurtis.Dunham@arm.comsystem.cpu3.iq.int_alu_accesses 236989 # Number of integer alu accesses 203311507SCurtis.Dunham@arm.comsystem.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses 203411507SCurtis.Dunham@arm.comsystem.cpu3.iew.lsq.thread0.forwLoads 29180 # Number of loads that had data forwarded from stores 203511507SCurtis.Dunham@arm.comsystem.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 203611507SCurtis.Dunham@arm.comsystem.cpu3.iew.lsq.thread0.squashedLoads 4384 # Number of loads squashed 203711507SCurtis.Dunham@arm.comsystem.cpu3.iew.lsq.thread0.ignoredResponses 23 # Number of memory responses ignored because the instruction is squashed 203811507SCurtis.Dunham@arm.comsystem.cpu3.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations 203911507SCurtis.Dunham@arm.comsystem.cpu3.iew.lsq.thread0.squashedStores 2661 # Number of stores squashed 204011507SCurtis.Dunham@arm.comsystem.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 204111507SCurtis.Dunham@arm.comsystem.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 204211507SCurtis.Dunham@arm.comsystem.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 204311507SCurtis.Dunham@arm.comsystem.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 204411507SCurtis.Dunham@arm.comsystem.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle 204511507SCurtis.Dunham@arm.comsystem.cpu3.iew.iewSquashCycles 2416 # Number of cycles IEW is squashing 204611507SCurtis.Dunham@arm.comsystem.cpu3.iew.iewBlockCycles 11113 # Number of cycles IEW is blocking 204711507SCurtis.Dunham@arm.comsystem.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking 204811507SCurtis.Dunham@arm.comsystem.cpu3.iew.iewDispatchedInsts 283276 # Number of instructions dispatched to IQ 204911507SCurtis.Dunham@arm.comsystem.cpu3.iew.iewDispSquashedInsts 304 # Number of squashed instructions skipped by dispatch 205011507SCurtis.Dunham@arm.comsystem.cpu3.iew.iewDispLoadInsts 77674 # Number of dispatched load instructions 205111507SCurtis.Dunham@arm.comsystem.cpu3.iew.iewDispStoreInsts 35638 # Number of dispatched store instructions 205211507SCurtis.Dunham@arm.comsystem.cpu3.iew.iewDispNonSpecInsts 1522 # Number of dispatched non-speculative instructions 205311507SCurtis.Dunham@arm.comsystem.cpu3.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall 205411507SCurtis.Dunham@arm.comsystem.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 205511507SCurtis.Dunham@arm.comsystem.cpu3.iew.memOrderViolationEvents 35 # Number of memory order violations 205611507SCurtis.Dunham@arm.comsystem.cpu3.iew.predictedTakenIncorrect 471 # Number of branches that were predicted taken incorrectly 205711507SCurtis.Dunham@arm.comsystem.cpu3.iew.predictedNotTakenIncorrect 2483 # Number of branches that were predicted not taken incorrectly 205811507SCurtis.Dunham@arm.comsystem.cpu3.iew.branchMispredicts 2954 # Number of branch mispredicts detected at execute 205911507SCurtis.Dunham@arm.comsystem.cpu3.iew.iewExecutedInsts 233943 # Number of executed instructions 206011507SCurtis.Dunham@arm.comsystem.cpu3.iew.iewExecLoadInsts 76012 # Number of load instructions executed 206111507SCurtis.Dunham@arm.comsystem.cpu3.iew.iewExecSquashedInsts 2585 # Number of squashed instructions skipped in execute 206211507SCurtis.Dunham@arm.comsystem.cpu3.iew.exec_swp 0 # number of swp insts executed 206311507SCurtis.Dunham@arm.comsystem.cpu3.iew.exec_nop 38771 # number of nop insts executed 206411507SCurtis.Dunham@arm.comsystem.cpu3.iew.exec_refs 110309 # number of memory reference insts executed 206511507SCurtis.Dunham@arm.comsystem.cpu3.iew.exec_branches 49060 # Number of branches executed 206611507SCurtis.Dunham@arm.comsystem.cpu3.iew.exec_stores 34297 # Number of stores executed 206711507SCurtis.Dunham@arm.comsystem.cpu3.iew.exec_rate 1.213725 # Inst execution rate 206811507SCurtis.Dunham@arm.comsystem.cpu3.iew.wb_sent 233093 # cumulative count of insts sent to commit 206911507SCurtis.Dunham@arm.comsystem.cpu3.iew.wb_count 232596 # cumulative count of insts written-back 207011507SCurtis.Dunham@arm.comsystem.cpu3.iew.wb_producers 128296 # num instructions producing a value 207111507SCurtis.Dunham@arm.comsystem.cpu3.iew.wb_consumers 135910 # num instructions consuming a value 207211507SCurtis.Dunham@arm.comsystem.cpu3.iew.wb_rate 1.206736 # insts written-back per cycle 207311507SCurtis.Dunham@arm.comsystem.cpu3.iew.wb_fanout 0.943978 # average fanout of values written-back 207411507SCurtis.Dunham@arm.comsystem.cpu3.commit.commitSquashedInsts 25736 # The number of squashed insts skipped by commit 207511507SCurtis.Dunham@arm.comsystem.cpu3.commit.commitNonSpecStalls 8582 # The number of times commit has been forced to stall to communicate backwards 207611507SCurtis.Dunham@arm.comsystem.cpu3.commit.branchMispredicts 2339 # The number of times a branch was mispredicted 207711507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::samples 186297 # Number of insts commited each cycle 207811507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::mean 1.382277 # Number of insts commited each cycle 207911507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::stdev 1.944418 # Number of insts commited each cycle 208011507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 208111507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::0 92574 49.69% 49.69% # Number of insts commited each cycle 208211507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::1 45329 24.33% 74.02% # Number of insts commited each cycle 208311507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::2 5460 2.93% 76.95% # Number of insts commited each cycle 208411507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::3 9239 4.96% 81.91% # Number of insts commited each cycle 208511507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::4 1287 0.69% 82.60% # Number of insts commited each cycle 208611507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::5 29468 15.82% 98.42% # Number of insts commited each cycle 208711507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::6 712 0.38% 98.80% # Number of insts commited each cycle 208811507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::7 1036 0.56% 99.36% # Number of insts commited each cycle 208911507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::8 1192 0.64% 100.00% # Number of insts commited each cycle 209011507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 209111507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 209211507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 209311507SCurtis.Dunham@arm.comsystem.cpu3.commit.committed_per_cycle::total 186297 # Number of insts commited each cycle 209411507SCurtis.Dunham@arm.comsystem.cpu3.commit.committedInsts 257514 # Number of instructions committed 209511507SCurtis.Dunham@arm.comsystem.cpu3.commit.committedOps 257514 # Number of ops (including micro ops) committed 209611507SCurtis.Dunham@arm.comsystem.cpu3.commit.swp_count 0 # Number of s/w prefetches committed 209711507SCurtis.Dunham@arm.comsystem.cpu3.commit.refs 106267 # Number of memory references committed 209811507SCurtis.Dunham@arm.comsystem.cpu3.commit.loads 73290 # Number of loads committed 209911507SCurtis.Dunham@arm.comsystem.cpu3.commit.membars 7865 # Number of memory barriers committed 210011507SCurtis.Dunham@arm.comsystem.cpu3.commit.branches 46801 # Number of branches committed 210111507SCurtis.Dunham@arm.comsystem.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. 210211507SCurtis.Dunham@arm.comsystem.cpu3.commit.int_insts 175188 # Number of committed integer instructions. 210311507SCurtis.Dunham@arm.comsystem.cpu3.commit.function_calls 322 # Number of function calls committed. 210411507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::No_OpClass 37588 14.60% 14.60% # Class of committed instruction 210511507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::IntAlu 105794 41.08% 55.68% # Class of committed instruction 210611507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::IntMult 0 0.00% 55.68% # Class of committed instruction 210711507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.68% # Class of committed instruction 210811507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.68% # Class of committed instruction 210911507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.68% # Class of committed instruction 211011507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.68% # Class of committed instruction 211111507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.68% # Class of committed instruction 211211507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.68% # Class of committed instruction 211311507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.68% # Class of committed instruction 211411507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.68% # Class of committed instruction 211511507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.68% # Class of committed instruction 211611507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.68% # Class of committed instruction 211711507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.68% # Class of committed instruction 211811507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.68% # Class of committed instruction 211911507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.68% # Class of committed instruction 212011507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.68% # Class of committed instruction 212111507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.68% # Class of committed instruction 212211507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.68% # Class of committed instruction 212311507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.68% # Class of committed instruction 212411507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.68% # Class of committed instruction 212511507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.68% # Class of committed instruction 212611507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.68% # Class of committed instruction 212711507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.68% # Class of committed instruction 212811507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.68% # Class of committed instruction 212911507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.68% # Class of committed instruction 213011507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.68% # Class of committed instruction 213111507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.68% # Class of committed instruction 213211507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.68% # Class of committed instruction 213311507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.68% # Class of committed instruction 213411507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::MemRead 81155 31.51% 87.19% # Class of committed instruction 213511507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::MemWrite 32977 12.81% 100.00% # Class of committed instruction 213611507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 213711507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 213811507SCurtis.Dunham@arm.comsystem.cpu3.commit.op_class_0::total 257514 # Class of committed instruction 213911507SCurtis.Dunham@arm.comsystem.cpu3.commit.bw_lim_events 1192 # number cycles where commit BW limit reached 214011507SCurtis.Dunham@arm.comsystem.cpu3.rob.rob_reads 467769 # The number of ROB reads 214111507SCurtis.Dunham@arm.comsystem.cpu3.rob.rob_writes 571412 # The number of ROB writes 214211507SCurtis.Dunham@arm.comsystem.cpu3.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself 214311507SCurtis.Dunham@arm.comsystem.cpu3.idleCycles 1607 # Total number of cycles that the CPU has spent unscheduled due to idling 214411507SCurtis.Dunham@arm.comsystem.cpu3.quiesceCycles 48179 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 214511507SCurtis.Dunham@arm.comsystem.cpu3.committedInsts 212061 # Number of Instructions Simulated 214611507SCurtis.Dunham@arm.comsystem.cpu3.committedOps 212061 # Number of Ops (including micro ops) Simulated 214711507SCurtis.Dunham@arm.comsystem.cpu3.cpi 0.908927 # CPI: Cycles Per Instruction 214811507SCurtis.Dunham@arm.comsystem.cpu3.cpi_total 0.908927 # CPI: Total CPI of All Threads 214911507SCurtis.Dunham@arm.comsystem.cpu3.ipc 1.100198 # IPC: Instructions Per Cycle 215011507SCurtis.Dunham@arm.comsystem.cpu3.ipc_total 1.100198 # IPC: Total IPC of All Threads 215111507SCurtis.Dunham@arm.comsystem.cpu3.int_regfile_reads 395124 # number of integer regfile reads 215211507SCurtis.Dunham@arm.comsystem.cpu3.int_regfile_writes 185063 # number of integer regfile writes 215311507SCurtis.Dunham@arm.comsystem.cpu3.fp_regfile_writes 64 # number of floating regfile writes 215411507SCurtis.Dunham@arm.comsystem.cpu3.misc_regfile_reads 112177 # number of misc regfile reads 215511507SCurtis.Dunham@arm.comsystem.cpu3.misc_regfile_writes 648 # number of misc regfile writes 215611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.replacements 0 # number of replacements 215711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.tagsinuse 24.465247 # Cycle average of tags in use 215811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.total_refs 40069 # Total number of references to valid blocks. 215911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. 216011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.avg_refs 1381.689655 # Average number of references to valid blocks. 216111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 216211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.occ_blocks::cpu3.data 24.465247 # Average occupied blocks per requestor 216311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.occ_percent::cpu3.data 0.047784 # Average percentage of cache occupancy 216411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.occ_percent::total 0.047784 # Average percentage of cache occupancy 216511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id 216611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 216711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 216811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id 216911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.tag_accesses 319388 # Number of tag accesses 217011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.tags.data_accesses 319388 # Number of data accesses 217111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_hits::cpu3.data 46353 # number of ReadReq hits 217211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_hits::total 46353 # number of ReadReq hits 217311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_hits::cpu3.data 32769 # number of WriteReq hits 217411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_hits::total 32769 # number of WriteReq hits 217511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits 217611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits 217711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_hits::cpu3.data 79122 # number of demand (read+write) hits 217811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_hits::total 79122 # number of demand (read+write) hits 217911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_hits::cpu3.data 79122 # number of overall hits 218011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_hits::total 79122 # number of overall hits 218111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_misses::cpu3.data 454 # number of ReadReq misses 218211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_misses::total 454 # number of ReadReq misses 218311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_misses::cpu3.data 137 # number of WriteReq misses 218411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_misses::total 137 # number of WriteReq misses 218511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses 218611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses 218711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_misses::cpu3.data 591 # number of demand (read+write) misses 218811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_misses::total 591 # number of demand (read+write) misses 218911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_misses::cpu3.data 591 # number of overall misses 219011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_misses::total 591 # number of overall misses 219111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_miss_latency::cpu3.data 6996500 # number of ReadReq miss cycles 219211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_miss_latency::total 6996500 # number of ReadReq miss cycles 219311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2957500 # number of WriteReq miss cycles 219411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_miss_latency::total 2957500 # number of WriteReq miss cycles 219511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_miss_latency::cpu3.data 770500 # number of SwapReq miss cycles 219611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_miss_latency::total 770500 # number of SwapReq miss cycles 219711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_miss_latency::cpu3.data 9954000 # number of demand (read+write) miss cycles 219811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_miss_latency::total 9954000 # number of demand (read+write) miss cycles 219911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_miss_latency::cpu3.data 9954000 # number of overall miss cycles 220011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_miss_latency::total 9954000 # number of overall miss cycles 220111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_accesses::cpu3.data 46807 # number of ReadReq accesses(hits+misses) 220211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_accesses::total 46807 # number of ReadReq accesses(hits+misses) 220311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_accesses::cpu3.data 32906 # number of WriteReq accesses(hits+misses) 220411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_accesses::total 32906 # number of WriteReq accesses(hits+misses) 220511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) 220611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) 220711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_accesses::cpu3.data 79713 # number of demand (read+write) accesses 220811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_accesses::total 79713 # number of demand (read+write) accesses 220911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_accesses::cpu3.data 79713 # number of overall (read+write) accesses 221011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_accesses::total 79713 # number of overall (read+write) accesses 221111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009699 # miss rate for ReadReq accesses 221211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_miss_rate::total 0.009699 # miss rate for ReadReq accesses 221311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004163 # miss rate for WriteReq accesses 221411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_miss_rate::total 0.004163 # miss rate for WriteReq accesses 221511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.788732 # miss rate for SwapReq accesses 221611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_miss_rate::total 0.788732 # miss rate for SwapReq accesses 221711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_miss_rate::cpu3.data 0.007414 # miss rate for demand accesses 221811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_miss_rate::total 0.007414 # miss rate for demand accesses 221911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_miss_rate::cpu3.data 0.007414 # miss rate for overall accesses 222011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_miss_rate::total 0.007414 # miss rate for overall accesses 222111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15410.792952 # average ReadReq miss latency 222211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_avg_miss_latency::total 15410.792952 # average ReadReq miss latency 222311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21587.591241 # average WriteReq miss latency 222411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_avg_miss_latency::total 21587.591241 # average WriteReq miss latency 222511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 13758.928571 # average SwapReq miss latency 222611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_avg_miss_latency::total 13758.928571 # average SwapReq miss latency 222711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16842.639594 # average overall miss latency 222811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_avg_miss_latency::total 16842.639594 # average overall miss latency 222911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16842.639594 # average overall miss latency 223011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_avg_miss_latency::total 16842.639594 # average overall miss latency 223111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 223211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 223311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 223411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked 223511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 223611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 223711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 292 # number of ReadReq MSHR hits 223811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_mshr_hits::total 292 # number of ReadReq MSHR hits 223911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 35 # number of WriteReq MSHR hits 224011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits 224111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 3 # number of SwapReq MSHR hits 224211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_mshr_hits::total 3 # number of SwapReq MSHR hits 224311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_mshr_hits::cpu3.data 327 # number of demand (read+write) MSHR hits 224411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_mshr_hits::total 327 # number of demand (read+write) MSHR hits 224511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_mshr_hits::cpu3.data 327 # number of overall MSHR hits 224611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_mshr_hits::total 327 # number of overall MSHR hits 224711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 162 # number of ReadReq MSHR misses 224811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses 224911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 102 # number of WriteReq MSHR misses 225011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses 225111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses 225211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses 225311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses 225411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses 225511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses 225611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses 225711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1605500 # number of ReadReq MSHR miss cycles 225811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_mshr_miss_latency::total 1605500 # number of ReadReq MSHR miss cycles 225911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1601500 # number of WriteReq MSHR miss cycles 226011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_miss_latency::total 1601500 # number of WriteReq MSHR miss cycles 226111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 714500 # number of SwapReq MSHR miss cycles 226211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_mshr_miss_latency::total 714500 # number of SwapReq MSHR miss cycles 226311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3207000 # number of demand (read+write) MSHR miss cycles 226411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_mshr_miss_latency::total 3207000 # number of demand (read+write) MSHR miss cycles 226511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3207000 # number of overall MSHR miss cycles 226611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_mshr_miss_latency::total 3207000 # number of overall MSHR miss cycles 226711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003461 # mshr miss rate for ReadReq accesses 226811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003461 # mshr miss rate for ReadReq accesses 226911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003100 # mshr miss rate for WriteReq accesses 227011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003100 # mshr miss rate for WriteReq accesses 227111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.746479 # mshr miss rate for SwapReq accesses 227211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.746479 # mshr miss rate for SwapReq accesses 227311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003312 # mshr miss rate for demand accesses 227411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_mshr_miss_rate::total 0.003312 # mshr miss rate for demand accesses 227511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003312 # mshr miss rate for overall accesses 227611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_mshr_miss_rate::total 0.003312 # mshr miss rate for overall accesses 227711507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9910.493827 # average ReadReq mshr miss latency 227811507SCurtis.Dunham@arm.comsystem.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9910.493827 # average ReadReq mshr miss latency 227911507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15700.980392 # average WriteReq mshr miss latency 228011507SCurtis.Dunham@arm.comsystem.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15700.980392 # average WriteReq mshr miss latency 228111507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 13481.132075 # average SwapReq mshr miss latency 228211507SCurtis.Dunham@arm.comsystem.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 13481.132075 # average SwapReq mshr miss latency 228311507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12147.727273 # average overall mshr miss latency 228411507SCurtis.Dunham@arm.comsystem.cpu3.dcache.demand_avg_mshr_miss_latency::total 12147.727273 # average overall mshr miss latency 228511507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12147.727273 # average overall mshr miss latency 228611507SCurtis.Dunham@arm.comsystem.cpu3.dcache.overall_avg_mshr_miss_latency::total 12147.727273 # average overall mshr miss latency 228711507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.replacements 563 # number of replacements 228811507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.tagsinuse 93.764815 # Cycle average of tags in use 228911507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.total_refs 29516 # Total number of references to valid blocks. 229011507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.sampled_refs 701 # Sample count of references to valid blocks. 229111507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.avg_refs 42.105563 # Average number of references to valid blocks. 229211507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 229311507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_blocks::cpu3.inst 93.764815 # Average occupied blocks per requestor 229411507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_percent::cpu3.inst 0.183134 # Average percentage of cache occupancy 229511507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_percent::total 0.183134 # Average percentage of cache occupancy 229611507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id 229711507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 229811507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 229911507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id 230011507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.occ_task_id_percent::1024 0.269531 # Percentage of cache occupancy per task id 230111507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.tag_accesses 31038 # Number of tag accesses 230211507SCurtis.Dunham@arm.comsystem.cpu3.icache.tags.data_accesses 31038 # Number of data accesses 230311507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_hits::cpu3.inst 29516 # number of ReadReq hits 230411507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_hits::total 29516 # number of ReadReq hits 230511507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_hits::cpu3.inst 29516 # number of demand (read+write) hits 230611507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_hits::total 29516 # number of demand (read+write) hits 230711507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_hits::cpu3.inst 29516 # number of overall hits 230811507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_hits::total 29516 # number of overall hits 230911507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_misses::cpu3.inst 821 # number of ReadReq misses 231011507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_misses::total 821 # number of ReadReq misses 231111507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_misses::cpu3.inst 821 # number of demand (read+write) misses 231211507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_misses::total 821 # number of demand (read+write) misses 231311507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_misses::cpu3.inst 821 # number of overall misses 231411507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_misses::total 821 # number of overall misses 231511507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_miss_latency::cpu3.inst 11709000 # number of ReadReq miss cycles 231611507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_miss_latency::total 11709000 # number of ReadReq miss cycles 231711507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_miss_latency::cpu3.inst 11709000 # number of demand (read+write) miss cycles 231811507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_miss_latency::total 11709000 # number of demand (read+write) miss cycles 231911507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_miss_latency::cpu3.inst 11709000 # number of overall miss cycles 232011507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_miss_latency::total 11709000 # number of overall miss cycles 232111507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_accesses::cpu3.inst 30337 # number of ReadReq accesses(hits+misses) 232211507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_accesses::total 30337 # number of ReadReq accesses(hits+misses) 232311507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_accesses::cpu3.inst 30337 # number of demand (read+write) accesses 232411507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_accesses::total 30337 # number of demand (read+write) accesses 232511507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_accesses::cpu3.inst 30337 # number of overall (read+write) accesses 232611507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_accesses::total 30337 # number of overall (read+write) accesses 232711507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.027063 # miss rate for ReadReq accesses 232811507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_miss_rate::total 0.027063 # miss rate for ReadReq accesses 232911507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_miss_rate::cpu3.inst 0.027063 # miss rate for demand accesses 233011507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_miss_rate::total 0.027063 # miss rate for demand accesses 233111507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_miss_rate::cpu3.inst 0.027063 # miss rate for overall accesses 233211507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_miss_rate::total 0.027063 # miss rate for overall accesses 233311507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14261.875761 # average ReadReq miss latency 233411507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_avg_miss_latency::total 14261.875761 # average ReadReq miss latency 233511507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14261.875761 # average overall miss latency 233611507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_avg_miss_latency::total 14261.875761 # average overall miss latency 233711507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14261.875761 # average overall miss latency 233811507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_avg_miss_latency::total 14261.875761 # average overall miss latency 233911507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 234011507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 234111507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked 234211507SCurtis.Dunham@arm.comsystem.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked 234311507SCurtis.Dunham@arm.comsystem.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 234411507SCurtis.Dunham@arm.comsystem.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 234511507SCurtis.Dunham@arm.comsystem.cpu3.icache.writebacks::writebacks 563 # number of writebacks 234611507SCurtis.Dunham@arm.comsystem.cpu3.icache.writebacks::total 563 # number of writebacks 234711507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 120 # number of ReadReq MSHR hits 234811507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits 234911507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_hits::cpu3.inst 120 # number of demand (read+write) MSHR hits 235011507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_hits::total 120 # number of demand (read+write) MSHR hits 235111507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_hits::cpu3.inst 120 # number of overall MSHR hits 235211507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_hits::total 120 # number of overall MSHR hits 235311507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 701 # number of ReadReq MSHR misses 235411507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_misses::total 701 # number of ReadReq MSHR misses 235511507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_misses::cpu3.inst 701 # number of demand (read+write) MSHR misses 235611507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_misses::total 701 # number of demand (read+write) MSHR misses 235711507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_misses::cpu3.inst 701 # number of overall MSHR misses 235811507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_misses::total 701 # number of overall MSHR misses 235911507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 10046500 # number of ReadReq MSHR miss cycles 236011507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_miss_latency::total 10046500 # number of ReadReq MSHR miss cycles 236111507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 10046500 # number of demand (read+write) MSHR miss cycles 236211507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_miss_latency::total 10046500 # number of demand (read+write) MSHR miss cycles 236311507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 10046500 # number of overall MSHR miss cycles 236411507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_miss_latency::total 10046500 # number of overall MSHR miss cycles 236511507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023107 # mshr miss rate for ReadReq accesses 236611507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023107 # mshr miss rate for ReadReq accesses 236711507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023107 # mshr miss rate for demand accesses 236811507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_mshr_miss_rate::total 0.023107 # mshr miss rate for demand accesses 236911507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023107 # mshr miss rate for overall accesses 237011507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_mshr_miss_rate::total 0.023107 # mshr miss rate for overall accesses 237111507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average ReadReq mshr miss latency 237211507SCurtis.Dunham@arm.comsystem.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 14331.669044 # average ReadReq mshr miss latency 237311507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average overall mshr miss latency 237411507SCurtis.Dunham@arm.comsystem.cpu3.icache.demand_avg_mshr_miss_latency::total 14331.669044 # average overall mshr miss latency 237511507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average overall mshr miss latency 237611507SCurtis.Dunham@arm.comsystem.cpu3.icache.overall_avg_mshr_miss_latency::total 14331.669044 # average overall mshr miss latency 237711507SCurtis.Dunham@arm.comsystem.l2c.tags.replacements 0 # number of replacements 237811507SCurtis.Dunham@arm.comsystem.l2c.tags.tagsinuse 455.287968 # Cycle average of tags in use 237911507SCurtis.Dunham@arm.comsystem.l2c.tags.total_refs 3075 # Total number of references to valid blocks. 238011507SCurtis.Dunham@arm.comsystem.l2c.tags.sampled_refs 580 # Sample count of references to valid blocks. 238111507SCurtis.Dunham@arm.comsystem.l2c.tags.avg_refs 5.301724 # Average number of references to valid blocks. 238211507SCurtis.Dunham@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 238311507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::writebacks 0.808056 # Average occupied blocks per requestor 238411507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 302.503225 # Average occupied blocks per requestor 238511507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 58.822483 # Average occupied blocks per requestor 238611507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 70.101034 # Average occupied blocks per requestor 238711507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 5.583860 # Average occupied blocks per requestor 238811507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu2.inst 9.384250 # Average occupied blocks per requestor 238911507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu2.data 1.286758 # Average occupied blocks per requestor 239011507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu3.inst 5.637625 # Average occupied blocks per requestor 239111507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu3.data 1.160677 # Average occupied blocks per requestor 239211507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy 239311507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.004616 # Average percentage of cache occupancy 239411507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.000898 # Average percentage of cache occupancy 239511507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.001070 # Average percentage of cache occupancy 239611507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.000085 # Average percentage of cache occupancy 239711507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu2.inst 0.000143 # Average percentage of cache occupancy 239811507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu2.data 0.000020 # Average percentage of cache occupancy 239911507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu3.inst 0.000086 # Average percentage of cache occupancy 240011507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu3.data 0.000018 # Average percentage of cache occupancy 240111507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::total 0.006947 # Average percentage of cache occupancy 240211507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 580 # Occupied blocks per task id 240311507SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 240411507SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id 240511507SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id 240611507SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.008850 # Percentage of cache occupancy per task id 240711507SCurtis.Dunham@arm.comsystem.l2c.tags.tag_accesses 31874 # Number of tag accesses 240811507SCurtis.Dunham@arm.comsystem.l2c.tags.data_accesses 31874 # Number of data accesses 240911507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits 241011507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits 241111507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_hits::writebacks 709 # number of WritebackClean hits 241211507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_hits::total 709 # number of WritebackClean hits 241311507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits 241411507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits 241511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu0.inst 319 # number of ReadCleanReq hits 241611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu1.inst 617 # number of ReadCleanReq hits 241711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu2.inst 711 # number of ReadCleanReq hits 241811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::cpu3.inst 686 # number of ReadCleanReq hits 241911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_hits::total 2333 # number of ReadCleanReq hits 242011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits 242111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits 242211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits 242311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits 242411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits 242511507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.inst 319 # number of demand (read+write) hits 242611507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits 242711507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.inst 617 # number of demand (read+write) hits 242811507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits 242911507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu2.inst 711 # number of demand (read+write) hits 243011507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits 243111507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu3.inst 686 # number of demand (read+write) hits 243211507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits 243311507SCurtis.Dunham@arm.comsystem.l2c.demand_hits::total 2365 # number of demand (read+write) hits 243411507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.inst 319 # number of overall hits 243511507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.data 5 # number of overall hits 243611507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.inst 617 # number of overall hits 243711507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.data 5 # number of overall hits 243811507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu2.inst 711 # number of overall hits 243911507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu2.data 11 # number of overall hits 244011507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu3.inst 686 # number of overall hits 244111507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu3.data 11 # number of overall hits 244211507SCurtis.Dunham@arm.comsystem.l2c.overall_hits::total 2365 # number of overall hits 244311507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 21 # number of UpgradeReq misses 244411507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses 244511507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu2.data 24 # number of UpgradeReq misses 244611507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses 244711507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::total 85 # number of UpgradeReq misses 244811507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses 244911507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses 245011507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses 245111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses 245211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses 245311507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu0.inst 377 # number of ReadCleanReq misses 245411507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu1.inst 96 # number of ReadCleanReq misses 245511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu2.inst 22 # number of ReadCleanReq misses 245611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::cpu3.inst 15 # number of ReadCleanReq misses 245711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_misses::total 510 # number of ReadCleanReq misses 245811507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 76 # number of ReadSharedReq misses 245911507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 9 # number of ReadSharedReq misses 246011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu2.data 3 # number of ReadSharedReq misses 246111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses 246211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses 246311507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.inst 377 # number of demand (read+write) misses 246411507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.data 170 # number of demand (read+write) misses 246511507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.inst 96 # number of demand (read+write) misses 246611507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.data 22 # number of demand (read+write) misses 246711507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu2.inst 22 # number of demand (read+write) misses 246811507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu2.data 15 # number of demand (read+write) misses 246911507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu3.inst 15 # number of demand (read+write) misses 247011507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu3.data 14 # number of demand (read+write) misses 247111507SCurtis.Dunham@arm.comsystem.l2c.demand_misses::total 731 # number of demand (read+write) misses 247211507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.inst 377 # number of overall misses 247311507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.data 170 # number of overall misses 247411507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.inst 96 # number of overall misses 247511507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.data 22 # number of overall misses 247611507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu2.inst 22 # number of overall misses 247711507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu2.data 15 # number of overall misses 247811507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu3.inst 15 # number of overall misses 247911507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu3.data 14 # number of overall misses 248011507SCurtis.Dunham@arm.comsystem.l2c.overall_misses::total 731 # number of overall misses 248111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 7826000 # number of ReadExReq miss cycles 248211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 1039500 # number of ReadExReq miss cycles 248311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu2.data 940000 # number of ReadExReq miss cycles 248411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu3.data 937500 # number of ReadExReq miss cycles 248511507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::total 10743000 # number of ReadExReq miss cycles 248611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu0.inst 29108500 # number of ReadCleanReq miss cycles 248711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu1.inst 7180500 # number of ReadCleanReq miss cycles 248811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu2.inst 1748500 # number of ReadCleanReq miss cycles 248911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu3.inst 1200000 # number of ReadCleanReq miss cycles 249011507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_latency::total 39237500 # number of ReadCleanReq miss cycles 249111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 6133500 # number of ReadSharedReq miss cycles 249211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 728000 # number of ReadSharedReq miss cycles 249311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu2.data 251500 # number of ReadSharedReq miss cycles 249411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu3.data 195000 # number of ReadSharedReq miss cycles 249511507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 7308000 # number of ReadSharedReq miss cycles 249611507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 29108500 # number of demand (read+write) miss cycles 249711507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.data 13959500 # number of demand (read+write) miss cycles 249811507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 7180500 # number of demand (read+write) miss cycles 249911507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.data 1767500 # number of demand (read+write) miss cycles 250011507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu2.inst 1748500 # number of demand (read+write) miss cycles 250111507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu2.data 1191500 # number of demand (read+write) miss cycles 250211507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu3.inst 1200000 # number of demand (read+write) miss cycles 250311507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu3.data 1132500 # number of demand (read+write) miss cycles 250411507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::total 57288500 # number of demand (read+write) miss cycles 250511507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 29108500 # number of overall miss cycles 250611507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.data 13959500 # number of overall miss cycles 250711507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 7180500 # number of overall miss cycles 250811507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.data 1767500 # number of overall miss cycles 250911507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu2.inst 1748500 # number of overall miss cycles 251011507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu2.data 1191500 # number of overall miss cycles 251111507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu3.inst 1200000 # number of overall miss cycles 251211507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu3.data 1132500 # number of overall miss cycles 251311507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::total 57288500 # number of overall miss cycles 251411507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) 251511507SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) 251611507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_accesses::writebacks 709 # number of WritebackClean accesses(hits+misses) 251711507SCurtis.Dunham@arm.comsystem.l2c.WritebackClean_accesses::total 709 # number of WritebackClean accesses(hits+misses) 251811507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 24 # number of UpgradeReq accesses(hits+misses) 251911507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) 252011507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu2.data 24 # number of UpgradeReq accesses(hits+misses) 252111507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) 252211507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses) 252311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) 252411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) 252511507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 252611507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 252711507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) 252811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu0.inst 696 # number of ReadCleanReq accesses(hits+misses) 252911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu1.inst 713 # number of ReadCleanReq accesses(hits+misses) 253011507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu2.inst 733 # number of ReadCleanReq accesses(hits+misses) 253111507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::cpu3.inst 701 # number of ReadCleanReq accesses(hits+misses) 253211507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_accesses::total 2843 # number of ReadCleanReq accesses(hits+misses) 253311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 81 # number of ReadSharedReq accesses(hits+misses) 253411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 14 # number of ReadSharedReq accesses(hits+misses) 253511507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu2.data 14 # number of ReadSharedReq accesses(hits+misses) 253611507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu3.data 13 # number of ReadSharedReq accesses(hits+misses) 253711507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::total 122 # number of ReadSharedReq accesses(hits+misses) 253811507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.inst 696 # number of demand (read+write) accesses 253911507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.data 175 # number of demand (read+write) accesses 254011507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.inst 713 # number of demand (read+write) accesses 254111507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.data 27 # number of demand (read+write) accesses 254211507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu2.inst 733 # number of demand (read+write) accesses 254311507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses 254411507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu3.inst 701 # number of demand (read+write) accesses 254511507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses 254611507SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::total 3096 # number of demand (read+write) accesses 254711507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.inst 696 # number of overall (read+write) accesses 254811507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.data 175 # number of overall (read+write) accesses 254911507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.inst 713 # number of overall (read+write) accesses 255011507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.data 27 # number of overall (read+write) accesses 255111507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu2.inst 733 # number of overall (read+write) accesses 255211507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses 255311507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu3.inst 701 # number of overall (read+write) accesses 255411507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses 255511507SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::total 3096 # number of overall (read+write) accesses 255611507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.875000 # miss rate for UpgradeReq accesses 255711507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 255811507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses 255911507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses 256011507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.965909 # miss rate for UpgradeReq accesses 256111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses 256211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses 256311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses 256411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses 256511507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 256611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.541667 # miss rate for ReadCleanReq accesses 256711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.134642 # miss rate for ReadCleanReq accesses 256811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.030014 # miss rate for ReadCleanReq accesses 256911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.021398 # miss rate for ReadCleanReq accesses 257011507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_miss_rate::total 0.179388 # miss rate for ReadCleanReq accesses 257111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.938272 # miss rate for ReadSharedReq accesses 257211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.642857 # miss rate for ReadSharedReq accesses 257311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu2.data 0.214286 # miss rate for ReadSharedReq accesses 257411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadSharedReq accesses 257511507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.737705 # miss rate for ReadSharedReq accesses 257611507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.541667 # miss rate for demand accesses 257711507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.971429 # miss rate for demand accesses 257811507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.134642 # miss rate for demand accesses 257911507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.814815 # miss rate for demand accesses 258011507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu2.inst 0.030014 # miss rate for demand accesses 258111507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu2.data 0.576923 # miss rate for demand accesses 258211507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu3.inst 0.021398 # miss rate for demand accesses 258311507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu3.data 0.560000 # miss rate for demand accesses 258411507SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::total 0.236111 # miss rate for demand accesses 258511507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.541667 # miss rate for overall accesses 258611507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.971429 # miss rate for overall accesses 258711507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.134642 # miss rate for overall accesses 258811507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.814815 # miss rate for overall accesses 258911507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu2.inst 0.030014 # miss rate for overall accesses 259011507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu2.data 0.576923 # miss rate for overall accesses 259111507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu3.inst 0.021398 # miss rate for overall accesses 259211507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu3.data 0.560000 # miss rate for overall accesses 259311507SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::total 0.236111 # miss rate for overall accesses 259411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 83255.319149 # average ReadExReq miss latency 259511507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 79961.538462 # average ReadExReq miss latency 259611507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu2.data 78333.333333 # average ReadExReq miss latency 259711507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu3.data 78125 # average ReadExReq miss latency 259811507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 82007.633588 # average ReadExReq miss latency 259911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 77210.875332 # average ReadCleanReq miss latency 260011507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74796.875000 # average ReadCleanReq miss latency 260111507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 79477.272727 # average ReadCleanReq miss latency 260211507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 80000 # average ReadCleanReq miss latency 260311507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_miss_latency::total 76936.274510 # average ReadCleanReq miss latency 260411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80703.947368 # average ReadSharedReq miss latency 260511507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 80888.888889 # average ReadSharedReq miss latency 260611507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 83833.333333 # average ReadSharedReq miss latency 260711507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 97500 # average ReadSharedReq miss latency 260811507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 81200 # average ReadSharedReq miss latency 260911507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 77210.875332 # average overall miss latency 261011507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 82114.705882 # average overall miss latency 261111507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 74796.875000 # average overall miss latency 261211507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 80340.909091 # average overall miss latency 261311507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu2.inst 79477.272727 # average overall miss latency 261411507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu2.data 79433.333333 # average overall miss latency 261511507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu3.inst 80000 # average overall miss latency 261611507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu3.data 80892.857143 # average overall miss latency 261711507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::total 78370.041040 # average overall miss latency 261811507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 77210.875332 # average overall miss latency 261911507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 82114.705882 # average overall miss latency 262011507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 74796.875000 # average overall miss latency 262111507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 80340.909091 # average overall miss latency 262211507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu2.inst 79477.272727 # average overall miss latency 262311507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu2.data 79433.333333 # average overall miss latency 262411507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu3.inst 80000 # average overall miss latency 262511507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu3.data 80892.857143 # average overall miss latency 262611507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::total 78370.041040 # average overall miss latency 262711507SCurtis.Dunham@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 262811507SCurtis.Dunham@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 262911507SCurtis.Dunham@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 263011507SCurtis.Dunham@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 263111507SCurtis.Dunham@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 263211507SCurtis.Dunham@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 263311507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits 263411507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 263511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_hits::cpu2.inst 8 # number of ReadCleanReq MSHR hits 263611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_hits::cpu3.inst 4 # number of ReadCleanReq MSHR hits 263711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_hits::total 17 # number of ReadCleanReq MSHR hits 263811507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 263911507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 264011507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu2.inst 8 # number of demand (read+write) MSHR hits 264111507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu3.inst 4 # number of demand (read+write) MSHR hits 264211507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 264311507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 264411507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 264511507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu2.inst 8 # number of overall MSHR hits 264611507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu3.inst 4 # number of overall MSHR hits 264711507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits 264811507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 21 # number of UpgradeReq MSHR misses 264911507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses 265011507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu2.data 24 # number of UpgradeReq MSHR misses 265111507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses 265211507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 85 # number of UpgradeReq MSHR misses 265311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses 265411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses 265511507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses 265611507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses 265711507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses 265811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_misses::cpu0.inst 376 # number of ReadCleanReq MSHR misses 265911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_misses::cpu1.inst 92 # number of ReadCleanReq MSHR misses 266011507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_misses::cpu2.inst 14 # number of ReadCleanReq MSHR misses 266111507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_misses::cpu3.inst 11 # number of ReadCleanReq MSHR misses 266211507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_misses::total 493 # number of ReadCleanReq MSHR misses 266311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 76 # number of ReadSharedReq MSHR misses 266411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 9 # number of ReadSharedReq MSHR misses 266511507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu2.data 3 # number of ReadSharedReq MSHR misses 266611507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu3.data 2 # number of ReadSharedReq MSHR misses 266711507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses 266811507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 376 # number of demand (read+write) MSHR misses 266911507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 170 # number of demand (read+write) MSHR misses 267011507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 92 # number of demand (read+write) MSHR misses 267111507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses 267211507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu2.inst 14 # number of demand (read+write) MSHR misses 267311507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses 267411507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu3.inst 11 # number of demand (read+write) MSHR misses 267511507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu3.data 14 # number of demand (read+write) MSHR misses 267611507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::total 714 # number of demand (read+write) MSHR misses 267711507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 376 # number of overall MSHR misses 267811507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 170 # number of overall MSHR misses 267911507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 92 # number of overall MSHR misses 268011507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses 268111507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu2.inst 14 # number of overall MSHR misses 268211507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses 268311507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu3.inst 11 # number of overall MSHR misses 268411507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu3.data 14 # number of overall MSHR misses 268511507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::total 714 # number of overall MSHR misses 268611507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 419500 # number of UpgradeReq MSHR miss cycles 268711507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 400000 # number of UpgradeReq MSHR miss cycles 268811507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 480000 # number of UpgradeReq MSHR miss cycles 268911507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 398000 # number of UpgradeReq MSHR miss cycles 269011507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 1697500 # number of UpgradeReq MSHR miss cycles 269111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6886000 # number of ReadExReq MSHR miss cycles 269211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 909500 # number of ReadExReq MSHR miss cycles 269311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu2.data 820000 # number of ReadExReq MSHR miss cycles 269411507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu3.data 817500 # number of ReadExReq MSHR miss cycles 269511507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 9433000 # number of ReadExReq MSHR miss cycles 269611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 25321000 # number of ReadCleanReq MSHR miss cycles 269711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 6077500 # number of ReadCleanReq MSHR miss cycles 269811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 1080000 # number of ReadCleanReq MSHR miss cycles 269911507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 797000 # number of ReadCleanReq MSHR miss cycles 270011507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_latency::total 33275500 # number of ReadCleanReq MSHR miss cycles 270111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5373500 # number of ReadSharedReq MSHR miss cycles 270211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 638000 # number of ReadSharedReq MSHR miss cycles 270311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 221500 # number of ReadSharedReq MSHR miss cycles 270411507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 175000 # number of ReadSharedReq MSHR miss cycles 270511507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 6408000 # number of ReadSharedReq MSHR miss cycles 270611507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 25321000 # number of demand (read+write) MSHR miss cycles 270711507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 12259500 # number of demand (read+write) MSHR miss cycles 270811507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 6077500 # number of demand (read+write) MSHR miss cycles 270911507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 1547500 # number of demand (read+write) MSHR miss cycles 271011507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu2.inst 1080000 # number of demand (read+write) MSHR miss cycles 271111507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu2.data 1041500 # number of demand (read+write) MSHR miss cycles 271211507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu3.inst 797000 # number of demand (read+write) MSHR miss cycles 271311507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu3.data 992500 # number of demand (read+write) MSHR miss cycles 271411507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::total 49116500 # number of demand (read+write) MSHR miss cycles 271511507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 25321000 # number of overall MSHR miss cycles 271611507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 12259500 # number of overall MSHR miss cycles 271711507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 6077500 # number of overall MSHR miss cycles 271811507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 1547500 # number of overall MSHR miss cycles 271911507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu2.inst 1080000 # number of overall MSHR miss cycles 272011507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu2.data 1041500 # number of overall MSHR miss cycles 272111507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu3.inst 797000 # number of overall MSHR miss cycles 272211507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu3.data 992500 # number of overall MSHR miss cycles 272311507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::total 49116500 # number of overall MSHR miss cycles 272411507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.875000 # mshr miss rate for UpgradeReq accesses 272511507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 272611507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses 272711507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses 272811507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.965909 # mshr miss rate for UpgradeReq accesses 272911507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses 273011507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses 273111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses 273211507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses 273311507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 273411507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for ReadCleanReq accesses 273511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.129032 # mshr miss rate for ReadCleanReq accesses 273611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.019100 # mshr miss rate for ReadCleanReq accesses 273711507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.015692 # mshr miss rate for ReadCleanReq accesses 273811507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::total 0.173408 # mshr miss rate for ReadCleanReq accesses 273911507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.938272 # mshr miss rate for ReadSharedReq accesses 274011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.642857 # mshr miss rate for ReadSharedReq accesses 274111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.214286 # mshr miss rate for ReadSharedReq accesses 274211507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.153846 # mshr miss rate for ReadSharedReq accesses 274311507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.737705 # mshr miss rate for ReadSharedReq accesses 274411507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for demand accesses 274511507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for demand accesses 274611507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.129032 # mshr miss rate for demand accesses 274711507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for demand accesses 274811507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu2.inst 0.019100 # mshr miss rate for demand accesses 274911507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu2.data 0.576923 # mshr miss rate for demand accesses 275011507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu3.inst 0.015692 # mshr miss rate for demand accesses 275111507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for demand accesses 275211507SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.230620 # mshr miss rate for demand accesses 275311507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for overall accesses 275411507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for overall accesses 275511507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.129032 # mshr miss rate for overall accesses 275611507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for overall accesses 275711507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu2.inst 0.019100 # mshr miss rate for overall accesses 275811507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu2.data 0.576923 # mshr miss rate for overall accesses 275911507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu3.inst 0.015692 # mshr miss rate for overall accesses 276011507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for overall accesses 276111507SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.230620 # mshr miss rate for overall accesses 276211507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19976.190476 # average UpgradeReq mshr miss latency 276311507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20000 # average UpgradeReq mshr miss latency 276411507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20000 # average UpgradeReq mshr miss latency 276511507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19900 # average UpgradeReq mshr miss latency 276611507SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 19970.588235 # average UpgradeReq mshr miss latency 276711507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73255.319149 # average ReadExReq mshr miss latency 276811507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69961.538462 # average ReadExReq mshr miss latency 276911507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68333.333333 # average ReadExReq mshr miss latency 277011507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 68125 # average ReadExReq mshr miss latency 277111507SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 72007.633588 # average ReadExReq mshr miss latency 277211507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67343.085106 # average ReadCleanReq mshr miss latency 277311507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66059.782609 # average ReadCleanReq mshr miss latency 277411507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 77142.857143 # average ReadCleanReq mshr miss latency 277511507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72454.545455 # average ReadCleanReq mshr miss latency 277611507SCurtis.Dunham@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::total 67495.943205 # average ReadCleanReq mshr miss latency 277711507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70703.947368 # average ReadSharedReq mshr miss latency 277811507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 70888.888889 # average ReadSharedReq mshr miss latency 277911507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73833.333333 # average ReadSharedReq mshr miss latency 278011507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 87500 # average ReadSharedReq mshr miss latency 278111507SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71200 # average ReadSharedReq mshr miss latency 278211507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67343.085106 # average overall mshr miss latency 278311507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 72114.705882 # average overall mshr miss latency 278411507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66059.782609 # average overall mshr miss latency 278511507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 70340.909091 # average overall mshr miss latency 278611507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu2.inst 77142.857143 # average overall mshr miss latency 278711507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu2.data 69433.333333 # average overall mshr miss latency 278811507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72454.545455 # average overall mshr miss latency 278911507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu3.data 70892.857143 # average overall mshr miss latency 279011507SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 68790.616246 # average overall mshr miss latency 279111507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67343.085106 # average overall mshr miss latency 279211507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 72114.705882 # average overall mshr miss latency 279311507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66059.782609 # average overall mshr miss latency 279411507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 70340.909091 # average overall mshr miss latency 279511507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu2.inst 77142.857143 # average overall mshr miss latency 279611507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu2.data 69433.333333 # average overall mshr miss latency 279711507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72454.545455 # average overall mshr miss latency 279811507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu3.data 70892.857143 # average overall mshr miss latency 279911507SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 68790.616246 # average overall mshr miss latency 280011507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_requests 1042 # Total number of requests made to the snoop filter. 280111507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_requests 329 # Number of requests hitting in the snoop filter with a single holder of the requested data. 280211507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 280311507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 280411507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 280511507SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 280611507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 582 # Transaction distribution 280711507SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 274 # Transaction distribution 280811507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 186 # Transaction distribution 280911507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 131 # Transaction distribution 281011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 582 # Transaction distribution 281111507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1755 # Packet count per connected master and slave (bytes) 281211507SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 1755 # Packet count per connected master and slave (bytes) 281311507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45632 # Cumulative packet size per connected master and slave (bytes) 281411507SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 45632 # Cumulative packet size per connected master and slave (bytes) 281511507SCurtis.Dunham@arm.comsystem.membus.snoops 244 # Total snoops (count) 281611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 1042 # Request fanout histogram 281711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 281811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 281911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 282011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 1042 100.00% 100.00% # Request fanout histogram 282111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 282211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 282311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 282411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 282511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 1042 # Request fanout histogram 282611507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 989502 # Layer occupancy (ticks) 282711507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.8 # Layer utilization (%) 282811507SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 3800250 # Layer occupancy (ticks) 282911507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 3.1 # Layer utilization (%) 283011507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_requests 6343 # Total number of requests made to the snoop filter. 283111507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 1724 # Number of requests hitting in the snoop filter with a single holder of the requested data. 283211507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 3317 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 283311507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 283411507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 283511507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 283611507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 3517 # Transaction distribution 283711507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadRespWithInvalidate 9 # Transaction distribution 283811507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution 283911507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackClean 2134 # Transaction distribution 284011507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution 284111507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution 284211507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution 284311507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExReq 403 # Transaction distribution 284411507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExResp 403 # Transaction distribution 284511507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadCleanReq 2843 # Transaction distribution 284611507SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 684 # Transaction distribution 284711507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1785 # Packet count per connected master and slave (bytes) 284811507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 593 # Packet count per connected master and slave (bytes) 284911507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 2005 # Packet count per connected master and slave (bytes) 285011507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 377 # Packet count per connected master and slave (bytes) 285111507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 2064 # Packet count per connected master and slave (bytes) 285211507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) 285311507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1965 # Packet count per connected master and slave (bytes) 285411507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) 285511507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count::total 9526 # Packet count per connected master and slave (bytes) 285611507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69696 # Cumulative packet size per connected master and slave (bytes) 285711507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes) 285811507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 82688 # Cumulative packet size per connected master and slave (bytes) 285911507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1728 # Cumulative packet size per connected master and slave (bytes) 286011507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 85184 # Cumulative packet size per connected master and slave (bytes) 286111507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) 286211507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 80896 # Cumulative packet size per connected master and slave (bytes) 286311507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) 286411507SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size::total 334720 # Cumulative packet size per connected master and slave (bytes) 286511507SCurtis.Dunham@arm.comsystem.toL2Bus.snoops 1023 # Total snoops (count) 286611507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::samples 4207 # Request fanout histogram 286711507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::mean 1.289042 # Request fanout histogram 286811507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::stdev 1.099056 # Request fanout histogram 286911507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 287011507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::0 1302 30.95% 30.95% # Request fanout histogram 287111507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::1 1193 28.36% 59.31% # Request fanout histogram 287211507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::2 906 21.54% 80.84% # Request fanout histogram 287311507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::3 806 19.16% 100.00% # Request fanout histogram 287411507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 287511507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram 287611507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 287711507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram 287811507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram 287911507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 288011507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 288111507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 288211507SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::total 4207 # Request fanout histogram 288311507SCurtis.Dunham@arm.comsystem.toL2Bus.reqLayer0.occupancy 5321969 # Layer occupancy (ticks) 288411507SCurtis.Dunham@arm.comsystem.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) 288511507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer0.occupancy 1043498 # Layer occupancy (ticks) 288611507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) 288711507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer1.occupancy 522987 # Layer occupancy (ticks) 288811507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 288911507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer2.occupancy 1072493 # Layer occupancy (ticks) 289011507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer2.utilization 0.9 # Layer utilization (%) 289111507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer3.occupancy 443462 # Layer occupancy (ticks) 289211507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) 289311507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer4.occupancy 1103489 # Layer occupancy (ticks) 289411507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer4.utilization 0.9 # Layer utilization (%) 289511507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer5.occupancy 430971 # Layer occupancy (ticks) 289611507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) 289711507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer6.occupancy 1053495 # Layer occupancy (ticks) 289811507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer6.utilization 0.8 # Layer utilization (%) 289911507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer7.occupancy 426466 # Layer occupancy (ticks) 290011507SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) 290111507SCurtis.Dunham@arm.com 290211507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 2903