1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000065 # Number of seconds simulated 4sim_ticks 64758000 # Number of ticks simulated 5final_tick 64758000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 610635 # Simulator instruction rate (inst/s) 8host_op_rate 610062 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6117087273 # Simulator tick rate (ticks/s) 10host_mem_usage 638532 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 6453 # Number of instructions simulated 13sim_ops 6453 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states 17system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory 25system.mem_ctrl.bw_read::cpu.inst 274745977 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 166033540 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 440779518 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 274745977 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 274745977 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 274745977 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 166033540 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 440779518 # Total bandwidth to/from this memory (bytes/s) 33system.mem_ctrl.readReqs 446 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 28544 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 28544 # Total read bytes from the system interface side 41system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.mem_ctrl.perBankRdBursts::0 62 # Per bank write bursts 46system.mem_ctrl.perBankRdBursts::1 26 # Per bank write bursts 47system.mem_ctrl.perBankRdBursts::2 24 # Per bank write bursts 48system.mem_ctrl.perBankRdBursts::3 43 # Per bank write bursts 49system.mem_ctrl.perBankRdBursts::4 40 # Per bank write bursts 50system.mem_ctrl.perBankRdBursts::5 17 # Per bank write bursts 51system.mem_ctrl.perBankRdBursts::6 1 # Per bank write bursts 52system.mem_ctrl.perBankRdBursts::7 3 # Per bank write bursts 53system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts 54system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts 55system.mem_ctrl.perBankRdBursts::10 19 # Per bank write bursts 56system.mem_ctrl.perBankRdBursts::11 23 # Per bank write bursts 57system.mem_ctrl.perBankRdBursts::12 14 # Per bank write bursts 58system.mem_ctrl.perBankRdBursts::13 116 # Per bank write bursts 59system.mem_ctrl.perBankRdBursts::14 45 # Per bank write bursts 60system.mem_ctrl.perBankRdBursts::15 12 # Per bank write bursts 61system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts 62system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts 63system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts 64system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts 65system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts 66system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts 67system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts 68system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts 69system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts 70system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry 79system.mem_ctrl.totGap 64501000 # Total gap between requests 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 446 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) 88system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) 89system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) 90system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) 91system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) 92system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) 93system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) 94system.mem_ctrl.rdQLenPdf::0 446 # What read queue length does an incoming req see 95system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see 96system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see 97system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.mem_ctrl.bytesPerActivate::samples 105 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 264.533333 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::gmean 181.831163 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 249.307389 # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::0-127 27 25.71% 25.71% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-255 40 38.10% 63.81% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::256-383 10 9.52% 73.33% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::384-511 9 8.57% 81.90% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::512-639 7 6.67% 88.57% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::640-767 6 5.71% 94.29% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::768-895 1 0.95% 95.24% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::total 105 # Bytes accessed per row activation 203system.mem_ctrl.totQLat 6134000 # Total ticks spent queuing 204system.mem_ctrl.totMemAccLat 14496500 # Total ticks spent from burst creation until serviced by the DRAM 205system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers 206system.mem_ctrl.avgQLat 13753.36 # Average queueing delay per DRAM burst 207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.mem_ctrl.avgMemAccLat 32503.36 # Average memory access latency per DRAM burst 209system.mem_ctrl.avgRdBW 440.78 # Average DRAM read bandwidth in MiByte/s 210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.mem_ctrl.avgRdBWSys 440.78 # Average system read bandwidth in MiByte/s 212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.mem_ctrl.busUtil 3.44 # Data bus utilization in percentage 215system.mem_ctrl.busUtilRead 3.44 # Data bus utilization in percentage for reads 216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.mem_ctrl.readRowHits 337 # Number of row buffer hits during reads 220system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes 221system.mem_ctrl.readRowHitRate 75.56 # Row buffer hit rate for reads 222system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes 223system.mem_ctrl.avgGap 144621.08 # Average gap between requests 224system.mem_ctrl.pageHitRate 75.56 # Row buffer hit rate, read and write combined 225system.mem_ctrl_0.actEnergy 314160 # Energy for activate commands per rank (pJ) 226system.mem_ctrl_0.preEnergy 163185 # Energy for precharge commands per rank (pJ) 227system.mem_ctrl_0.readEnergy 1542240 # Energy for read commands per rank (pJ) 228system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) 230system.mem_ctrl_0.actBackEnergy 3812160 # Energy for active background per rank (pJ) 231system.mem_ctrl_0.preBackEnergy 131040 # Energy for precharge background per rank (pJ) 232system.mem_ctrl_0.actPowerDownEnergy 22575420 # Energy for active power-down per rank (pJ) 233system.mem_ctrl_0.prePowerDownEnergy 2515200 # Energy for precharge power-down per rank (pJ) 234system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 235system.mem_ctrl_0.totalEnergy 35970525 # Total energy per rank (pJ) 236system.mem_ctrl_0.averagePower 555.454282 # Core power per rank (mW) 237system.mem_ctrl_0.totalIdleTime 55623250 # Total Idle time Per DRAM Rank 238system.mem_ctrl_0.memoryStateTime::IDLE 77000 # Time in different power states 239system.mem_ctrl_0.memoryStateTime::REF 2080000 # Time in different power states 240system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states 241system.mem_ctrl_0.memoryStateTime::PRE_PDN 6549500 # Time in different power states 242system.mem_ctrl_0.memoryStateTime::ACT 6531250 # Time in different power states 243system.mem_ctrl_0.memoryStateTime::ACT_PDN 49520250 # Time in different power states 244system.mem_ctrl_1.actEnergy 464100 # Energy for activate commands per rank (pJ) 245system.mem_ctrl_1.preEnergy 235290 # Energy for precharge commands per rank (pJ) 246system.mem_ctrl_1.readEnergy 1642200 # Energy for read commands per rank (pJ) 247system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 248system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) 249system.mem_ctrl_1.actBackEnergy 4174680 # Energy for active background per rank (pJ) 250system.mem_ctrl_1.preBackEnergy 251520 # Energy for precharge background per rank (pJ) 251system.mem_ctrl_1.actPowerDownEnergy 24338430 # Energy for active power-down per rank (pJ) 252system.mem_ctrl_1.prePowerDownEnergy 604800 # Energy for precharge power-down per rank (pJ) 253system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 254system.mem_ctrl_1.totalEnergy 36628140 # Total energy per rank (pJ) 255system.mem_ctrl_1.averagePower 565.609126 # Core power per rank (mW) 256system.mem_ctrl_1.totalIdleTime 54728750 # Total Idle time Per DRAM Rank 257system.mem_ctrl_1.memoryStateTime::IDLE 283000 # Time in different power states 258system.mem_ctrl_1.memoryStateTime::REF 2080000 # Time in different power states 259system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states 260system.mem_ctrl_1.memoryStateTime::PRE_PDN 1573250 # Time in different power states 261system.mem_ctrl_1.memoryStateTime::ACT 7457000 # Time in different power states 262system.mem_ctrl_1.memoryStateTime::ACT_PDN 53364750 # Time in different power states 263system.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states 264system.cpu.dtb.fetch_hits 0 # ITB hits 265system.cpu.dtb.fetch_misses 0 # ITB misses 266system.cpu.dtb.fetch_acv 0 # ITB acv 267system.cpu.dtb.fetch_accesses 0 # ITB accesses 268system.cpu.dtb.read_hits 1190 # DTB read hits 269system.cpu.dtb.read_misses 7 # DTB read misses 270system.cpu.dtb.read_acv 0 # DTB read access violations 271system.cpu.dtb.read_accesses 1197 # DTB read accesses 272system.cpu.dtb.write_hits 865 # DTB write hits 273system.cpu.dtb.write_misses 3 # DTB write misses 274system.cpu.dtb.write_acv 0 # DTB write access violations 275system.cpu.dtb.write_accesses 868 # DTB write accesses 276system.cpu.dtb.data_hits 2055 # DTB hits 277system.cpu.dtb.data_misses 10 # DTB misses 278system.cpu.dtb.data_acv 0 # DTB access violations 279system.cpu.dtb.data_accesses 2065 # DTB accesses 280system.cpu.itb.fetch_hits 6464 # ITB hits 281system.cpu.itb.fetch_misses 17 # ITB misses 282system.cpu.itb.fetch_acv 0 # ITB acv 283system.cpu.itb.fetch_accesses 6481 # ITB accesses 284system.cpu.itb.read_hits 0 # DTB read hits 285system.cpu.itb.read_misses 0 # DTB read misses 286system.cpu.itb.read_acv 0 # DTB read access violations 287system.cpu.itb.read_accesses 0 # DTB read accesses 288system.cpu.itb.write_hits 0 # DTB write hits 289system.cpu.itb.write_misses 0 # DTB write misses 290system.cpu.itb.write_acv 0 # DTB write access violations 291system.cpu.itb.write_accesses 0 # DTB write accesses 292system.cpu.itb.data_hits 0 # DTB hits 293system.cpu.itb.data_misses 0 # DTB misses 294system.cpu.itb.data_acv 0 # DTB access violations 295system.cpu.itb.data_accesses 0 # DTB accesses 296system.cpu.workload.numSyscalls 17 # Number of system calls 297system.cpu.pwrStateResidencyTicks::ON 64758000 # Cumulative time (in ticks) in various power states 298system.cpu.numCycles 64758 # number of cpu cycles simulated 299system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 300system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 301system.cpu.committedInsts 6453 # Number of instructions committed 302system.cpu.committedOps 6453 # Number of ops (including micro ops) committed 303system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses 304system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 305system.cpu.num_func_calls 251 # number of times a function call or return occured 306system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls 307system.cpu.num_int_insts 6380 # number of integer instructions 308system.cpu.num_fp_insts 10 # number of float instructions 309system.cpu.num_int_register_reads 8392 # number of times the integer registers were read 310system.cpu.num_int_register_writes 4621 # number of times the integer registers were written 311system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 312system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 313system.cpu.num_mem_refs 2065 # number of memory refs 314system.cpu.num_load_insts 1197 # Number of load instructions 315system.cpu.num_store_insts 868 # Number of store instructions 316system.cpu.num_idle_cycles 0 # Number of idle cycles 317system.cpu.num_busy_cycles 64758 # Number of busy cycles 318system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 319system.cpu.idle_fraction 0 # Percentage of idle cycles 320system.cpu.Branches 1060 # Number of branches fetched 321system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction 322system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction 323system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction 324system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction 325system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction 326system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction 327system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction 328system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction 329system.cpu.op_class::FloatMultAcc 0 0.00% 68.05% # Class of executed instruction 330system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction 331system.cpu.op_class::FloatMisc 0 0.00% 68.05% # Class of executed instruction 332system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction 333system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction 334system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction 335system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction 336system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction 337system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction 338system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction 339system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction 340system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction 341system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction 342system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction 343system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction 344system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction 345system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction 346system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction 347system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction 348system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction 349system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction 350system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction 351system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction 352system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction 353system.cpu.op_class::MemRead 1196 18.51% 86.55% # Class of executed instruction 354system.cpu.op_class::MemWrite 861 13.32% 99.88% # Class of executed instruction 355system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction 356system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction 357system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 358system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 359system.cpu.op_class::total 6463 # Class of executed instruction 360system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states 361system.cpu.dcache.tags.replacements 0 # number of replacements 362system.cpu.dcache.tags.tagsinuse 104.399751 # Cycle average of tags in use 363system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. 364system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 365system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. 366system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 367system.cpu.dcache.tags.occ_blocks::cpu.data 104.399751 # Average occupied blocks per requestor 368system.cpu.dcache.tags.occ_percent::cpu.data 0.101953 # Average percentage of cache occupancy 369system.cpu.dcache.tags.occ_percent::total 0.101953 # Average percentage of cache occupancy 370system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 371system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 372system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 373system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id 374system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses 375system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses 376system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states 377system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits 378system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits 379system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 380system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 381system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits 382system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits 383system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits 384system.cpu.dcache.overall_hits::total 1887 # number of overall hits 385system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 386system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 387system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 388system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 389system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 390system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 391system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 392system.cpu.dcache.overall_misses::total 168 # number of overall misses 393system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261000 # number of ReadReq miss cycles 394system.cpu.dcache.ReadReq_miss_latency::total 10261000 # number of ReadReq miss cycles 395system.cpu.dcache.WriteReq_miss_latency::cpu.data 7802000 # number of WriteReq miss cycles 396system.cpu.dcache.WriteReq_miss_latency::total 7802000 # number of WriteReq miss cycles 397system.cpu.dcache.demand_miss_latency::cpu.data 18063000 # number of demand (read+write) miss cycles 398system.cpu.dcache.demand_miss_latency::total 18063000 # number of demand (read+write) miss cycles 399system.cpu.dcache.overall_miss_latency::cpu.data 18063000 # number of overall miss cycles 400system.cpu.dcache.overall_miss_latency::total 18063000 # number of overall miss cycles 401system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) 402system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) 403system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 404system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 405system.cpu.dcache.demand_accesses::cpu.data 2055 # number of demand (read+write) accesses 406system.cpu.dcache.demand_accesses::total 2055 # number of demand (read+write) accesses 407system.cpu.dcache.overall_accesses::cpu.data 2055 # number of overall (read+write) accesses 408system.cpu.dcache.overall_accesses::total 2055 # number of overall (read+write) accesses 409system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079832 # miss rate for ReadReq accesses 410system.cpu.dcache.ReadReq_miss_rate::total 0.079832 # miss rate for ReadReq accesses 411system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 412system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 413system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 # miss rate for demand accesses 414system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses 415system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses 416system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses 417system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108010.526316 # average ReadReq miss latency 418system.cpu.dcache.ReadReq_avg_miss_latency::total 108010.526316 # average ReadReq miss latency 419system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106876.712329 # average WriteReq miss latency 420system.cpu.dcache.WriteReq_avg_miss_latency::total 106876.712329 # average WriteReq miss latency 421system.cpu.dcache.demand_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency 422system.cpu.dcache.demand_avg_miss_latency::total 107517.857143 # average overall miss latency 423system.cpu.dcache.overall_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency 424system.cpu.dcache.overall_avg_miss_latency::total 107517.857143 # average overall miss latency 425system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 426system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 427system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 428system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 429system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 430system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 431system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 432system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 433system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 434system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 435system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 436system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 437system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 438system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses 439system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10071000 # number of ReadReq MSHR miss cycles 440system.cpu.dcache.ReadReq_mshr_miss_latency::total 10071000 # number of ReadReq MSHR miss cycles 441system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7656000 # number of WriteReq MSHR miss cycles 442system.cpu.dcache.WriteReq_mshr_miss_latency::total 7656000 # number of WriteReq MSHR miss cycles 443system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17727000 # number of demand (read+write) MSHR miss cycles 444system.cpu.dcache.demand_mshr_miss_latency::total 17727000 # number of demand (read+write) MSHR miss cycles 445system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17727000 # number of overall MSHR miss cycles 446system.cpu.dcache.overall_mshr_miss_latency::total 17727000 # number of overall MSHR miss cycles 447system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses 448system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses 449system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 450system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 451system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses 452system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses 453system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses 454system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses 455system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106010.526316 # average ReadReq mshr miss latency 456system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106010.526316 # average ReadReq mshr miss latency 457system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104876.712329 # average WriteReq mshr miss latency 458system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104876.712329 # average WriteReq mshr miss latency 459system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency 460system.cpu.dcache.demand_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency 461system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency 462system.cpu.dcache.overall_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency 463system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states 464system.cpu.icache.tags.replacements 62 # number of replacements 465system.cpu.icache.tags.tagsinuse 113.445692 # Cycle average of tags in use 466system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. 467system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. 468system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. 469system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 470system.cpu.icache.tags.occ_blocks::cpu.inst 113.445692 # Average occupied blocks per requestor 471system.cpu.icache.tags.occ_percent::cpu.inst 0.443147 # Average percentage of cache occupancy 472system.cpu.icache.tags.occ_percent::total 0.443147 # Average percentage of cache occupancy 473system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id 474system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 475system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 476system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id 477system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses 478system.cpu.icache.tags.data_accesses 13209 # Number of data accesses 479system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states 480system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits 481system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits 482system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits 483system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits 484system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits 485system.cpu.icache.overall_hits::total 6183 # number of overall hits 486system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses 487system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses 488system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses 489system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses 490system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses 491system.cpu.icache.overall_misses::total 281 # number of overall misses 492system.cpu.icache.ReadReq_miss_latency::cpu.inst 30557000 # number of ReadReq miss cycles 493system.cpu.icache.ReadReq_miss_latency::total 30557000 # number of ReadReq miss cycles 494system.cpu.icache.demand_miss_latency::cpu.inst 30557000 # number of demand (read+write) miss cycles 495system.cpu.icache.demand_miss_latency::total 30557000 # number of demand (read+write) miss cycles 496system.cpu.icache.overall_miss_latency::cpu.inst 30557000 # number of overall miss cycles 497system.cpu.icache.overall_miss_latency::total 30557000 # number of overall miss cycles 498system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) 499system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) 500system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses 501system.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses 502system.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses 503system.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses 504system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses 505system.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses 506system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses 507system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses 508system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses 509system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses 510system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108743.772242 # average ReadReq miss latency 511system.cpu.icache.ReadReq_avg_miss_latency::total 108743.772242 # average ReadReq miss latency 512system.cpu.icache.demand_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency 513system.cpu.icache.demand_avg_miss_latency::total 108743.772242 # average overall miss latency 514system.cpu.icache.overall_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency 515system.cpu.icache.overall_avg_miss_latency::total 108743.772242 # average overall miss latency 516system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 517system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 518system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 519system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 520system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 521system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 522system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses 523system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses 524system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses 525system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses 526system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses 527system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses 528system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29995000 # number of ReadReq MSHR miss cycles 529system.cpu.icache.ReadReq_mshr_miss_latency::total 29995000 # number of ReadReq MSHR miss cycles 530system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29995000 # number of demand (read+write) MSHR miss cycles 531system.cpu.icache.demand_mshr_miss_latency::total 29995000 # number of demand (read+write) MSHR miss cycles 532system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29995000 # number of overall MSHR miss cycles 533system.cpu.icache.overall_mshr_miss_latency::total 29995000 # number of overall MSHR miss cycles 534system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses 535system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses 536system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses 537system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses 538system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses 539system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses 540system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106743.772242 # average ReadReq mshr miss latency 541system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106743.772242 # average ReadReq mshr miss latency 542system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency 543system.cpu.icache.demand_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency 544system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency 545system.cpu.icache.overall_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency 546system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. 547system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. 548system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 549system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 550system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 551system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 552system.l2bus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states 553system.l2bus.trans_dist::ReadResp 376 # Transaction distribution 554system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution 555system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution 556system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution 557system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution 558system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) 559system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 560system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) 561system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 17984 # Cumulative packet size per connected master and slave (bytes) 562system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) 563system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes) 564system.l2bus.snoops 0 # Total snoops (count) 565system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) 566system.l2bus.snoop_fanout::samples 449 # Request fanout histogram 567system.l2bus.snoop_fanout::mean 0.002227 # Request fanout histogram 568system.l2bus.snoop_fanout::stdev 0.047193 # Request fanout histogram 569system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 570system.l2bus.snoop_fanout::0 448 99.78% 99.78% # Request fanout histogram 571system.l2bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram 572system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 573system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 574system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 575system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 576system.l2bus.snoop_fanout::total 449 # Request fanout histogram 577system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) 578system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 579system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) 580system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) 581system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) 582system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) 583system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states 584system.l2cache.tags.replacements 0 # number of replacements 585system.l2cache.tags.tagsinuse 232.606847 # Cycle average of tags in use 586system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. 587system.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. 588system.l2cache.tags.avg_refs 0.145740 # Average number of references to valid blocks. 589system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 590system.l2cache.tags.occ_blocks::cpu.inst 128.152617 # Average occupied blocks per requestor 591system.l2cache.tags.occ_blocks::cpu.data 104.454231 # Average occupied blocks per requestor 592system.l2cache.tags.occ_percent::cpu.inst 0.031287 # Average percentage of cache occupancy 593system.l2cache.tags.occ_percent::cpu.data 0.025502 # Average percentage of cache occupancy 594system.l2cache.tags.occ_percent::total 0.056789 # Average percentage of cache occupancy 595system.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id 596system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 597system.l2cache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id 598system.l2cache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id 599system.l2cache.tags.tag_accesses 4534 # Number of tag accesses 600system.l2cache.tags.data_accesses 4534 # Number of data accesses 601system.l2cache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states 602system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits 603system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 604system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 605system.l2cache.demand_hits::total 3 # number of demand (read+write) hits 606system.l2cache.overall_hits::cpu.inst 3 # number of overall hits 607system.l2cache.overall_hits::total 3 # number of overall hits 608system.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 609system.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 610system.l2cache.ReadSharedReq_misses::cpu.inst 278 # number of ReadSharedReq misses 611system.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses 612system.l2cache.ReadSharedReq_misses::total 373 # number of ReadSharedReq misses 613system.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 614system.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 615system.l2cache.demand_misses::total 446 # number of demand (read+write) misses 616system.l2cache.overall_misses::cpu.inst 278 # number of overall misses 617system.l2cache.overall_misses::cpu.data 168 # number of overall misses 618system.l2cache.overall_misses::total 446 # number of overall misses 619system.l2cache.ReadExReq_miss_latency::cpu.data 7437000 # number of ReadExReq miss cycles 620system.l2cache.ReadExReq_miss_latency::total 7437000 # number of ReadExReq miss cycles 621system.l2cache.ReadSharedReq_miss_latency::cpu.inst 29087000 # number of ReadSharedReq miss cycles 622system.l2cache.ReadSharedReq_miss_latency::cpu.data 9786000 # number of ReadSharedReq miss cycles 623system.l2cache.ReadSharedReq_miss_latency::total 38873000 # number of ReadSharedReq miss cycles 624system.l2cache.demand_miss_latency::cpu.inst 29087000 # number of demand (read+write) miss cycles 625system.l2cache.demand_miss_latency::cpu.data 17223000 # number of demand (read+write) miss cycles 626system.l2cache.demand_miss_latency::total 46310000 # number of demand (read+write) miss cycles 627system.l2cache.overall_miss_latency::cpu.inst 29087000 # number of overall miss cycles 628system.l2cache.overall_miss_latency::cpu.data 17223000 # number of overall miss cycles 629system.l2cache.overall_miss_latency::total 46310000 # number of overall miss cycles 630system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 631system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 632system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) 633system.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) 634system.l2cache.ReadSharedReq_accesses::total 376 # number of ReadSharedReq accesses(hits+misses) 635system.l2cache.demand_accesses::cpu.inst 281 # number of demand (read+write) accesses 636system.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 637system.l2cache.demand_accesses::total 449 # number of demand (read+write) accesses 638system.l2cache.overall_accesses::cpu.inst 281 # number of overall (read+write) accesses 639system.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 640system.l2cache.overall_accesses::total 449 # number of overall (read+write) accesses 641system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 642system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 643system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.989324 # miss rate for ReadSharedReq accesses 644system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 645system.l2cache.ReadSharedReq_miss_rate::total 0.992021 # miss rate for ReadSharedReq accesses 646system.l2cache.demand_miss_rate::cpu.inst 0.989324 # miss rate for demand accesses 647system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 648system.l2cache.demand_miss_rate::total 0.993318 # miss rate for demand accesses 649system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses 650system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 651system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses 652system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101876.712329 # average ReadExReq miss latency 653system.l2cache.ReadExReq_avg_miss_latency::total 101876.712329 # average ReadExReq miss latency 654system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104629.496403 # average ReadSharedReq miss latency 655system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103010.526316 # average ReadSharedReq miss latency 656system.l2cache.ReadSharedReq_avg_miss_latency::total 104217.158177 # average ReadSharedReq miss latency 657system.l2cache.demand_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency 658system.l2cache.demand_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency 659system.l2cache.demand_avg_miss_latency::total 103834.080717 # average overall miss latency 660system.l2cache.overall_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency 661system.l2cache.overall_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency 662system.l2cache.overall_avg_miss_latency::total 103834.080717 # average overall miss latency 663system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 664system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 665system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 666system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 667system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 668system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 669system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 670system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 671system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses 672system.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses 673system.l2cache.ReadSharedReq_mshr_misses::total 373 # number of ReadSharedReq MSHR misses 674system.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 675system.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 676system.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 677system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 678system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 679system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 680system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5977000 # number of ReadExReq MSHR miss cycles 681system.l2cache.ReadExReq_mshr_miss_latency::total 5977000 # number of ReadExReq MSHR miss cycles 682system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 23527000 # number of ReadSharedReq MSHR miss cycles 683system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7886000 # number of ReadSharedReq MSHR miss cycles 684system.l2cache.ReadSharedReq_mshr_miss_latency::total 31413000 # number of ReadSharedReq MSHR miss cycles 685system.l2cache.demand_mshr_miss_latency::cpu.inst 23527000 # number of demand (read+write) MSHR miss cycles 686system.l2cache.demand_mshr_miss_latency::cpu.data 13863000 # number of demand (read+write) MSHR miss cycles 687system.l2cache.demand_mshr_miss_latency::total 37390000 # number of demand (read+write) MSHR miss cycles 688system.l2cache.overall_mshr_miss_latency::cpu.inst 23527000 # number of overall MSHR miss cycles 689system.l2cache.overall_mshr_miss_latency::cpu.data 13863000 # number of overall MSHR miss cycles 690system.l2cache.overall_mshr_miss_latency::total 37390000 # number of overall MSHR miss cycles 691system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 692system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 693system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses 694system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 695system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.992021 # mshr miss rate for ReadSharedReq accesses 696system.l2cache.demand_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for demand accesses 697system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 698system.l2cache.demand_mshr_miss_rate::total 0.993318 # mshr miss rate for demand accesses 699system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses 700system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 701system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses 702system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81876.712329 # average ReadExReq mshr miss latency 703system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81876.712329 # average ReadExReq mshr miss latency 704system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84629.496403 # average ReadSharedReq mshr miss latency 705system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83010.526316 # average ReadSharedReq mshr miss latency 706system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84217.158177 # average ReadSharedReq mshr miss latency 707system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency 708system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency 709system.l2cache.demand_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency 710system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency 711system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency 712system.l2cache.overall_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency 713system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. 714system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 715system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 716system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 717system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 718system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 719system.membus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states 720system.membus.trans_dist::ReadResp 373 # Transaction distribution 721system.membus.trans_dist::ReadExReq 73 # Transaction distribution 722system.membus.trans_dist::ReadExResp 73 # Transaction distribution 723system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 724system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 892 # Packet count per connected master and slave (bytes) 725system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 726system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 28544 # Cumulative packet size per connected master and slave (bytes) 727system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) 728system.membus.snoops 0 # Total snoops (count) 729system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 730system.membus.snoop_fanout::samples 446 # Request fanout histogram 731system.membus.snoop_fanout::mean 0 # Request fanout histogram 732system.membus.snoop_fanout::stdev 0 # Request fanout histogram 733system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 734system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram 735system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 736system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 737system.membus.snoop_fanout::min_value 0 # Request fanout histogram 738system.membus.snoop_fanout::max_value 0 # Request fanout histogram 739system.membus.snoop_fanout::total 446 # Request fanout histogram 740system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) 741system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) 742system.membus.respLayer0.occupancy 2377500 # Layer occupancy (ticks) 743system.membus.respLayer0.utilization 3.7 # Layer utilization (%) 744 745---------- End Simulation Statistics ---------- 746