config.ini revision 11731:c473ca7cc650
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=TimingSimpleCPU 58children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload 59branchPred=Null 60checker=Null 61clk_domain=system.cpu_clk_domain 62cpu_id=0 63default_p_state=UNDEFINED 64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dtb=system.cpu.dtb 68eventq_index=0 69function_trace=false 70function_trace_start=0 71interrupts=system.cpu.interrupts 72isa=system.cpu.isa 73itb=system.cpu.itb 74max_insts_all_threads=0 75max_insts_any_thread=0 76max_loads_all_threads=0 77max_loads_any_thread=0 78numThreads=1 79p_state_clk_gate_bins=20 80p_state_clk_gate_max=1000000000000 81p_state_clk_gate_min=1000 82power_model=Null 83profile=0 84progress_interval=0 85simpoint_start_insts= 86socket_id=0 87switched_out=false 88system=system 89tracer=system.cpu.tracer 90workload=system.cpu.workload 91dcache_port=system.cpu.dcache.cpu_side 92icache_port=system.cpu.icache.cpu_side 93 94[system.cpu.dcache] 95type=Cache 96children=tags 97addr_ranges=0:18446744073709551615:0:0:0:0 98assoc=2 99clk_domain=system.cpu_clk_domain 100clusivity=mostly_incl 101data_latency=2 102default_p_state=UNDEFINED 103demand_mshr_reserve=1 104eventq_index=0 105is_read_only=false 106max_miss_count=0 107mshrs=4 108p_state_clk_gate_bins=20 109p_state_clk_gate_max=1000000000000 110p_state_clk_gate_min=1000 111power_model=Null 112prefetch_on_access=false 113prefetcher=Null 114response_latency=2 115sequential_access=false 116size=262144 117system=system 118tag_latency=2 119tags=system.cpu.dcache.tags 120tgts_per_mshr=20 121write_buffers=8 122writeback_clean=false 123cpu_side=system.cpu.dcache_port 124mem_side=system.cpu.toL2Bus.slave[1] 125 126[system.cpu.dcache.tags] 127type=LRU 128assoc=2 129block_size=64 130clk_domain=system.cpu_clk_domain 131data_latency=2 132default_p_state=UNDEFINED 133eventq_index=0 134p_state_clk_gate_bins=20 135p_state_clk_gate_max=1000000000000 136p_state_clk_gate_min=1000 137power_model=Null 138sequential_access=false 139size=262144 140tag_latency=2 141 142[system.cpu.dtb] 143type=RiscvTLB 144eventq_index=0 145size=64 146 147[system.cpu.icache] 148type=Cache 149children=tags 150addr_ranges=0:18446744073709551615:0:0:0:0 151assoc=2 152clk_domain=system.cpu_clk_domain 153clusivity=mostly_incl 154data_latency=2 155default_p_state=UNDEFINED 156demand_mshr_reserve=1 157eventq_index=0 158is_read_only=true 159max_miss_count=0 160mshrs=4 161p_state_clk_gate_bins=20 162p_state_clk_gate_max=1000000000000 163p_state_clk_gate_min=1000 164power_model=Null 165prefetch_on_access=false 166prefetcher=Null 167response_latency=2 168sequential_access=false 169size=131072 170system=system 171tag_latency=2 172tags=system.cpu.icache.tags 173tgts_per_mshr=20 174write_buffers=8 175writeback_clean=true 176cpu_side=system.cpu.icache_port 177mem_side=system.cpu.toL2Bus.slave[0] 178 179[system.cpu.icache.tags] 180type=LRU 181assoc=2 182block_size=64 183clk_domain=system.cpu_clk_domain 184data_latency=2 185default_p_state=UNDEFINED 186eventq_index=0 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191sequential_access=false 192size=131072 193tag_latency=2 194 195[system.cpu.interrupts] 196type=RiscvInterrupts 197eventq_index=0 198 199[system.cpu.isa] 200type=RiscvISA 201eventq_index=0 202 203[system.cpu.itb] 204type=RiscvTLB 205eventq_index=0 206size=64 207 208[system.cpu.l2cache] 209type=Cache 210children=tags 211addr_ranges=0:18446744073709551615:0:0:0:0 212assoc=8 213clk_domain=system.cpu_clk_domain 214clusivity=mostly_incl 215data_latency=20 216default_p_state=UNDEFINED 217demand_mshr_reserve=1 218eventq_index=0 219is_read_only=false 220max_miss_count=0 221mshrs=20 222p_state_clk_gate_bins=20 223p_state_clk_gate_max=1000000000000 224p_state_clk_gate_min=1000 225power_model=Null 226prefetch_on_access=false 227prefetcher=Null 228response_latency=20 229sequential_access=false 230size=2097152 231system=system 232tag_latency=20 233tags=system.cpu.l2cache.tags 234tgts_per_mshr=12 235write_buffers=8 236writeback_clean=false 237cpu_side=system.cpu.toL2Bus.master[0] 238mem_side=system.membus.slave[1] 239 240[system.cpu.l2cache.tags] 241type=LRU 242assoc=8 243block_size=64 244clk_domain=system.cpu_clk_domain 245data_latency=20 246default_p_state=UNDEFINED 247eventq_index=0 248p_state_clk_gate_bins=20 249p_state_clk_gate_max=1000000000000 250p_state_clk_gate_min=1000 251power_model=Null 252sequential_access=false 253size=2097152 254tag_latency=20 255 256[system.cpu.toL2Bus] 257type=CoherentXBar 258children=snoop_filter 259clk_domain=system.cpu_clk_domain 260default_p_state=UNDEFINED 261eventq_index=0 262forward_latency=0 263frontend_latency=1 264p_state_clk_gate_bins=20 265p_state_clk_gate_max=1000000000000 266p_state_clk_gate_min=1000 267point_of_coherency=false 268power_model=Null 269response_latency=1 270snoop_filter=system.cpu.toL2Bus.snoop_filter 271snoop_response_latency=1 272system=system 273use_default_range=false 274width=32 275master=system.cpu.l2cache.cpu_side 276slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 277 278[system.cpu.toL2Bus.snoop_filter] 279type=SnoopFilter 280eventq_index=0 281lookup_latency=0 282max_capacity=8388608 283system=system 284 285[system.cpu.tracer] 286type=ExeTracer 287eventq_index=0 288 289[system.cpu.workload] 290type=LiveProcess 291cmd=insttest 292cwd= 293drivers= 294egid=100 295env= 296errout=cerr 297euid=100 298eventq_index=0 299executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest 300gid=100 301input=cin 302kvmInSE=false 303max_stack_size=67108864 304output=cout 305pid=100 306ppid=99 307simpoint=0 308system=system 309uid=100 310useArchPT=false 311 312[system.cpu_clk_domain] 313type=SrcClockDomain 314clock=500 315domain_id=-1 316eventq_index=0 317init_perf_level=0 318voltage_domain=system.voltage_domain 319 320[system.dvfs_handler] 321type=DVFSHandler 322domains= 323enable=false 324eventq_index=0 325sys_clk_domain=system.clk_domain 326transition_latency=100000000 327 328[system.membus] 329type=CoherentXBar 330children=snoop_filter 331clk_domain=system.clk_domain 332default_p_state=UNDEFINED 333eventq_index=0 334forward_latency=4 335frontend_latency=3 336p_state_clk_gate_bins=20 337p_state_clk_gate_max=1000000000000 338p_state_clk_gate_min=1000 339point_of_coherency=true 340power_model=Null 341response_latency=2 342snoop_filter=system.membus.snoop_filter 343snoop_response_latency=4 344system=system 345use_default_range=false 346width=16 347master=system.physmem.port 348slave=system.system_port system.cpu.l2cache.mem_side 349 350[system.membus.snoop_filter] 351type=SnoopFilter 352eventq_index=0 353lookup_latency=1 354max_capacity=8388608 355system=system 356 357[system.physmem] 358type=SimpleMemory 359bandwidth=73.000000 360clk_domain=system.clk_domain 361conf_table_reported=true 362default_p_state=UNDEFINED 363eventq_index=0 364in_addr_map=true 365kvm_map=true 366latency=30000 367latency_var=0 368null=false 369p_state_clk_gate_bins=20 370p_state_clk_gate_max=1000000000000 371p_state_clk_gate_min=1000 372power_model=Null 373range=0:134217727:0:0:0:0 374port=system.membus.master[0] 375 376[system.voltage_domain] 377type=VoltageDomain 378eventq_index=0 379voltage=1.000000 380 381