1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=TimingSimpleCPU 58children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload 59branchPred=Null 60checker=Null 61clk_domain=system.cpu_clk_domain 62cpu_id=0 63default_p_state=UNDEFINED 64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dtb=system.cpu.dtb 68eventq_index=0 69function_trace=false 70function_trace_start=0 71interrupts=system.cpu.interrupts 72isa=system.cpu.isa 73itb=system.cpu.itb 74max_insts_all_threads=0 75max_insts_any_thread=0 76max_loads_all_threads=0 77max_loads_any_thread=0 78numThreads=1 79p_state_clk_gate_bins=20 80p_state_clk_gate_max=1000000000000 81p_state_clk_gate_min=1000 82power_model=Null 83profile=0 84progress_interval=0 85simpoint_start_insts= 86socket_id=0 87switched_out=false 88syscallRetryLatency=10000 89system=system 90tracer=system.cpu.tracer 91wait_for_remote_gdb=false 92workload=system.cpu.workload 93dcache_port=system.cpu.dcache.cpu_side 94icache_port=system.cpu.icache.cpu_side 95 96[system.cpu.dcache] 97type=Cache 98children=tags 99addr_ranges=0:18446744073709551615:0:0:0:0 100assoc=2 101clk_domain=system.cpu_clk_domain 102clusivity=mostly_incl 103data_latency=2 104default_p_state=UNDEFINED 105demand_mshr_reserve=1 106eventq_index=0 107is_read_only=false 108max_miss_count=0 109mshrs=4 110p_state_clk_gate_bins=20 111p_state_clk_gate_max=1000000000000 112p_state_clk_gate_min=1000 113power_model=Null 114prefetch_on_access=false 115prefetcher=Null 116response_latency=2 117sequential_access=false 118size=262144 119system=system 120tag_latency=2 121tags=system.cpu.dcache.tags 122tgts_per_mshr=20 123write_buffers=8 124writeback_clean=false 125cpu_side=system.cpu.dcache_port 126mem_side=system.cpu.toL2Bus.slave[1] 127 128[system.cpu.dcache.tags] 129type=LRU 130assoc=2 131block_size=64 132clk_domain=system.cpu_clk_domain 133data_latency=2 134default_p_state=UNDEFINED 135eventq_index=0 136p_state_clk_gate_bins=20 137p_state_clk_gate_max=1000000000000 138p_state_clk_gate_min=1000 139power_model=Null 140sequential_access=false 141size=262144 142tag_latency=2 143 144[system.cpu.dtb] 145type=RiscvTLB 146eventq_index=0 147size=64 148 149[system.cpu.icache] 150type=Cache 151children=tags 152addr_ranges=0:18446744073709551615:0:0:0:0 153assoc=2 154clk_domain=system.cpu_clk_domain 155clusivity=mostly_incl 156data_latency=2 157default_p_state=UNDEFINED 158demand_mshr_reserve=1 159eventq_index=0 160is_read_only=true 161max_miss_count=0 162mshrs=4 163p_state_clk_gate_bins=20 164p_state_clk_gate_max=1000000000000 165p_state_clk_gate_min=1000 166power_model=Null 167prefetch_on_access=false 168prefetcher=Null 169response_latency=2 170sequential_access=false 171size=131072 172system=system 173tag_latency=2 174tags=system.cpu.icache.tags 175tgts_per_mshr=20 176write_buffers=8 177writeback_clean=true 178cpu_side=system.cpu.icache_port 179mem_side=system.cpu.toL2Bus.slave[0] 180 181[system.cpu.icache.tags] 182type=LRU 183assoc=2 184block_size=64 185clk_domain=system.cpu_clk_domain 186data_latency=2 187default_p_state=UNDEFINED 188eventq_index=0 189p_state_clk_gate_bins=20 190p_state_clk_gate_max=1000000000000 191p_state_clk_gate_min=1000 192power_model=Null 193sequential_access=false 194size=131072 195tag_latency=2 196 197[system.cpu.interrupts] 198type=RiscvInterrupts 199eventq_index=0 200 201[system.cpu.isa] 202type=RiscvISA 203eventq_index=0 204 205[system.cpu.itb] 206type=RiscvTLB 207eventq_index=0 208size=64 209 210[system.cpu.l2cache] 211type=Cache 212children=tags 213addr_ranges=0:18446744073709551615:0:0:0:0 214assoc=8 215clk_domain=system.cpu_clk_domain 216clusivity=mostly_incl 217data_latency=20 218default_p_state=UNDEFINED 219demand_mshr_reserve=1 220eventq_index=0 221is_read_only=false 222max_miss_count=0 223mshrs=20 224p_state_clk_gate_bins=20 225p_state_clk_gate_max=1000000000000 226p_state_clk_gate_min=1000 227power_model=Null 228prefetch_on_access=false 229prefetcher=Null 230response_latency=20 231sequential_access=false 232size=2097152 233system=system 234tag_latency=20 235tags=system.cpu.l2cache.tags 236tgts_per_mshr=12 237write_buffers=8 238writeback_clean=false 239cpu_side=system.cpu.toL2Bus.master[0] 240mem_side=system.membus.slave[1] 241 242[system.cpu.l2cache.tags] 243type=LRU 244assoc=8 245block_size=64 246clk_domain=system.cpu_clk_domain 247data_latency=20 248default_p_state=UNDEFINED 249eventq_index=0 250p_state_clk_gate_bins=20 251p_state_clk_gate_max=1000000000000 252p_state_clk_gate_min=1000 253power_model=Null 254sequential_access=false 255size=2097152 256tag_latency=20 257 258[system.cpu.toL2Bus] 259type=CoherentXBar 260children=snoop_filter 261clk_domain=system.cpu_clk_domain 262default_p_state=UNDEFINED 263eventq_index=0 264forward_latency=0 265frontend_latency=1 266p_state_clk_gate_bins=20 267p_state_clk_gate_max=1000000000000 268p_state_clk_gate_min=1000 269point_of_coherency=false 270power_model=Null 271response_latency=1 272snoop_filter=system.cpu.toL2Bus.snoop_filter 273snoop_response_latency=1 274system=system 275use_default_range=false 276width=32 277master=system.cpu.l2cache.cpu_side 278slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 279 280[system.cpu.toL2Bus.snoop_filter] 281type=SnoopFilter 282eventq_index=0 283lookup_latency=0 284max_capacity=8388608 285system=system 286 287[system.cpu.tracer] 288type=ExeTracer 289eventq_index=0 290 291[system.cpu.workload] 292type=Process 293cmd=insttest 294cwd= 295drivers= 296egid=100 297env= 298errout=cerr 299euid=100 300eventq_index=0 301executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest 302gid=100 303input=cin 304kvmInSE=false 305maxStackSize=67108864 306output=cout 307pgid=100 308pid=100 309ppid=0 310simpoint=0 311system=system 312uid=100 313useArchPT=false 314 315[system.cpu_clk_domain] 316type=SrcClockDomain 317clock=500 318domain_id=-1 319eventq_index=0 320init_perf_level=0 321voltage_domain=system.voltage_domain 322 323[system.dvfs_handler] 324type=DVFSHandler 325domains= 326enable=false 327eventq_index=0 328sys_clk_domain=system.clk_domain 329transition_latency=100000000 330 331[system.membus] 332type=CoherentXBar 333children=snoop_filter 334clk_domain=system.clk_domain 335default_p_state=UNDEFINED 336eventq_index=0 337forward_latency=4 338frontend_latency=3 339p_state_clk_gate_bins=20 340p_state_clk_gate_max=1000000000000 341p_state_clk_gate_min=1000 342point_of_coherency=true 343power_model=Null 344response_latency=2 345snoop_filter=system.membus.snoop_filter 346snoop_response_latency=4 347system=system 348use_default_range=false 349width=16 350master=system.physmem.port 351slave=system.system_port system.cpu.l2cache.mem_side 352 353[system.membus.snoop_filter] 354type=SnoopFilter 355eventq_index=0 356lookup_latency=1 357max_capacity=8388608 358system=system 359 360[system.physmem] 361type=SimpleMemory 362bandwidth=73.000000 363clk_domain=system.clk_domain 364conf_table_reported=true 365default_p_state=UNDEFINED 366eventq_index=0 367in_addr_map=true 368kvm_map=true 369latency=30000 370latency_var=0 371null=false 372p_state_clk_gate_bins=20 373p_state_clk_gate_max=1000000000000 374p_state_clk_gate_min=1000 375power_model=Null 376range=0:134217727:0:0:0:0 377port=system.membus.master[0] 378 379[system.voltage_domain] 380type=VoltageDomain 381eventq_index=0 382voltage=1.000000 383 384