stats.txt revision 9150
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000015 # Number of seconds simulated 4sim_ticks 14993500 # Number of ticks simulated 5final_tick 14993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 32330 # Simulator instruction rate (inst/s) 8host_op_rate 32329 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38030689 # Simulator tick rate (ticks/s) 10host_mem_usage 224252 # Number of bytes of host memory used 11host_seconds 0.39 # Real time elapsed on the host 12sim_insts 12745 # Number of instructions simulated 13sim_ops 12745 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 39872 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 22464 # Number of bytes read from this memory 16system.physmem.bytes_read::total 62336 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 39872 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 39872 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 623 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 351 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 974 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2659285690 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 1498249241 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 4157534932 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2659285690 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2659285690 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2659285690 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 1498249241 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 4157534932 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.dtb.fetch_hits 0 # ITB hits 31system.cpu.dtb.fetch_misses 0 # ITB misses 32system.cpu.dtb.fetch_acv 0 # ITB acv 33system.cpu.dtb.fetch_accesses 0 # ITB accesses 34system.cpu.dtb.read_hits 4043 # DTB read hits 35system.cpu.dtb.read_misses 104 # DTB read misses 36system.cpu.dtb.read_acv 0 # DTB read access violations 37system.cpu.dtb.read_accesses 4147 # DTB read accesses 38system.cpu.dtb.write_hits 2093 # DTB write hits 39system.cpu.dtb.write_misses 65 # DTB write misses 40system.cpu.dtb.write_acv 0 # DTB write access violations 41system.cpu.dtb.write_accesses 2158 # DTB write accesses 42system.cpu.dtb.data_hits 6136 # DTB hits 43system.cpu.dtb.data_misses 169 # DTB misses 44system.cpu.dtb.data_acv 0 # DTB access violations 45system.cpu.dtb.data_accesses 6305 # DTB accesses 46system.cpu.itb.fetch_hits 5063 # ITB hits 47system.cpu.itb.fetch_misses 68 # ITB misses 48system.cpu.itb.fetch_acv 0 # ITB acv 49system.cpu.itb.fetch_accesses 5131 # ITB accesses 50system.cpu.itb.read_hits 0 # DTB read hits 51system.cpu.itb.read_misses 0 # DTB read misses 52system.cpu.itb.read_acv 0 # DTB read access violations 53system.cpu.itb.read_accesses 0 # DTB read accesses 54system.cpu.itb.write_hits 0 # DTB write hits 55system.cpu.itb.write_misses 0 # DTB write misses 56system.cpu.itb.write_acv 0 # DTB write access violations 57system.cpu.itb.write_accesses 0 # DTB write accesses 58system.cpu.itb.data_hits 0 # DTB hits 59system.cpu.itb.data_misses 0 # DTB misses 60system.cpu.itb.data_acv 0 # DTB access violations 61system.cpu.itb.data_accesses 0 # DTB accesses 62system.cpu.workload0.num_syscalls 17 # Number of system calls 63system.cpu.workload1.num_syscalls 17 # Number of system calls 64system.cpu.numCycles 29988 # number of cpu cycles simulated 65system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 66system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 67system.cpu.BPredUnit.lookups 6234 # Number of BP lookups 68system.cpu.BPredUnit.condPredicted 3551 # Number of conditional branches predicted 69system.cpu.BPredUnit.condIncorrect 1730 # Number of conditional branches incorrect 70system.cpu.BPredUnit.BTBLookups 4726 # Number of BTB lookups 71system.cpu.BPredUnit.BTBHits 792 # Number of BTB hits 72system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 73system.cpu.BPredUnit.usedRAS 829 # Number of times the RAS was used to get a target. 74system.cpu.BPredUnit.RASInCorrect 185 # Number of incorrect RAS predictions. 75system.cpu.fetch.icacheStallCycles 1565 # Number of cycles fetch is stalled on an Icache miss 76system.cpu.fetch.Insts 34888 # Number of instructions fetch has processed 77system.cpu.fetch.Branches 6234 # Number of branches that fetch encountered 78system.cpu.fetch.predictedBranches 1621 # Number of branches that fetch has predicted taken 79system.cpu.fetch.Cycles 5843 # Number of cycles fetch has run and was not squashing or blocked 80system.cpu.fetch.SquashCycles 1806 # Number of cycles fetch has spent squashing 81system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 82system.cpu.fetch.CacheLines 5063 # Number of cache lines fetched 83system.cpu.fetch.IcacheSquashes 763 # Number of outstanding Icache misses that were squashed 84system.cpu.fetch.rateDist::samples 24485 # Number of instructions fetched each cycle (Total) 85system.cpu.fetch.rateDist::mean 1.424872 # Number of instructions fetched each cycle (Total) 86system.cpu.fetch.rateDist::stdev 2.811431 # Number of instructions fetched each cycle (Total) 87system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 88system.cpu.fetch.rateDist::0 18642 76.14% 76.14% # Number of instructions fetched each cycle (Total) 89system.cpu.fetch.rateDist::1 463 1.89% 78.03% # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::2 348 1.42% 79.45% # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::3 451 1.84% 81.29% # Number of instructions fetched each cycle (Total) 92system.cpu.fetch.rateDist::4 433 1.77% 83.06% # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.rateDist::5 338 1.38% 84.44% # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.rateDist::6 497 2.03% 86.47% # Number of instructions fetched each cycle (Total) 95system.cpu.fetch.rateDist::7 532 2.17% 88.64% # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::8 2781 11.36% 100.00% # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::total 24485 # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.branchRate 0.207883 # Number of branch fetches per cycle 102system.cpu.fetch.rate 1.163399 # Number of inst fetches per cycle 103system.cpu.decode.IdleCycles 35160 # Number of cycles decode is idle 104system.cpu.decode.BlockedCycles 5629 # Number of cycles decode is blocked 105system.cpu.decode.RunCycles 5043 # Number of cycles decode is running 106system.cpu.decode.UnblockCycles 481 # Number of cycles decode is unblocking 107system.cpu.decode.SquashCycles 2441 # Number of cycles decode is squashing 108system.cpu.decode.BranchResolved 657 # Number of times decode resolved a branch 109system.cpu.decode.BranchMispred 429 # Number of times decode detected a branch misprediction 110system.cpu.decode.DecodedInsts 30497 # Number of instructions handled by decode 111system.cpu.decode.SquashedInsts 762 # Number of squashed instructions handled by decode 112system.cpu.rename.SquashCycles 2441 # Number of cycles rename is squashing 113system.cpu.rename.IdleCycles 35832 # Number of cycles rename is idle 114system.cpu.rename.BlockCycles 2821 # Number of cycles rename is blocking 115system.cpu.rename.serializeStallCycles 862 # count of cycles rename stalled for serializing inst 116system.cpu.rename.RunCycles 4769 # Number of cycles rename is running 117system.cpu.rename.UnblockCycles 2029 # Number of cycles rename is unblocking 118system.cpu.rename.RenamedInsts 28347 # Number of instructions processed by rename 119system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full 120system.cpu.rename.LSQFullEvents 2069 # Number of times rename has blocked due to LSQ full 121system.cpu.rename.RenamedOperands 21319 # Number of destination operands rename has renamed 122system.cpu.rename.RenameLookups 35425 # Number of register rename lookups that rename has made 123system.cpu.rename.int_rename_lookups 35391 # Number of integer rename lookups 124system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups 125system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed 126system.cpu.rename.UndoneMaps 12179 # Number of HB maps that are undone due to squashing 127system.cpu.rename.serializingInsts 54 # count of serializing insts renamed 128system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed 129system.cpu.rename.skidInsts 5554 # count of insts added to the skid buffer 130system.cpu.memDep0.insertedLoads 2631 # Number of loads inserted to the mem dependence unit. 131system.cpu.memDep0.insertedStores 1322 # Number of stores inserted to the mem dependence unit. 132system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. 133system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 134system.cpu.memDep1.insertedLoads 2538 # Number of loads inserted to the mem dependence unit. 135system.cpu.memDep1.insertedStores 1270 # Number of stores inserted to the mem dependence unit. 136system.cpu.memDep1.conflictingLoads 13 # Number of conflicting loads. 137system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. 138system.cpu.iq.iqInstsAdded 25174 # Number of instructions added to the IQ (excludes non-spec) 139system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ 140system.cpu.iq.iqInstsIssued 21355 # Number of instructions issued 141system.cpu.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued 142system.cpu.iq.iqSquashedInstsExamined 11204 # Number of squashed instructions iterated over during squash; mainly for profiling 143system.cpu.iq.iqSquashedOperandsExamined 6343 # Number of squashed operands that are examined and possibly removed from graph 144system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed 145system.cpu.iq.issued_per_cycle::samples 24485 # Number of insts issued each cycle 146system.cpu.iq.issued_per_cycle::mean 0.872167 # Number of insts issued each cycle 147system.cpu.iq.issued_per_cycle::stdev 1.446196 # Number of insts issued each cycle 148system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::0 15521 63.39% 63.39% # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::1 3217 13.14% 76.53% # Number of insts issued each cycle 151system.cpu.iq.issued_per_cycle::2 2370 9.68% 86.21% # Number of insts issued each cycle 152system.cpu.iq.issued_per_cycle::3 1453 5.93% 92.14% # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::4 1034 4.22% 96.37% # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::5 556 2.27% 98.64% # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::6 237 0.97% 99.60% # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::7 75 0.31% 99.91% # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::8 22 0.09% 100.00% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::total 24485 # Number of insts issued each cycle 162system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 163system.cpu.iq.fu_full::IntAlu 11 6.18% 6.18% # attempts to use FU when none available 164system.cpu.iq.fu_full::IntMult 0 0.00% 6.18% # attempts to use FU when none available 165system.cpu.iq.fu_full::IntDiv 0 0.00% 6.18% # attempts to use FU when none available 166system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.18% # attempts to use FU when none available 167system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.18% # attempts to use FU when none available 168system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.18% # attempts to use FU when none available 169system.cpu.iq.fu_full::FloatMult 0 0.00% 6.18% # attempts to use FU when none available 170system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.18% # attempts to use FU when none available 171system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.18% # attempts to use FU when none available 172system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.18% # attempts to use FU when none available 173system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.18% # attempts to use FU when none available 174system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.18% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.18% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.18% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.18% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdMult 0 0.00% 6.18% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.18% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdShift 0 0.00% 6.18% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.18% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.18% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.18% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.18% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.18% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.18% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.18% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.18% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.18% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.18% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.18% # attempts to use FU when none available 192system.cpu.iq.fu_full::MemRead 104 58.43% 64.61% # attempts to use FU when none available 193system.cpu.iq.fu_full::MemWrite 63 35.39% 100.00% # attempts to use FU when none available 194system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 195system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 196system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 197system.cpu.iq.FU_type_0::IntAlu 7361 67.94% 67.96% # Type of FU issued 198system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.97% # Type of FU issued 199system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.97% # Type of FU issued 200system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.99% # Type of FU issued 201system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.99% # Type of FU issued 202system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.99% # Type of FU issued 203system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.99% # Type of FU issued 204system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.99% # Type of FU issued 205system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.99% # Type of FU issued 206system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.99% # Type of FU issued 207system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.99% # Type of FU issued 208system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.99% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.99% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.99% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.99% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.99% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.99% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.99% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.99% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.99% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.99% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.99% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.99% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.99% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.99% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.99% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.99% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.99% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.99% # Type of FU issued 226system.cpu.iq.FU_type_0::MemRead 2308 21.30% 89.29% # Type of FU issued 227system.cpu.iq.FU_type_0::MemWrite 1160 10.71% 100.00% # Type of FU issued 228system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 229system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 230system.cpu.iq.FU_type_0::total 10834 # Type of FU issued 231system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued 232system.cpu.iq.FU_type_1::IntAlu 7172 68.17% 68.19% # Type of FU issued 233system.cpu.iq.FU_type_1::IntMult 1 0.01% 68.20% # Type of FU issued 234system.cpu.iq.FU_type_1::IntDiv 0 0.00% 68.20% # Type of FU issued 235system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 68.22% # Type of FU issued 236system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 68.22% # Type of FU issued 237system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 68.22% # Type of FU issued 238system.cpu.iq.FU_type_1::FloatMult 0 0.00% 68.22% # Type of FU issued 239system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 68.22% # Type of FU issued 240system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 68.22% # Type of FU issued 241system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 68.22% # Type of FU issued 242system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 68.22% # Type of FU issued 243system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 68.22% # Type of FU issued 244system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 68.22% # Type of FU issued 245system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 68.22% # Type of FU issued 246system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 68.22% # Type of FU issued 247system.cpu.iq.FU_type_1::SimdMult 0 0.00% 68.22% # Type of FU issued 248system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 68.22% # Type of FU issued 249system.cpu.iq.FU_type_1::SimdShift 0 0.00% 68.22% # Type of FU issued 250system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued 251system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 68.22% # Type of FU issued 252system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued 253system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued 254system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued 255system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued 256system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued 257system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 68.22% # Type of FU issued 258system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 68.22% # Type of FU issued 259system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued 260system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued 261system.cpu.iq.FU_type_1::MemRead 2223 21.13% 89.35% # Type of FU issued 262system.cpu.iq.FU_type_1::MemWrite 1121 10.65% 100.00% # Type of FU issued 263system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 264system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued 265system.cpu.iq.FU_type_1::total 10521 # Type of FU issued 266system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued 267system.cpu.iq.FU_type::IntAlu 14533 68.05% 68.07% # Type of FU issued 268system.cpu.iq.FU_type::IntMult 2 0.01% 68.08% # Type of FU issued 269system.cpu.iq.FU_type::IntDiv 0 0.00% 68.08% # Type of FU issued 270system.cpu.iq.FU_type::FloatAdd 4 0.02% 68.10% # Type of FU issued 271system.cpu.iq.FU_type::FloatCmp 0 0.00% 68.10% # Type of FU issued 272system.cpu.iq.FU_type::FloatCvt 0 0.00% 68.10% # Type of FU issued 273system.cpu.iq.FU_type::FloatMult 0 0.00% 68.10% # Type of FU issued 274system.cpu.iq.FU_type::FloatDiv 0 0.00% 68.10% # Type of FU issued 275system.cpu.iq.FU_type::FloatSqrt 0 0.00% 68.10% # Type of FU issued 276system.cpu.iq.FU_type::SimdAdd 0 0.00% 68.10% # Type of FU issued 277system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 68.10% # Type of FU issued 278system.cpu.iq.FU_type::SimdAlu 0 0.00% 68.10% # Type of FU issued 279system.cpu.iq.FU_type::SimdCmp 0 0.00% 68.10% # Type of FU issued 280system.cpu.iq.FU_type::SimdCvt 0 0.00% 68.10% # Type of FU issued 281system.cpu.iq.FU_type::SimdMisc 0 0.00% 68.10% # Type of FU issued 282system.cpu.iq.FU_type::SimdMult 0 0.00% 68.10% # Type of FU issued 283system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 68.10% # Type of FU issued 284system.cpu.iq.FU_type::SimdShift 0 0.00% 68.10% # Type of FU issued 285system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued 286system.cpu.iq.FU_type::SimdSqrt 0 0.00% 68.10% # Type of FU issued 287system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued 288system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued 289system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued 290system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued 291system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued 292system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 68.10% # Type of FU issued 293system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 68.10% # Type of FU issued 294system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 68.10% # Type of FU issued 295system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 68.10% # Type of FU issued 296system.cpu.iq.FU_type::MemRead 4531 21.22% 89.32% # Type of FU issued 297system.cpu.iq.FU_type::MemWrite 2281 10.68% 100.00% # Type of FU issued 298system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued 299system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued 300system.cpu.iq.FU_type::total 21355 # Type of FU issued 301system.cpu.iq.rate 0.712118 # Inst issue rate 302system.cpu.iq.fu_busy_cnt::0 95 # FU busy when requested 303system.cpu.iq.fu_busy_cnt::1 83 # FU busy when requested 304system.cpu.iq.fu_busy_cnt::total 178 # FU busy when requested 305system.cpu.iq.fu_busy_rate::0 0.004449 # FU busy rate (busy events/executed inst) 306system.cpu.iq.fu_busy_rate::1 0.003887 # FU busy rate (busy events/executed inst) 307system.cpu.iq.fu_busy_rate::total 0.008335 # FU busy rate (busy events/executed inst) 308system.cpu.iq.int_inst_queue_reads 67413 # Number of integer instruction queue reads 309system.cpu.iq.int_inst_queue_writes 36435 # Number of integer instruction queue writes 310system.cpu.iq.int_inst_queue_wakeup_accesses 19171 # Number of integer instruction queue wakeup accesses 311system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads 312system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 313system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses 314system.cpu.iq.int_alu_accesses 21507 # Number of integer alu accesses 315system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses 316system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores 317system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 318system.cpu.iew.lsq.thread0.squashedLoads 1448 # Number of loads squashed 319system.cpu.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed 320system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations 321system.cpu.iew.lsq.thread0.squashedStores 457 # Number of stores squashed 322system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 323system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 324system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 325system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 326system.cpu.iew.lsq.thread1.forwLoads 64 # Number of loads that had data forwarded from stores 327system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address 328system.cpu.iew.lsq.thread1.squashedLoads 1355 # Number of loads squashed 329system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 330system.cpu.iew.lsq.thread1.memOrderViolation 14 # Number of memory ordering violations 331system.cpu.iew.lsq.thread1.squashedStores 405 # Number of stores squashed 332system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 333system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 334system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled 335system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 336system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 337system.cpu.iew.iewSquashCycles 2441 # Number of cycles IEW is squashing 338system.cpu.iew.iewBlockCycles 573 # Number of cycles IEW is blocking 339system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking 340system.cpu.iew.iewDispatchedInsts 25387 # Number of instructions dispatched to IQ 341system.cpu.iew.iewDispSquashedInsts 653 # Number of squashed instructions skipped by dispatch 342system.cpu.iew.iewDispLoadInsts 5169 # Number of dispatched load instructions 343system.cpu.iew.iewDispStoreInsts 2592 # Number of dispatched store instructions 344system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions 345system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall 346system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall 347system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations 348system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly 349system.cpu.iew.predictedNotTakenIncorrect 1220 # Number of branches that were predicted not taken incorrectly 350system.cpu.iew.branchMispredicts 1482 # Number of branch mispredicts detected at execute 351system.cpu.iew.iewExecutedInsts 20001 # Number of executed instructions 352system.cpu.iew.iewExecLoadInsts::0 2104 # Number of load instructions executed 353system.cpu.iew.iewExecLoadInsts::1 2055 # Number of load instructions executed 354system.cpu.iew.iewExecLoadInsts::total 4159 # Number of load instructions executed 355system.cpu.iew.iewExecSquashedInsts 1354 # Number of squashed instructions skipped in execute 356system.cpu.iew.exec_swp::0 0 # number of swp insts executed 357system.cpu.iew.exec_swp::1 0 # number of swp insts executed 358system.cpu.iew.exec_swp::total 0 # number of swp insts executed 359system.cpu.iew.exec_nop::0 84 # number of nop insts executed 360system.cpu.iew.exec_nop::1 78 # number of nop insts executed 361system.cpu.iew.exec_nop::total 162 # number of nop insts executed 362system.cpu.iew.exec_refs::0 3212 # number of memory reference insts executed 363system.cpu.iew.exec_refs::1 3127 # number of memory reference insts executed 364system.cpu.iew.exec_refs::total 6339 # number of memory reference insts executed 365system.cpu.iew.exec_branches::0 1650 # Number of branches executed 366system.cpu.iew.exec_branches::1 1625 # Number of branches executed 367system.cpu.iew.exec_branches::total 3275 # Number of branches executed 368system.cpu.iew.exec_stores::0 1108 # Number of stores executed 369system.cpu.iew.exec_stores::1 1072 # Number of stores executed 370system.cpu.iew.exec_stores::total 2180 # Number of stores executed 371system.cpu.iew.exec_rate 0.666967 # Inst execution rate 372system.cpu.iew.wb_sent::0 9882 # cumulative count of insts sent to commit 373system.cpu.iew.wb_sent::1 9596 # cumulative count of insts sent to commit 374system.cpu.iew.wb_sent::total 19478 # cumulative count of insts sent to commit 375system.cpu.iew.wb_count::0 9755 # cumulative count of insts written-back 376system.cpu.iew.wb_count::1 9436 # cumulative count of insts written-back 377system.cpu.iew.wb_count::total 19191 # cumulative count of insts written-back 378system.cpu.iew.wb_producers::0 5007 # num instructions producing a value 379system.cpu.iew.wb_producers::1 4861 # num instructions producing a value 380system.cpu.iew.wb_producers::total 9868 # num instructions producing a value 381system.cpu.iew.wb_consumers::0 6484 # num instructions consuming a value 382system.cpu.iew.wb_consumers::1 6279 # num instructions consuming a value 383system.cpu.iew.wb_consumers::total 12763 # num instructions consuming a value 384system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ 385system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ 386system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ 387system.cpu.iew.wb_rate::0 0.325297 # insts written-back per cycle 388system.cpu.iew.wb_rate::1 0.314659 # insts written-back per cycle 389system.cpu.iew.wb_rate::total 0.639956 # insts written-back per cycle 390system.cpu.iew.wb_fanout::0 0.772209 # average fanout of values written-back 391system.cpu.iew.wb_fanout::1 0.774168 # average fanout of values written-back 392system.cpu.iew.wb_fanout::total 0.773172 # average fanout of values written-back 393system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ 394system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ 395system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ 396system.cpu.commit.commitCommittedInsts 12779 # The number of committed instructions 397system.cpu.commit.commitCommittedOps 12779 # The number of committed instructions 398system.cpu.commit.commitSquashedInsts 12568 # The number of squashed insts skipped by commit 399system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards 400system.cpu.commit.branchMispredicts 1309 # The number of times a branch was mispredicted 401system.cpu.commit.committed_per_cycle::samples 24431 # Number of insts commited each cycle 402system.cpu.commit.committed_per_cycle::mean 0.523065 # Number of insts commited each cycle 403system.cpu.commit.committed_per_cycle::stdev 1.302863 # Number of insts commited each cycle 404system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 405system.cpu.commit.committed_per_cycle::0 18816 77.02% 77.02% # Number of insts commited each cycle 406system.cpu.commit.committed_per_cycle::1 2827 11.57% 88.59% # Number of insts commited each cycle 407system.cpu.commit.committed_per_cycle::2 1198 4.90% 93.49% # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::3 508 2.08% 95.57% # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::4 350 1.43% 97.00% # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::5 244 1.00% 98.00% # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::6 205 0.84% 98.84% # Number of insts commited each cycle 412system.cpu.commit.committed_per_cycle::7 82 0.34% 99.18% # Number of insts commited each cycle 413system.cpu.commit.committed_per_cycle::8 201 0.82% 100.00% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::total 24431 # Number of insts commited each cycle 418system.cpu.commit.committedInsts::0 6389 # Number of instructions committed 419system.cpu.commit.committedInsts::1 6390 # Number of instructions committed 420system.cpu.commit.committedInsts::total 12779 # Number of instructions committed 421system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed 422system.cpu.commit.committedOps::1 6390 # Number of ops (including micro ops) committed 423system.cpu.commit.committedOps::total 12779 # Number of ops (including micro ops) committed 424system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 425system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed 426system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed 427system.cpu.commit.refs::0 2048 # Number of memory references committed 428system.cpu.commit.refs::1 2048 # Number of memory references committed 429system.cpu.commit.refs::total 4096 # Number of memory references committed 430system.cpu.commit.loads::0 1183 # Number of loads committed 431system.cpu.commit.loads::1 1183 # Number of loads committed 432system.cpu.commit.loads::total 2366 # Number of loads committed 433system.cpu.commit.membars::0 0 # Number of memory barriers committed 434system.cpu.commit.membars::1 0 # Number of memory barriers committed 435system.cpu.commit.membars::total 0 # Number of memory barriers committed 436system.cpu.commit.branches::0 1050 # Number of branches committed 437system.cpu.commit.branches::1 1050 # Number of branches committed 438system.cpu.commit.branches::total 2100 # Number of branches committed 439system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. 440system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. 441system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. 442system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions. 443system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions. 444system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions. 445system.cpu.commit.function_calls::0 127 # Number of function calls committed. 446system.cpu.commit.function_calls::1 127 # Number of function calls committed. 447system.cpu.commit.function_calls::total 254 # Number of function calls committed. 448system.cpu.commit.bw_lim_events 201 # number cycles where commit BW limit reached 449system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits 450system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits 451system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits 452system.cpu.rob.rob_reads 117663 # The number of ROB reads 453system.cpu.rob.rob_writes 53150 # The number of ROB writes 454system.cpu.timesIdled 296 # Number of times that the entire CPU went into an idle state and unscheduled itself 455system.cpu.idleCycles 5503 # Total number of cycles that the CPU has spent unscheduled due to idling 456system.cpu.committedInsts::0 6372 # Number of Instructions Simulated 457system.cpu.committedInsts::1 6373 # Number of Instructions Simulated 458system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated 459system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated 460system.cpu.committedInsts_total 12745 # Number of Instructions Simulated 461system.cpu.cpi::0 4.706215 # CPI: Cycles Per Instruction 462system.cpu.cpi::1 4.705476 # CPI: Cycles Per Instruction 463system.cpu.cpi_total 2.352923 # CPI: Total CPI of All Threads 464system.cpu.ipc::0 0.212485 # IPC: Instructions Per Cycle 465system.cpu.ipc::1 0.212518 # IPC: Instructions Per Cycle 466system.cpu.ipc_total 0.425003 # IPC: Total IPC of All Threads 467system.cpu.int_regfile_reads 25299 # number of integer regfile reads 468system.cpu.int_regfile_writes 14501 # number of integer regfile writes 469system.cpu.fp_regfile_reads 16 # number of floating regfile reads 470system.cpu.fp_regfile_writes 4 # number of floating regfile writes 471system.cpu.misc_regfile_reads 2 # number of misc regfile reads 472system.cpu.misc_regfile_writes 2 # number of misc regfile writes 473system.cpu.icache.replacements::0 6 # number of replacements 474system.cpu.icache.replacements::1 0 # number of replacements 475system.cpu.icache.replacements::total 6 # number of replacements 476system.cpu.icache.tagsinuse 314.927989 # Cycle average of tags in use 477system.cpu.icache.total_refs 4192 # Total number of references to valid blocks. 478system.cpu.icache.sampled_refs 625 # Sample count of references to valid blocks. 479system.cpu.icache.avg_refs 6.707200 # Average number of references to valid blocks. 480system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 481system.cpu.icache.occ_blocks::cpu.inst 314.927989 # Average occupied blocks per requestor 482system.cpu.icache.occ_percent::cpu.inst 0.153773 # Average percentage of cache occupancy 483system.cpu.icache.occ_percent::total 0.153773 # Average percentage of cache occupancy 484system.cpu.icache.ReadReq_hits::cpu.inst 4192 # number of ReadReq hits 485system.cpu.icache.ReadReq_hits::total 4192 # number of ReadReq hits 486system.cpu.icache.demand_hits::cpu.inst 4192 # number of demand (read+write) hits 487system.cpu.icache.demand_hits::total 4192 # number of demand (read+write) hits 488system.cpu.icache.overall_hits::cpu.inst 4192 # number of overall hits 489system.cpu.icache.overall_hits::total 4192 # number of overall hits 490system.cpu.icache.ReadReq_misses::cpu.inst 871 # number of ReadReq misses 491system.cpu.icache.ReadReq_misses::total 871 # number of ReadReq misses 492system.cpu.icache.demand_misses::cpu.inst 871 # number of demand (read+write) misses 493system.cpu.icache.demand_misses::total 871 # number of demand (read+write) misses 494system.cpu.icache.overall_misses::cpu.inst 871 # number of overall misses 495system.cpu.icache.overall_misses::total 871 # number of overall misses 496system.cpu.icache.ReadReq_miss_latency::cpu.inst 34167000 # number of ReadReq miss cycles 497system.cpu.icache.ReadReq_miss_latency::total 34167000 # number of ReadReq miss cycles 498system.cpu.icache.demand_miss_latency::cpu.inst 34167000 # number of demand (read+write) miss cycles 499system.cpu.icache.demand_miss_latency::total 34167000 # number of demand (read+write) miss cycles 500system.cpu.icache.overall_miss_latency::cpu.inst 34167000 # number of overall miss cycles 501system.cpu.icache.overall_miss_latency::total 34167000 # number of overall miss cycles 502system.cpu.icache.ReadReq_accesses::cpu.inst 5063 # number of ReadReq accesses(hits+misses) 503system.cpu.icache.ReadReq_accesses::total 5063 # number of ReadReq accesses(hits+misses) 504system.cpu.icache.demand_accesses::cpu.inst 5063 # number of demand (read+write) accesses 505system.cpu.icache.demand_accesses::total 5063 # number of demand (read+write) accesses 506system.cpu.icache.overall_accesses::cpu.inst 5063 # number of overall (read+write) accesses 507system.cpu.icache.overall_accesses::total 5063 # number of overall (read+write) accesses 508system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.172032 # miss rate for ReadReq accesses 509system.cpu.icache.ReadReq_miss_rate::total 0.172032 # miss rate for ReadReq accesses 510system.cpu.icache.demand_miss_rate::cpu.inst 0.172032 # miss rate for demand accesses 511system.cpu.icache.demand_miss_rate::total 0.172032 # miss rate for demand accesses 512system.cpu.icache.overall_miss_rate::cpu.inst 0.172032 # miss rate for overall accesses 513system.cpu.icache.overall_miss_rate::total 0.172032 # miss rate for overall accesses 514system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39227.324914 # average ReadReq miss latency 515system.cpu.icache.ReadReq_avg_miss_latency::total 39227.324914 # average ReadReq miss latency 516system.cpu.icache.demand_avg_miss_latency::cpu.inst 39227.324914 # average overall miss latency 517system.cpu.icache.demand_avg_miss_latency::total 39227.324914 # average overall miss latency 518system.cpu.icache.overall_avg_miss_latency::cpu.inst 39227.324914 # average overall miss latency 519system.cpu.icache.overall_avg_miss_latency::total 39227.324914 # average overall miss latency 520system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 521system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 522system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 523system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 524system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 525system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 526system.cpu.icache.fast_writes 0 # number of fast writes performed 527system.cpu.icache.cache_copies 0 # number of cache copies performed 528system.cpu.icache.ReadReq_mshr_hits::cpu.inst 246 # number of ReadReq MSHR hits 529system.cpu.icache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits 530system.cpu.icache.demand_mshr_hits::cpu.inst 246 # number of demand (read+write) MSHR hits 531system.cpu.icache.demand_mshr_hits::total 246 # number of demand (read+write) MSHR hits 532system.cpu.icache.overall_mshr_hits::cpu.inst 246 # number of overall MSHR hits 533system.cpu.icache.overall_mshr_hits::total 246 # number of overall MSHR hits 534system.cpu.icache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses 535system.cpu.icache.ReadReq_mshr_misses::total 625 # number of ReadReq MSHR misses 536system.cpu.icache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses 537system.cpu.icache.demand_mshr_misses::total 625 # number of demand (read+write) MSHR misses 538system.cpu.icache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses 539system.cpu.icache.overall_mshr_misses::total 625 # number of overall MSHR misses 540system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24783500 # number of ReadReq MSHR miss cycles 541system.cpu.icache.ReadReq_mshr_miss_latency::total 24783500 # number of ReadReq MSHR miss cycles 542system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24783500 # number of demand (read+write) MSHR miss cycles 543system.cpu.icache.demand_mshr_miss_latency::total 24783500 # number of demand (read+write) MSHR miss cycles 544system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24783500 # number of overall MSHR miss cycles 545system.cpu.icache.overall_mshr_miss_latency::total 24783500 # number of overall MSHR miss cycles 546system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.123445 # mshr miss rate for ReadReq accesses 547system.cpu.icache.ReadReq_mshr_miss_rate::total 0.123445 # mshr miss rate for ReadReq accesses 548system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.123445 # mshr miss rate for demand accesses 549system.cpu.icache.demand_mshr_miss_rate::total 0.123445 # mshr miss rate for demand accesses 550system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.123445 # mshr miss rate for overall accesses 551system.cpu.icache.overall_mshr_miss_rate::total 0.123445 # mshr miss rate for overall accesses 552system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39653.600000 # average ReadReq mshr miss latency 553system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39653.600000 # average ReadReq mshr miss latency 554system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39653.600000 # average overall mshr miss latency 555system.cpu.icache.demand_avg_mshr_miss_latency::total 39653.600000 # average overall mshr miss latency 556system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39653.600000 # average overall mshr miss latency 557system.cpu.icache.overall_avg_mshr_miss_latency::total 39653.600000 # average overall mshr miss latency 558system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 559system.cpu.dcache.replacements::0 0 # number of replacements 560system.cpu.dcache.replacements::1 0 # number of replacements 561system.cpu.dcache.replacements::total 0 # number of replacements 562system.cpu.dcache.tagsinuse 215.917106 # Cycle average of tags in use 563system.cpu.dcache.total_refs 4606 # Total number of references to valid blocks. 564system.cpu.dcache.sampled_refs 350 # Sample count of references to valid blocks. 565system.cpu.dcache.avg_refs 13.160000 # Average number of references to valid blocks. 566system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 567system.cpu.dcache.occ_blocks::cpu.data 215.917106 # Average occupied blocks per requestor 568system.cpu.dcache.occ_percent::cpu.data 0.052714 # Average percentage of cache occupancy 569system.cpu.dcache.occ_percent::total 0.052714 # Average percentage of cache occupancy 570system.cpu.dcache.ReadReq_hits::cpu.data 3594 # number of ReadReq hits 571system.cpu.dcache.ReadReq_hits::total 3594 # number of ReadReq hits 572system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits 573system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits 574system.cpu.dcache.demand_hits::cpu.data 4606 # number of demand (read+write) hits 575system.cpu.dcache.demand_hits::total 4606 # number of demand (read+write) hits 576system.cpu.dcache.overall_hits::cpu.data 4606 # number of overall hits 577system.cpu.dcache.overall_hits::total 4606 # number of overall hits 578system.cpu.dcache.ReadReq_misses::cpu.data 324 # number of ReadReq misses 579system.cpu.dcache.ReadReq_misses::total 324 # number of ReadReq misses 580system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses 581system.cpu.dcache.WriteReq_misses::total 718 # number of WriteReq misses 582system.cpu.dcache.demand_misses::cpu.data 1042 # number of demand (read+write) misses 583system.cpu.dcache.demand_misses::total 1042 # number of demand (read+write) misses 584system.cpu.dcache.overall_misses::cpu.data 1042 # number of overall misses 585system.cpu.dcache.overall_misses::total 1042 # number of overall misses 586system.cpu.dcache.ReadReq_miss_latency::cpu.data 14022500 # number of ReadReq miss cycles 587system.cpu.dcache.ReadReq_miss_latency::total 14022500 # number of ReadReq miss cycles 588system.cpu.dcache.WriteReq_miss_latency::cpu.data 28872500 # number of WriteReq miss cycles 589system.cpu.dcache.WriteReq_miss_latency::total 28872500 # number of WriteReq miss cycles 590system.cpu.dcache.demand_miss_latency::cpu.data 42895000 # number of demand (read+write) miss cycles 591system.cpu.dcache.demand_miss_latency::total 42895000 # number of demand (read+write) miss cycles 592system.cpu.dcache.overall_miss_latency::cpu.data 42895000 # number of overall miss cycles 593system.cpu.dcache.overall_miss_latency::total 42895000 # number of overall miss cycles 594system.cpu.dcache.ReadReq_accesses::cpu.data 3918 # number of ReadReq accesses(hits+misses) 595system.cpu.dcache.ReadReq_accesses::total 3918 # number of ReadReq accesses(hits+misses) 596system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) 597system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) 598system.cpu.dcache.demand_accesses::cpu.data 5648 # number of demand (read+write) accesses 599system.cpu.dcache.demand_accesses::total 5648 # number of demand (read+write) accesses 600system.cpu.dcache.overall_accesses::cpu.data 5648 # number of overall (read+write) accesses 601system.cpu.dcache.overall_accesses::total 5648 # number of overall (read+write) accesses 602system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082695 # miss rate for ReadReq accesses 603system.cpu.dcache.ReadReq_miss_rate::total 0.082695 # miss rate for ReadReq accesses 604system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 605system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 606system.cpu.dcache.demand_miss_rate::cpu.data 0.184490 # miss rate for demand accesses 607system.cpu.dcache.demand_miss_rate::total 0.184490 # miss rate for demand accesses 608system.cpu.dcache.overall_miss_rate::cpu.data 0.184490 # miss rate for overall accesses 609system.cpu.dcache.overall_miss_rate::total 0.184490 # miss rate for overall accesses 610system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43279.320988 # average ReadReq miss latency 611system.cpu.dcache.ReadReq_avg_miss_latency::total 43279.320988 # average ReadReq miss latency 612system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40212.395543 # average WriteReq miss latency 613system.cpu.dcache.WriteReq_avg_miss_latency::total 40212.395543 # average WriteReq miss latency 614system.cpu.dcache.demand_avg_miss_latency::cpu.data 41166.026871 # average overall miss latency 615system.cpu.dcache.demand_avg_miss_latency::total 41166.026871 # average overall miss latency 616system.cpu.dcache.overall_avg_miss_latency::cpu.data 41166.026871 # average overall miss latency 617system.cpu.dcache.overall_avg_miss_latency::total 41166.026871 # average overall miss latency 618system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 619system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 620system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 621system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 622system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 623system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 624system.cpu.dcache.fast_writes 0 # number of fast writes performed 625system.cpu.dcache.cache_copies 0 # number of cache copies performed 626system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits 627system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits 628system.cpu.dcache.WriteReq_mshr_hits::cpu.data 572 # number of WriteReq MSHR hits 629system.cpu.dcache.WriteReq_mshr_hits::total 572 # number of WriteReq MSHR hits 630system.cpu.dcache.demand_mshr_hits::cpu.data 691 # number of demand (read+write) MSHR hits 631system.cpu.dcache.demand_mshr_hits::total 691 # number of demand (read+write) MSHR hits 632system.cpu.dcache.overall_mshr_hits::cpu.data 691 # number of overall MSHR hits 633system.cpu.dcache.overall_mshr_hits::total 691 # number of overall MSHR hits 634system.cpu.dcache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses 635system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses 636system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses 637system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses 638system.cpu.dcache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses 639system.cpu.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 640system.cpu.dcache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses 641system.cpu.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses 642system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9453500 # number of ReadReq MSHR miss cycles 643system.cpu.dcache.ReadReq_mshr_miss_latency::total 9453500 # number of ReadReq MSHR miss cycles 644system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6369000 # number of WriteReq MSHR miss cycles 645system.cpu.dcache.WriteReq_mshr_miss_latency::total 6369000 # number of WriteReq MSHR miss cycles 646system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15822500 # number of demand (read+write) MSHR miss cycles 647system.cpu.dcache.demand_mshr_miss_latency::total 15822500 # number of demand (read+write) MSHR miss cycles 648system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15822500 # number of overall MSHR miss cycles 649system.cpu.dcache.overall_mshr_miss_latency::total 15822500 # number of overall MSHR miss cycles 650system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052323 # mshr miss rate for ReadReq accesses 651system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses 652system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 653system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 654system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062146 # mshr miss rate for demand accesses 655system.cpu.dcache.demand_mshr_miss_rate::total 0.062146 # mshr miss rate for demand accesses 656system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062146 # mshr miss rate for overall accesses 657system.cpu.dcache.overall_mshr_miss_rate::total 0.062146 # mshr miss rate for overall accesses 658system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46114.634146 # average ReadReq mshr miss latency 659system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46114.634146 # average ReadReq mshr miss latency 660system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43623.287671 # average WriteReq mshr miss latency 661system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43623.287671 # average WriteReq mshr miss latency 662system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45078.347578 # average overall mshr miss latency 663system.cpu.dcache.demand_avg_mshr_miss_latency::total 45078.347578 # average overall mshr miss latency 664system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45078.347578 # average overall mshr miss latency 665system.cpu.dcache.overall_avg_mshr_miss_latency::total 45078.347578 # average overall mshr miss latency 666system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 667system.cpu.l2cache.replacements::0 0 # number of replacements 668system.cpu.l2cache.replacements::1 0 # number of replacements 669system.cpu.l2cache.replacements::total 0 # number of replacements 670system.cpu.l2cache.tagsinuse 435.815079 # Cycle average of tags in use 671system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 672system.cpu.l2cache.sampled_refs 827 # Sample count of references to valid blocks. 673system.cpu.l2cache.avg_refs 0.002418 # Average number of references to valid blocks. 674system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 675system.cpu.l2cache.occ_blocks::cpu.inst 315.212279 # Average occupied blocks per requestor 676system.cpu.l2cache.occ_blocks::cpu.data 120.602800 # Average occupied blocks per requestor 677system.cpu.l2cache.occ_percent::cpu.inst 0.009620 # Average percentage of cache occupancy 678system.cpu.l2cache.occ_percent::cpu.data 0.003681 # Average percentage of cache occupancy 679system.cpu.l2cache.occ_percent::total 0.013300 # Average percentage of cache occupancy 680system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 681system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 682system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 683system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 684system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 685system.cpu.l2cache.overall_hits::total 2 # number of overall hits 686system.cpu.l2cache.ReadReq_misses::cpu.inst 623 # number of ReadReq misses 687system.cpu.l2cache.ReadReq_misses::cpu.data 205 # number of ReadReq misses 688system.cpu.l2cache.ReadReq_misses::total 828 # number of ReadReq misses 689system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses 690system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses 691system.cpu.l2cache.demand_misses::cpu.inst 623 # number of demand (read+write) misses 692system.cpu.l2cache.demand_misses::cpu.data 351 # number of demand (read+write) misses 693system.cpu.l2cache.demand_misses::total 974 # number of demand (read+write) misses 694system.cpu.l2cache.overall_misses::cpu.inst 623 # number of overall misses 695system.cpu.l2cache.overall_misses::cpu.data 351 # number of overall misses 696system.cpu.l2cache.overall_misses::total 974 # number of overall misses 697system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24119500 # number of ReadReq miss cycles 698system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9201500 # number of ReadReq miss cycles 699system.cpu.l2cache.ReadReq_miss_latency::total 33321000 # number of ReadReq miss cycles 700system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6205000 # number of ReadExReq miss cycles 701system.cpu.l2cache.ReadExReq_miss_latency::total 6205000 # number of ReadExReq miss cycles 702system.cpu.l2cache.demand_miss_latency::cpu.inst 24119500 # number of demand (read+write) miss cycles 703system.cpu.l2cache.demand_miss_latency::cpu.data 15406500 # number of demand (read+write) miss cycles 704system.cpu.l2cache.demand_miss_latency::total 39526000 # number of demand (read+write) miss cycles 705system.cpu.l2cache.overall_miss_latency::cpu.inst 24119500 # number of overall miss cycles 706system.cpu.l2cache.overall_miss_latency::cpu.data 15406500 # number of overall miss cycles 707system.cpu.l2cache.overall_miss_latency::total 39526000 # number of overall miss cycles 708system.cpu.l2cache.ReadReq_accesses::cpu.inst 625 # number of ReadReq accesses(hits+misses) 709system.cpu.l2cache.ReadReq_accesses::cpu.data 205 # number of ReadReq accesses(hits+misses) 710system.cpu.l2cache.ReadReq_accesses::total 830 # number of ReadReq accesses(hits+misses) 711system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) 712system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) 713system.cpu.l2cache.demand_accesses::cpu.inst 625 # number of demand (read+write) accesses 714system.cpu.l2cache.demand_accesses::cpu.data 351 # number of demand (read+write) accesses 715system.cpu.l2cache.demand_accesses::total 976 # number of demand (read+write) accesses 716system.cpu.l2cache.overall_accesses::cpu.inst 625 # number of overall (read+write) accesses 717system.cpu.l2cache.overall_accesses::cpu.data 351 # number of overall (read+write) accesses 718system.cpu.l2cache.overall_accesses::total 976 # number of overall (read+write) accesses 719system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996800 # miss rate for ReadReq accesses 720system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 721system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses 722system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 723system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 724system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996800 # miss rate for demand accesses 725system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 726system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses 727system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996800 # miss rate for overall accesses 728system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 729system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses 730system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 38715.088283 # average ReadReq miss latency 731system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 44885.365854 # average ReadReq miss latency 732system.cpu.l2cache.ReadReq_avg_miss_latency::total 40242.753623 # average ReadReq miss latency 733system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42500 # average ReadExReq miss latency 734system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42500 # average ReadExReq miss latency 735system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 38715.088283 # average overall miss latency 736system.cpu.l2cache.demand_avg_miss_latency::cpu.data 43893.162393 # average overall miss latency 737system.cpu.l2cache.demand_avg_miss_latency::total 40581.108830 # average overall miss latency 738system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38715.088283 # average overall miss latency 739system.cpu.l2cache.overall_avg_miss_latency::cpu.data 43893.162393 # average overall miss latency 740system.cpu.l2cache.overall_avg_miss_latency::total 40581.108830 # average overall miss latency 741system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked 742system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 743system.cpu.l2cache.blocked::no_mshrs 10 # number of cycles access was blocked 744system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 745system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3750 # average number of cycles each access was blocked 746system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 747system.cpu.l2cache.fast_writes 0 # number of fast writes performed 748system.cpu.l2cache.cache_copies 0 # number of cache copies performed 749system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 623 # number of ReadReq MSHR misses 750system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses 751system.cpu.l2cache.ReadReq_mshr_misses::total 828 # number of ReadReq MSHR misses 752system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses 753system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses 754system.cpu.l2cache.demand_mshr_misses::cpu.inst 623 # number of demand (read+write) MSHR misses 755system.cpu.l2cache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses 756system.cpu.l2cache.demand_mshr_misses::total 974 # number of demand (read+write) MSHR misses 757system.cpu.l2cache.overall_mshr_misses::cpu.inst 623 # number of overall MSHR misses 758system.cpu.l2cache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses 759system.cpu.l2cache.overall_mshr_misses::total 974 # number of overall MSHR misses 760system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22168000 # number of ReadReq MSHR miss cycles 761system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8579500 # number of ReadReq MSHR miss cycles 762system.cpu.l2cache.ReadReq_mshr_miss_latency::total 30747500 # number of ReadReq MSHR miss cycles 763system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5752000 # number of ReadExReq MSHR miss cycles 764system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5752000 # number of ReadExReq MSHR miss cycles 765system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22168000 # number of demand (read+write) MSHR miss cycles 766system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14331500 # number of demand (read+write) MSHR miss cycles 767system.cpu.l2cache.demand_mshr_miss_latency::total 36499500 # number of demand (read+write) MSHR miss cycles 768system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22168000 # number of overall MSHR miss cycles 769system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14331500 # number of overall MSHR miss cycles 770system.cpu.l2cache.overall_mshr_miss_latency::total 36499500 # number of overall MSHR miss cycles 771system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for ReadReq accesses 772system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 773system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses 774system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 775system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 776system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for demand accesses 777system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 778system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses 779system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for overall accesses 780system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 781system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses 782system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35582.664526 # average ReadReq mshr miss latency 783system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41851.219512 # average ReadReq mshr miss latency 784system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37134.661836 # average ReadReq mshr miss latency 785system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39397.260274 # average ReadExReq mshr miss latency 786system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39397.260274 # average ReadExReq mshr miss latency 787system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35582.664526 # average overall mshr miss latency 788system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40830.484330 # average overall mshr miss latency 789system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37473.819302 # average overall mshr miss latency 790system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35582.664526 # average overall mshr miss latency 791system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40830.484330 # average overall mshr miss latency 792system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37473.819302 # average overall mshr miss latency 793system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 794 795---------- End Simulation Statistics ---------- 796