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11960:c7bf1b698ccd |
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29-Mar-2017 |
Gabe Black <gabeblack@google.com> |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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11955:1170d039b31e |
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03-Apr-2017 |
Gabe Black <gabeblack@google.com> |
stats: Rename num_syscalls to numSyscalls in the reference stats.
The name of the stat was changed in the following change which broke all the
reference outputs.
commit 2367198921765848a4f5b3d020a7cc5776209f80
Author: Brandon Potter <brandon.potter@amd.com>
Date: Mon Feb 27 14:10:15 2017 -0500
syscall_emul: [PATCH 15/22] add clone/execve for threading and
multiprocess simulations
Change-Id: Id98b085ccae098c50c434ad81a72beee46084f40
Reviewed-on: https://gem5-review.googlesource.com/2651
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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| #
11954:19e1cd4edfd2 |
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30-Mar-2017 |
Gabe Black <gabeblack@google.com> |
stats: Update 01.hello-2T-smt and 40.perlbmks stats on ARM/Alpha o3-timing.
The following change removed a write to an integer register when completing
a system call. This changed the reference statistics slightly.
commit 073cb266079edddec64ea8cd5169dd2cbef8f812
Author: Brandon Potter <brandon.potter@amd.com>
Date: Mon Feb 27 14:10:02 2017 -0500
syscall_emul: [patch 14/22] adds identifier system calls
Change-Id: I3bee42ab826dd9cbc49aab34340da57caf4f045d
Reviewed-on: https://gem5-review.googlesource.com/2650
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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11860:67dee11badea |
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19-Feb-2017 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Get all stats updated to reflect current behaviour
Line everything up again.
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| #
11731:c473ca7cc650 |
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30-Nov-2016 |
Jason Lowe-Power <jason@lowepower.com> |
tests: Regression stats updated for recent patches
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| #
11687:b3d5f0e9e258 |
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19-Oct-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to reflect recent changes to floats
Mostly just splitting out the floats ops and corresponding
reads/writes.
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11680:b4d943429dc6 |
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13-Oct-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
stats: update references
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| #
11606:6b749761c398 |
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12-Aug-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Update to match classic memory changes
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| #
11570:4aac82f10951 |
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21-Jul-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
stats: update references
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11530:6e143fd2cabf |
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06-Jun-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Add power stats to test references
Change-Id: Ic827213134b199446822f128b81d4a480e777fee
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11502:e273e86a873d |
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31-May-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
stats: update for snoop filter tweak
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| #
11456:c0fb4435b80f |
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21-Apr-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to reflect cache changes
Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.
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11440:76b5639162af |
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08-Apr-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
stats: update stats for thermals, indirect BP
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11390:f40859930028 |
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17-Mar-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: update stats for ld.so support
Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
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11384:e3cbd2823210 |
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17-Mar-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: update stats for mmap() change.
SE O3 runs see an additional reg read per mmap() call.
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11312:3d7a85d71bd1 |
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22-Jan-2016 |
Tony Gutierrez <anthony.gutierrez@amd.com> |
stats: update stats to after GPU checkin
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11268:8b4b55d79ddd |
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12-Dec-2015 |
Anthony Gutierrez <atgutier@umich.edu> |
stats: bump stats to reflect ruby tester changes
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11219:b65d4e878ed2 |
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16-Nov-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to recent chagnesets
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| #
11214:966091379ded |
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16-Nov-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: remove wb_penalized and wb_penalized_rate
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| #
11201:b1bd4afb6b16 |
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06-Nov-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to match cache changes
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| #
11156:a37dda0f0202 |
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05-Oct-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Update SMT tests to correctly configure CPUs
The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup
the number of threads before creating interrupt controllers, which
confused the constructor in BaseCPU. This changeset adds SMT support
to the test configuration infrastructure.
|