stats.txt revision 8983
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000014 # Number of seconds simulated 4sim_ticks 13973500 # Number of ticks simulated 5final_tick 13973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 43715 # Simulator instruction rate (inst/s) 8host_op_rate 43711 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47815570 # Simulator tick rate (ticks/s) 10host_mem_usage 215652 # Number of bytes of host memory used 11host_seconds 0.29 # Real time elapsed on the host 12sim_insts 12773 # Number of instructions simulated 13sim_ops 12773 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 62784 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 40192 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 981 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 4493076180 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 2876301571 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 4493076180 # Total bandwidth to/from this memory (bytes/s) 23system.cpu.dtb.fetch_hits 0 # ITB hits 24system.cpu.dtb.fetch_misses 0 # ITB misses 25system.cpu.dtb.fetch_acv 0 # ITB acv 26system.cpu.dtb.fetch_accesses 0 # ITB accesses 27system.cpu.dtb.read_hits 4112 # DTB read hits 28system.cpu.dtb.read_misses 99 # DTB read misses 29system.cpu.dtb.read_acv 0 # DTB read access violations 30system.cpu.dtb.read_accesses 4211 # DTB read accesses 31system.cpu.dtb.write_hits 2113 # DTB write hits 32system.cpu.dtb.write_misses 55 # DTB write misses 33system.cpu.dtb.write_acv 0 # DTB write access violations 34system.cpu.dtb.write_accesses 2168 # DTB write accesses 35system.cpu.dtb.data_hits 6225 # DTB hits 36system.cpu.dtb.data_misses 154 # DTB misses 37system.cpu.dtb.data_acv 0 # DTB access violations 38system.cpu.dtb.data_accesses 6379 # DTB accesses 39system.cpu.itb.fetch_hits 5262 # ITB hits 40system.cpu.itb.fetch_misses 46 # ITB misses 41system.cpu.itb.fetch_acv 0 # ITB acv 42system.cpu.itb.fetch_accesses 5308 # ITB accesses 43system.cpu.itb.read_hits 0 # DTB read hits 44system.cpu.itb.read_misses 0 # DTB read misses 45system.cpu.itb.read_acv 0 # DTB read access violations 46system.cpu.itb.read_accesses 0 # DTB read accesses 47system.cpu.itb.write_hits 0 # DTB write hits 48system.cpu.itb.write_misses 0 # DTB write misses 49system.cpu.itb.write_acv 0 # DTB write access violations 50system.cpu.itb.write_accesses 0 # DTB write accesses 51system.cpu.itb.data_hits 0 # DTB hits 52system.cpu.itb.data_misses 0 # DTB misses 53system.cpu.itb.data_acv 0 # DTB access violations 54system.cpu.itb.data_accesses 0 # DTB accesses 55system.cpu.workload0.num_syscalls 17 # Number of system calls 56system.cpu.workload1.num_syscalls 17 # Number of system calls 57system.cpu.numCycles 27948 # number of cpu cycles simulated 58system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 59system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 60system.cpu.BPredUnit.lookups 6404 # Number of BP lookups 61system.cpu.BPredUnit.condPredicted 3641 # Number of conditional branches predicted 62system.cpu.BPredUnit.condIncorrect 1747 # Number of conditional branches incorrect 63system.cpu.BPredUnit.BTBLookups 4779 # Number of BTB lookups 64system.cpu.BPredUnit.BTBHits 777 # Number of BTB hits 65system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 66system.cpu.BPredUnit.usedRAS 907 # Number of times the RAS was used to get a target. 67system.cpu.BPredUnit.RASInCorrect 237 # Number of incorrect RAS predictions. 68system.cpu.fetch.icacheStallCycles 1564 # Number of cycles fetch is stalled on an Icache miss 69system.cpu.fetch.Insts 36319 # Number of instructions fetch has processed 70system.cpu.fetch.Branches 6404 # Number of branches that fetch encountered 71system.cpu.fetch.predictedBranches 1684 # Number of branches that fetch has predicted taken 72system.cpu.fetch.Cycles 6095 # Number of cycles fetch has run and was not squashing or blocked 73system.cpu.fetch.SquashCycles 1819 # Number of cycles fetch has spent squashing 74system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 75system.cpu.fetch.CacheLines 5262 # Number of cache lines fetched 76system.cpu.fetch.IcacheSquashes 778 # Number of outstanding Icache misses that were squashed 77system.cpu.fetch.rateDist::samples 22184 # Number of instructions fetched each cycle (Total) 78system.cpu.fetch.rateDist::mean 1.637171 # Number of instructions fetched each cycle (Total) 79system.cpu.fetch.rateDist::stdev 2.955550 # Number of instructions fetched each cycle (Total) 80system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 81system.cpu.fetch.rateDist::0 16089 72.53% 72.53% # Number of instructions fetched each cycle (Total) 82system.cpu.fetch.rateDist::1 484 2.18% 74.71% # Number of instructions fetched each cycle (Total) 83system.cpu.fetch.rateDist::2 383 1.73% 76.43% # Number of instructions fetched each cycle (Total) 84system.cpu.fetch.rateDist::3 489 2.20% 78.64% # Number of instructions fetched each cycle (Total) 85system.cpu.fetch.rateDist::4 412 1.86% 80.49% # Number of instructions fetched each cycle (Total) 86system.cpu.fetch.rateDist::5 381 1.72% 82.21% # Number of instructions fetched each cycle (Total) 87system.cpu.fetch.rateDist::6 471 2.12% 84.34% # Number of instructions fetched each cycle (Total) 88system.cpu.fetch.rateDist::7 577 2.60% 86.94% # Number of instructions fetched each cycle (Total) 89system.cpu.fetch.rateDist::8 2898 13.06% 100.00% # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 92system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.rateDist::total 22184 # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.branchRate 0.229140 # Number of branch fetches per cycle 95system.cpu.fetch.rate 1.299521 # Number of inst fetches per cycle 96system.cpu.decode.IdleCycles 30972 # Number of cycles decode is idle 97system.cpu.decode.BlockedCycles 4872 # Number of cycles decode is blocked 98system.cpu.decode.RunCycles 5207 # Number of cycles decode is running 99system.cpu.decode.UnblockCycles 530 # Number of cycles decode is unblocking 100system.cpu.decode.SquashCycles 2493 # Number of cycles decode is squashing 101system.cpu.decode.BranchResolved 640 # Number of times decode resolved a branch 102system.cpu.decode.BranchMispred 419 # Number of times decode detected a branch misprediction 103system.cpu.decode.DecodedInsts 31709 # Number of instructions handled by decode 104system.cpu.decode.SquashedInsts 698 # Number of squashed instructions handled by decode 105system.cpu.rename.SquashCycles 2493 # Number of cycles rename is squashing 106system.cpu.rename.IdleCycles 31718 # Number of cycles rename is idle 107system.cpu.rename.BlockCycles 2312 # Number of cycles rename is blocking 108system.cpu.rename.serializeStallCycles 672 # count of cycles rename stalled for serializing inst 109system.cpu.rename.RunCycles 4929 # Number of cycles rename is running 110system.cpu.rename.UnblockCycles 1950 # Number of cycles rename is unblocking 111system.cpu.rename.RenamedInsts 29261 # Number of instructions processed by rename 112system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full 113system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 114system.cpu.rename.LSQFullEvents 1965 # Number of times rename has blocked due to LSQ full 115system.cpu.rename.RenamedOperands 22098 # Number of destination operands rename has renamed 116system.cpu.rename.RenameLookups 36589 # Number of register rename lookups that rename has made 117system.cpu.rename.int_rename_lookups 36555 # Number of integer rename lookups 118system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups 119system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed 120system.cpu.rename.UndoneMaps 12932 # Number of HB maps that are undone due to squashing 121system.cpu.rename.serializingInsts 50 # count of serializing insts renamed 122system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 123system.cpu.rename.skidInsts 5419 # count of insts added to the skid buffer 124system.cpu.memDep0.insertedLoads 2664 # Number of loads inserted to the mem dependence unit. 125system.cpu.memDep0.insertedStores 1324 # Number of stores inserted to the mem dependence unit. 126system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. 127system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 128system.cpu.memDep1.insertedLoads 2650 # Number of loads inserted to the mem dependence unit. 129system.cpu.memDep1.insertedStores 1324 # Number of stores inserted to the mem dependence unit. 130system.cpu.memDep1.conflictingLoads 24 # Number of conflicting loads. 131system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. 132system.cpu.iq.iqInstsAdded 25756 # Number of instructions added to the IQ (excludes non-spec) 133system.cpu.iq.iqNonSpecInstsAdded 47 # Number of non-speculative instructions added to the IQ 134system.cpu.iq.iqInstsIssued 21797 # Number of instructions issued 135system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued 136system.cpu.iq.iqSquashedInstsExamined 11896 # Number of squashed instructions iterated over during squash; mainly for profiling 137system.cpu.iq.iqSquashedOperandsExamined 6581 # Number of squashed operands that are examined and possibly removed from graph 138system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed 139system.cpu.iq.issued_per_cycle::samples 22184 # Number of insts issued each cycle 140system.cpu.iq.issued_per_cycle::mean 0.982555 # Number of insts issued each cycle 141system.cpu.iq.issued_per_cycle::stdev 1.521995 # Number of insts issued each cycle 142system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 143system.cpu.iq.issued_per_cycle::0 13300 59.95% 59.95% # Number of insts issued each cycle 144system.cpu.iq.issued_per_cycle::1 3017 13.60% 73.55% # Number of insts issued each cycle 145system.cpu.iq.issued_per_cycle::2 2291 10.33% 83.88% # Number of insts issued each cycle 146system.cpu.iq.issued_per_cycle::3 1563 7.05% 90.93% # Number of insts issued each cycle 147system.cpu.iq.issued_per_cycle::4 1046 4.72% 95.64% # Number of insts issued each cycle 148system.cpu.iq.issued_per_cycle::5 585 2.64% 98.28% # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::6 293 1.32% 99.60% # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::7 70 0.32% 99.91% # Number of insts issued each cycle 151system.cpu.iq.issued_per_cycle::8 19 0.09% 100.00% # Number of insts issued each cycle 152system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::total 22184 # Number of insts issued each cycle 156system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 157system.cpu.iq.fu_full::IntAlu 16 8.00% 8.00% # attempts to use FU when none available 158system.cpu.iq.fu_full::IntMult 0 0.00% 8.00% # attempts to use FU when none available 159system.cpu.iq.fu_full::IntDiv 0 0.00% 8.00% # attempts to use FU when none available 160system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.00% # attempts to use FU when none available 161system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.00% # attempts to use FU when none available 162system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.00% # attempts to use FU when none available 163system.cpu.iq.fu_full::FloatMult 0 0.00% 8.00% # attempts to use FU when none available 164system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.00% # attempts to use FU when none available 165system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.00% # attempts to use FU when none available 166system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.00% # attempts to use FU when none available 167system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.00% # attempts to use FU when none available 168system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.00% # attempts to use FU when none available 169system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.00% # attempts to use FU when none available 170system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.00% # attempts to use FU when none available 171system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.00% # attempts to use FU when none available 172system.cpu.iq.fu_full::SimdMult 0 0.00% 8.00% # attempts to use FU when none available 173system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.00% # attempts to use FU when none available 174system.cpu.iq.fu_full::SimdShift 0 0.00% 8.00% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.00% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.00% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.00% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.00% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.00% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.00% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.00% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.00% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.00% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.00% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.00% # attempts to use FU when none available 186system.cpu.iq.fu_full::MemRead 115 57.50% 65.50% # attempts to use FU when none available 187system.cpu.iq.fu_full::MemWrite 69 34.50% 100.00% # attempts to use FU when none available 188system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 189system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 190system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 191system.cpu.iq.FU_type_0::IntAlu 7481 68.23% 68.24% # Type of FU issued 192system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.25% # Type of FU issued 193system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.25% # Type of FU issued 194system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.27% # Type of FU issued 195system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.27% # Type of FU issued 196system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.27% # Type of FU issued 197system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.27% # Type of FU issued 198system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.27% # Type of FU issued 199system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.27% # Type of FU issued 200system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.27% # Type of FU issued 201system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.27% # Type of FU issued 202system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.27% # Type of FU issued 203system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.27% # Type of FU issued 204system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.27% # Type of FU issued 205system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.27% # Type of FU issued 206system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.27% # Type of FU issued 207system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.27% # Type of FU issued 208system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.27% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.27% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.27% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.27% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.27% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.27% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.27% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.27% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.27% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.27% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.27% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.27% # Type of FU issued 220system.cpu.iq.FU_type_0::MemRead 2338 21.32% 89.59% # Type of FU issued 221system.cpu.iq.FU_type_0::MemWrite 1141 10.41% 100.00% # Type of FU issued 222system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 223system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 224system.cpu.iq.FU_type_0::total 10965 # Type of FU issued 225system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued 226system.cpu.iq.FU_type_1::IntAlu 7346 67.82% 67.84% # Type of FU issued 227system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.85% # Type of FU issued 228system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.85% # Type of FU issued 229system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.86% # Type of FU issued 230system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.86% # Type of FU issued 231system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.86% # Type of FU issued 232system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.86% # Type of FU issued 233system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.86% # Type of FU issued 234system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.86% # Type of FU issued 235system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.86% # Type of FU issued 236system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.86% # Type of FU issued 237system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.86% # Type of FU issued 238system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.86% # Type of FU issued 239system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.86% # Type of FU issued 240system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.86% # Type of FU issued 241system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.86% # Type of FU issued 242system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.86% # Type of FU issued 243system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.86% # Type of FU issued 244system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.86% # Type of FU issued 245system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.86% # Type of FU issued 246system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.86% # Type of FU issued 247system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.86% # Type of FU issued 248system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.86% # Type of FU issued 249system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.86% # Type of FU issued 250system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.86% # Type of FU issued 251system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.86% # Type of FU issued 252system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.86% # Type of FU issued 253system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.86% # Type of FU issued 254system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.86% # Type of FU issued 255system.cpu.iq.FU_type_1::MemRead 2331 21.52% 89.38% # Type of FU issued 256system.cpu.iq.FU_type_1::MemWrite 1150 10.62% 100.00% # Type of FU issued 257system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 258system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued 259system.cpu.iq.FU_type_1::total 10832 # Type of FU issued 260system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued 261system.cpu.iq.FU_type::IntAlu 14827 68.02% 68.04% # Type of FU issued 262system.cpu.iq.FU_type::IntMult 2 0.01% 68.05% # Type of FU issued 263system.cpu.iq.FU_type::IntDiv 0 0.00% 68.05% # Type of FU issued 264system.cpu.iq.FU_type::FloatAdd 4 0.02% 68.07% # Type of FU issued 265system.cpu.iq.FU_type::FloatCmp 0 0.00% 68.07% # Type of FU issued 266system.cpu.iq.FU_type::FloatCvt 0 0.00% 68.07% # Type of FU issued 267system.cpu.iq.FU_type::FloatMult 0 0.00% 68.07% # Type of FU issued 268system.cpu.iq.FU_type::FloatDiv 0 0.00% 68.07% # Type of FU issued 269system.cpu.iq.FU_type::FloatSqrt 0 0.00% 68.07% # Type of FU issued 270system.cpu.iq.FU_type::SimdAdd 0 0.00% 68.07% # Type of FU issued 271system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 68.07% # Type of FU issued 272system.cpu.iq.FU_type::SimdAlu 0 0.00% 68.07% # Type of FU issued 273system.cpu.iq.FU_type::SimdCmp 0 0.00% 68.07% # Type of FU issued 274system.cpu.iq.FU_type::SimdCvt 0 0.00% 68.07% # Type of FU issued 275system.cpu.iq.FU_type::SimdMisc 0 0.00% 68.07% # Type of FU issued 276system.cpu.iq.FU_type::SimdMult 0 0.00% 68.07% # Type of FU issued 277system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 68.07% # Type of FU issued 278system.cpu.iq.FU_type::SimdShift 0 0.00% 68.07% # Type of FU issued 279system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 68.07% # Type of FU issued 280system.cpu.iq.FU_type::SimdSqrt 0 0.00% 68.07% # Type of FU issued 281system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 68.07% # Type of FU issued 282system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 68.07% # Type of FU issued 283system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 68.07% # Type of FU issued 284system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 68.07% # Type of FU issued 285system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 68.07% # Type of FU issued 286system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 68.07% # Type of FU issued 287system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 68.07% # Type of FU issued 288system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued 289system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued 290system.cpu.iq.FU_type::MemRead 4669 21.42% 89.49% # Type of FU issued 291system.cpu.iq.FU_type::MemWrite 2291 10.51% 100.00% # Type of FU issued 292system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued 293system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued 294system.cpu.iq.FU_type::total 21797 # Type of FU issued 295system.cpu.iq.rate 0.779913 # Inst issue rate 296system.cpu.iq.fu_busy_cnt::0 93 # FU busy when requested 297system.cpu.iq.fu_busy_cnt::1 107 # FU busy when requested 298system.cpu.iq.fu_busy_cnt::total 200 # FU busy when requested 299system.cpu.iq.fu_busy_rate::0 0.004267 # FU busy rate (busy events/executed inst) 300system.cpu.iq.fu_busy_rate::1 0.004909 # FU busy rate (busy events/executed inst) 301system.cpu.iq.fu_busy_rate::total 0.009176 # FU busy rate (busy events/executed inst) 302system.cpu.iq.int_inst_queue_reads 66052 # Number of integer instruction queue reads 303system.cpu.iq.int_inst_queue_writes 37703 # Number of integer instruction queue writes 304system.cpu.iq.int_inst_queue_wakeup_accesses 19403 # Number of integer instruction queue wakeup accesses 305system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads 306system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 307system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses 308system.cpu.iq.int_alu_accesses 21971 # Number of integer alu accesses 309system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses 310system.cpu.iew.lsq.thread0.forwLoads 51 # Number of loads that had data forwarded from stores 311system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 312system.cpu.iew.lsq.thread0.squashedLoads 1479 # Number of loads squashed 313system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 314system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations 315system.cpu.iew.lsq.thread0.squashedStores 459 # Number of stores squashed 316system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 317system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 318system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 319system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 320system.cpu.iew.lsq.thread1.forwLoads 72 # Number of loads that had data forwarded from stores 321system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address 322system.cpu.iew.lsq.thread1.squashedLoads 1465 # Number of loads squashed 323system.cpu.iew.lsq.thread1.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed 324system.cpu.iew.lsq.thread1.memOrderViolation 19 # Number of memory ordering violations 325system.cpu.iew.lsq.thread1.squashedStores 459 # Number of stores squashed 326system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 327system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 328system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled 329system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 330system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 331system.cpu.iew.iewSquashCycles 2493 # Number of cycles IEW is squashing 332system.cpu.iew.iewBlockCycles 461 # Number of cycles IEW is blocking 333system.cpu.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking 334system.cpu.iew.iewDispatchedInsts 25944 # Number of instructions dispatched to IQ 335system.cpu.iew.iewDispSquashedInsts 945 # Number of squashed instructions skipped by dispatch 336system.cpu.iew.iewDispLoadInsts 5314 # Number of dispatched load instructions 337system.cpu.iew.iewDispStoreInsts 2648 # Number of dispatched store instructions 338system.cpu.iew.iewDispNonSpecInsts 47 # Number of dispatched non-speculative instructions 339system.cpu.iew.iewIQFullEvents 29 # Number of times the IQ has become full, causing a stall 340system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall 341system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations 342system.cpu.iew.predictedTakenIncorrect 326 # Number of branches that were predicted taken incorrectly 343system.cpu.iew.predictedNotTakenIncorrect 1247 # Number of branches that were predicted not taken incorrectly 344system.cpu.iew.branchMispredicts 1573 # Number of branch mispredicts detected at execute 345system.cpu.iew.iewExecutedInsts 20270 # Number of executed instructions 346system.cpu.iew.iewExecLoadInsts::0 2100 # Number of load instructions executed 347system.cpu.iew.iewExecLoadInsts::1 2134 # Number of load instructions executed 348system.cpu.iew.iewExecLoadInsts::total 4234 # Number of load instructions executed 349system.cpu.iew.iewExecSquashedInsts 1527 # Number of squashed instructions skipped in execute 350system.cpu.iew.exec_swp::0 0 # number of swp insts executed 351system.cpu.iew.exec_swp::1 0 # number of swp insts executed 352system.cpu.iew.exec_swp::total 0 # number of swp insts executed 353system.cpu.iew.exec_nop::0 72 # number of nop insts executed 354system.cpu.iew.exec_nop::1 69 # number of nop insts executed 355system.cpu.iew.exec_nop::total 141 # number of nop insts executed 356system.cpu.iew.exec_refs::0 3199 # number of memory reference insts executed 357system.cpu.iew.exec_refs::1 3222 # number of memory reference insts executed 358system.cpu.iew.exec_refs::total 6421 # number of memory reference insts executed 359system.cpu.iew.exec_branches::0 1640 # Number of branches executed 360system.cpu.iew.exec_branches::1 1645 # Number of branches executed 361system.cpu.iew.exec_branches::total 3285 # Number of branches executed 362system.cpu.iew.exec_stores::0 1099 # Number of stores executed 363system.cpu.iew.exec_stores::1 1088 # Number of stores executed 364system.cpu.iew.exec_stores::total 2187 # Number of stores executed 365system.cpu.iew.exec_rate 0.725276 # Inst execution rate 366system.cpu.iew.wb_sent::0 9893 # cumulative count of insts sent to commit 367system.cpu.iew.wb_sent::1 9800 # cumulative count of insts sent to commit 368system.cpu.iew.wb_sent::total 19693 # cumulative count of insts sent to commit 369system.cpu.iew.wb_count::0 9771 # cumulative count of insts written-back 370system.cpu.iew.wb_count::1 9652 # cumulative count of insts written-back 371system.cpu.iew.wb_count::total 19423 # cumulative count of insts written-back 372system.cpu.iew.wb_producers::0 5068 # num instructions producing a value 373system.cpu.iew.wb_producers::1 5042 # num instructions producing a value 374system.cpu.iew.wb_producers::total 10110 # num instructions producing a value 375system.cpu.iew.wb_consumers::0 6625 # num instructions consuming a value 376system.cpu.iew.wb_consumers::1 6584 # num instructions consuming a value 377system.cpu.iew.wb_consumers::total 13209 # num instructions consuming a value 378system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ 379system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ 380system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ 381system.cpu.iew.wb_rate::0 0.349614 # insts written-back per cycle 382system.cpu.iew.wb_rate::1 0.345356 # insts written-back per cycle 383system.cpu.iew.wb_rate::total 0.694969 # insts written-back per cycle 384system.cpu.iew.wb_fanout::0 0.764981 # average fanout of values written-back 385system.cpu.iew.wb_fanout::1 0.765796 # average fanout of values written-back 386system.cpu.iew.wb_fanout::total 1.530777 # average fanout of values written-back 387system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ 388system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ 389system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ 390system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions 391system.cpu.commit.commitCommittedOps 12807 # The number of committed instructions 392system.cpu.commit.commitSquashedInsts 13040 # The number of squashed insts skipped by commit 393system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards 394system.cpu.commit.branchMispredicts 1358 # The number of times a branch was mispredicted 395system.cpu.commit.committed_per_cycle::samples 22111 # Number of insts commited each cycle 396system.cpu.commit.committed_per_cycle::mean 0.579214 # Number of insts commited each cycle 397system.cpu.commit.committed_per_cycle::stdev 1.379258 # Number of insts commited each cycle 398system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 399system.cpu.commit.committed_per_cycle::0 16588 75.02% 75.02% # Number of insts commited each cycle 400system.cpu.commit.committed_per_cycle::1 2733 12.36% 87.38% # Number of insts commited each cycle 401system.cpu.commit.committed_per_cycle::2 1194 5.40% 92.78% # Number of insts commited each cycle 402system.cpu.commit.committed_per_cycle::3 519 2.35% 95.13% # Number of insts commited each cycle 403system.cpu.commit.committed_per_cycle::4 313 1.42% 96.54% # Number of insts commited each cycle 404system.cpu.commit.committed_per_cycle::5 257 1.16% 97.71% # Number of insts commited each cycle 405system.cpu.commit.committed_per_cycle::6 189 0.85% 98.56% # Number of insts commited each cycle 406system.cpu.commit.committed_per_cycle::7 86 0.39% 98.95% # Number of insts commited each cycle 407system.cpu.commit.committed_per_cycle::8 232 1.05% 100.00% # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::total 22111 # Number of insts commited each cycle 412system.cpu.commit.committedInsts::0 6403 # Number of instructions committed 413system.cpu.commit.committedInsts::1 6404 # Number of instructions committed 414system.cpu.commit.committedInsts::total 12807 # Number of instructions committed 415system.cpu.commit.committedOps::0 6403 # Number of ops (including micro ops) committed 416system.cpu.commit.committedOps::1 6404 # Number of ops (including micro ops) committed 417system.cpu.commit.committedOps::total 12807 # Number of ops (including micro ops) committed 418system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 419system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed 420system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed 421system.cpu.commit.refs::0 2050 # Number of memory references committed 422system.cpu.commit.refs::1 2050 # Number of memory references committed 423system.cpu.commit.refs::total 4100 # Number of memory references committed 424system.cpu.commit.loads::0 1185 # Number of loads committed 425system.cpu.commit.loads::1 1185 # Number of loads committed 426system.cpu.commit.loads::total 2370 # Number of loads committed 427system.cpu.commit.membars::0 0 # Number of memory barriers committed 428system.cpu.commit.membars::1 0 # Number of memory barriers committed 429system.cpu.commit.membars::total 0 # Number of memory barriers committed 430system.cpu.commit.branches::0 1051 # Number of branches committed 431system.cpu.commit.branches::1 1051 # Number of branches committed 432system.cpu.commit.branches::total 2102 # Number of branches committed 433system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. 434system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. 435system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. 436system.cpu.commit.int_insts::0 6321 # Number of committed integer instructions. 437system.cpu.commit.int_insts::1 6321 # Number of committed integer instructions. 438system.cpu.commit.int_insts::total 12642 # Number of committed integer instructions. 439system.cpu.commit.function_calls::0 127 # Number of function calls committed. 440system.cpu.commit.function_calls::1 127 # Number of function calls committed. 441system.cpu.commit.function_calls::total 254 # Number of function calls committed. 442system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached 443system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits 444system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits 445system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits 446system.cpu.rob.rob_reads 114163 # The number of ROB reads 447system.cpu.rob.rob_writes 54209 # The number of ROB writes 448system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself 449system.cpu.idleCycles 5764 # Total number of cycles that the CPU has spent unscheduled due to idling 450system.cpu.committedInsts::0 6386 # Number of Instructions Simulated 451system.cpu.committedInsts::1 6387 # Number of Instructions Simulated 452system.cpu.committedOps::0 6386 # Number of Ops (including micro ops) Simulated 453system.cpu.committedOps::1 6387 # Number of Ops (including micro ops) Simulated 454system.cpu.committedInsts_total 12773 # Number of Instructions Simulated 455system.cpu.cpi::0 4.376448 # CPI: Cycles Per Instruction 456system.cpu.cpi::1 4.375763 # CPI: Cycles Per Instruction 457system.cpu.cpi_total 2.188053 # CPI: Total CPI of All Threads 458system.cpu.ipc::0 0.228496 # IPC: Instructions Per Cycle 459system.cpu.ipc::1 0.228532 # IPC: Instructions Per Cycle 460system.cpu.ipc_total 0.457027 # IPC: Total IPC of All Threads 461system.cpu.int_regfile_reads 25651 # number of integer regfile reads 462system.cpu.int_regfile_writes 14680 # number of integer regfile writes 463system.cpu.fp_regfile_reads 16 # number of floating regfile reads 464system.cpu.fp_regfile_writes 4 # number of floating regfile writes 465system.cpu.misc_regfile_reads 2 # number of misc regfile reads 466system.cpu.misc_regfile_writes 2 # number of misc regfile writes 467system.cpu.icache.replacements::0 7 # number of replacements 468system.cpu.icache.replacements::1 0 # number of replacements 469system.cpu.icache.replacements::total 7 # number of replacements 470system.cpu.icache.tagsinuse 324.653687 # Cycle average of tags in use 471system.cpu.icache.total_refs 4369 # Total number of references to valid blocks. 472system.cpu.icache.sampled_refs 631 # Sample count of references to valid blocks. 473system.cpu.icache.avg_refs 6.923930 # Average number of references to valid blocks. 474system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 475system.cpu.icache.occ_blocks::cpu.inst 324.653687 # Average occupied blocks per requestor 476system.cpu.icache.occ_percent::cpu.inst 0.158522 # Average percentage of cache occupancy 477system.cpu.icache.occ_percent::total 0.158522 # Average percentage of cache occupancy 478system.cpu.icache.ReadReq_hits::cpu.inst 4369 # number of ReadReq hits 479system.cpu.icache.ReadReq_hits::total 4369 # number of ReadReq hits 480system.cpu.icache.demand_hits::cpu.inst 4369 # number of demand (read+write) hits 481system.cpu.icache.demand_hits::total 4369 # number of demand (read+write) hits 482system.cpu.icache.overall_hits::cpu.inst 4369 # number of overall hits 483system.cpu.icache.overall_hits::total 4369 # number of overall hits 484system.cpu.icache.ReadReq_misses::cpu.inst 893 # number of ReadReq misses 485system.cpu.icache.ReadReq_misses::total 893 # number of ReadReq misses 486system.cpu.icache.demand_misses::cpu.inst 893 # number of demand (read+write) misses 487system.cpu.icache.demand_misses::total 893 # number of demand (read+write) misses 488system.cpu.icache.overall_misses::cpu.inst 893 # number of overall misses 489system.cpu.icache.overall_misses::total 893 # number of overall misses 490system.cpu.icache.ReadReq_miss_latency::cpu.inst 31736000 # number of ReadReq miss cycles 491system.cpu.icache.ReadReq_miss_latency::total 31736000 # number of ReadReq miss cycles 492system.cpu.icache.demand_miss_latency::cpu.inst 31736000 # number of demand (read+write) miss cycles 493system.cpu.icache.demand_miss_latency::total 31736000 # number of demand (read+write) miss cycles 494system.cpu.icache.overall_miss_latency::cpu.inst 31736000 # number of overall miss cycles 495system.cpu.icache.overall_miss_latency::total 31736000 # number of overall miss cycles 496system.cpu.icache.ReadReq_accesses::cpu.inst 5262 # number of ReadReq accesses(hits+misses) 497system.cpu.icache.ReadReq_accesses::total 5262 # number of ReadReq accesses(hits+misses) 498system.cpu.icache.demand_accesses::cpu.inst 5262 # number of demand (read+write) accesses 499system.cpu.icache.demand_accesses::total 5262 # number of demand (read+write) accesses 500system.cpu.icache.overall_accesses::cpu.inst 5262 # number of overall (read+write) accesses 501system.cpu.icache.overall_accesses::total 5262 # number of overall (read+write) accesses 502system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169707 # miss rate for ReadReq accesses 503system.cpu.icache.demand_miss_rate::cpu.inst 0.169707 # miss rate for demand accesses 504system.cpu.icache.overall_miss_rate::cpu.inst 0.169707 # miss rate for overall accesses 505system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35538.633819 # average ReadReq miss latency 506system.cpu.icache.demand_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency 507system.cpu.icache.overall_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency 508system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 509system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 510system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 511system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 512system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 513system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 514system.cpu.icache.fast_writes 0 # number of fast writes performed 515system.cpu.icache.cache_copies 0 # number of cache copies performed 516system.cpu.icache.ReadReq_mshr_hits::cpu.inst 262 # number of ReadReq MSHR hits 517system.cpu.icache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits 518system.cpu.icache.demand_mshr_hits::cpu.inst 262 # number of demand (read+write) MSHR hits 519system.cpu.icache.demand_mshr_hits::total 262 # number of demand (read+write) MSHR hits 520system.cpu.icache.overall_mshr_hits::cpu.inst 262 # number of overall MSHR hits 521system.cpu.icache.overall_mshr_hits::total 262 # number of overall MSHR hits 522system.cpu.icache.ReadReq_mshr_misses::cpu.inst 631 # number of ReadReq MSHR misses 523system.cpu.icache.ReadReq_mshr_misses::total 631 # number of ReadReq MSHR misses 524system.cpu.icache.demand_mshr_misses::cpu.inst 631 # number of demand (read+write) MSHR misses 525system.cpu.icache.demand_mshr_misses::total 631 # number of demand (read+write) MSHR misses 526system.cpu.icache.overall_mshr_misses::cpu.inst 631 # number of overall MSHR misses 527system.cpu.icache.overall_mshr_misses::total 631 # number of overall MSHR misses 528system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22442500 # number of ReadReq MSHR miss cycles 529system.cpu.icache.ReadReq_mshr_miss_latency::total 22442500 # number of ReadReq MSHR miss cycles 530system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22442500 # number of demand (read+write) MSHR miss cycles 531system.cpu.icache.demand_mshr_miss_latency::total 22442500 # number of demand (read+write) MSHR miss cycles 532system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22442500 # number of overall MSHR miss cycles 533system.cpu.icache.overall_mshr_miss_latency::total 22442500 # number of overall MSHR miss cycles 534system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for ReadReq accesses 535system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for demand accesses 536system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for overall accesses 537system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35566.561014 # average ReadReq mshr miss latency 538system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency 539system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency 540system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 541system.cpu.dcache.replacements::0 0 # number of replacements 542system.cpu.dcache.replacements::1 0 # number of replacements 543system.cpu.dcache.replacements::total 0 # number of replacements 544system.cpu.dcache.tagsinuse 221.504894 # Cycle average of tags in use 545system.cpu.dcache.total_refs 4696 # Total number of references to valid blocks. 546system.cpu.dcache.sampled_refs 353 # Sample count of references to valid blocks. 547system.cpu.dcache.avg_refs 13.303116 # Average number of references to valid blocks. 548system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 549system.cpu.dcache.occ_blocks::cpu.data 221.504894 # Average occupied blocks per requestor 550system.cpu.dcache.occ_percent::cpu.data 0.054078 # Average percentage of cache occupancy 551system.cpu.dcache.occ_percent::total 0.054078 # Average percentage of cache occupancy 552system.cpu.dcache.ReadReq_hits::cpu.data 3676 # number of ReadReq hits 553system.cpu.dcache.ReadReq_hits::total 3676 # number of ReadReq hits 554system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits 555system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits 556system.cpu.dcache.demand_hits::cpu.data 4696 # number of demand (read+write) hits 557system.cpu.dcache.demand_hits::total 4696 # number of demand (read+write) hits 558system.cpu.dcache.overall_hits::cpu.data 4696 # number of overall hits 559system.cpu.dcache.overall_hits::total 4696 # number of overall hits 560system.cpu.dcache.ReadReq_misses::cpu.data 311 # number of ReadReq misses 561system.cpu.dcache.ReadReq_misses::total 311 # number of ReadReq misses 562system.cpu.dcache.WriteReq_misses::cpu.data 710 # number of WriteReq misses 563system.cpu.dcache.WriteReq_misses::total 710 # number of WriteReq misses 564system.cpu.dcache.demand_misses::cpu.data 1021 # number of demand (read+write) misses 565system.cpu.dcache.demand_misses::total 1021 # number of demand (read+write) misses 566system.cpu.dcache.overall_misses::cpu.data 1021 # number of overall misses 567system.cpu.dcache.overall_misses::total 1021 # number of overall misses 568system.cpu.dcache.ReadReq_miss_latency::cpu.data 11221000 # number of ReadReq miss cycles 569system.cpu.dcache.ReadReq_miss_latency::total 11221000 # number of ReadReq miss cycles 570system.cpu.dcache.WriteReq_miss_latency::cpu.data 22533500 # number of WriteReq miss cycles 571system.cpu.dcache.WriteReq_miss_latency::total 22533500 # number of WriteReq miss cycles 572system.cpu.dcache.demand_miss_latency::cpu.data 33754500 # number of demand (read+write) miss cycles 573system.cpu.dcache.demand_miss_latency::total 33754500 # number of demand (read+write) miss cycles 574system.cpu.dcache.overall_miss_latency::cpu.data 33754500 # number of overall miss cycles 575system.cpu.dcache.overall_miss_latency::total 33754500 # number of overall miss cycles 576system.cpu.dcache.ReadReq_accesses::cpu.data 3987 # number of ReadReq accesses(hits+misses) 577system.cpu.dcache.ReadReq_accesses::total 3987 # number of ReadReq accesses(hits+misses) 578system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) 579system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) 580system.cpu.dcache.demand_accesses::cpu.data 5717 # number of demand (read+write) accesses 581system.cpu.dcache.demand_accesses::total 5717 # number of demand (read+write) accesses 582system.cpu.dcache.overall_accesses::cpu.data 5717 # number of overall (read+write) accesses 583system.cpu.dcache.overall_accesses::total 5717 # number of overall (read+write) accesses 584system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078004 # miss rate for ReadReq accesses 585system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.410405 # miss rate for WriteReq accesses 586system.cpu.dcache.demand_miss_rate::cpu.data 0.178590 # miss rate for demand accesses 587system.cpu.dcache.overall_miss_rate::cpu.data 0.178590 # miss rate for overall accesses 588system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36080.385852 # average ReadReq miss latency 589system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31737.323944 # average WriteReq miss latency 590system.cpu.dcache.demand_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency 591system.cpu.dcache.overall_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency 592system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 593system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 594system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 595system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 596system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 597system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 598system.cpu.dcache.fast_writes 0 # number of fast writes performed 599system.cpu.dcache.cache_copies 0 # number of cache copies performed 600system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104 # number of ReadReq MSHR hits 601system.cpu.dcache.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits 602system.cpu.dcache.WriteReq_mshr_hits::cpu.data 564 # number of WriteReq MSHR hits 603system.cpu.dcache.WriteReq_mshr_hits::total 564 # number of WriteReq MSHR hits 604system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits 605system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits 606system.cpu.dcache.overall_mshr_hits::cpu.data 668 # number of overall MSHR hits 607system.cpu.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits 608system.cpu.dcache.ReadReq_mshr_misses::cpu.data 207 # number of ReadReq MSHR misses 609system.cpu.dcache.ReadReq_mshr_misses::total 207 # number of ReadReq MSHR misses 610system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses 611system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses 612system.cpu.dcache.demand_mshr_misses::cpu.data 353 # number of demand (read+write) MSHR misses 613system.cpu.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses 614system.cpu.dcache.overall_mshr_misses::cpu.data 353 # number of overall MSHR misses 615system.cpu.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses 616system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7607500 # number of ReadReq MSHR miss cycles 617system.cpu.dcache.ReadReq_mshr_miss_latency::total 7607500 # number of ReadReq MSHR miss cycles 618system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5291500 # number of WriteReq MSHR miss cycles 619system.cpu.dcache.WriteReq_mshr_miss_latency::total 5291500 # number of WriteReq MSHR miss cycles 620system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12899000 # number of demand (read+write) MSHR miss cycles 621system.cpu.dcache.demand_mshr_miss_latency::total 12899000 # number of demand (read+write) MSHR miss cycles 622system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12899000 # number of overall MSHR miss cycles 623system.cpu.dcache.overall_mshr_miss_latency::total 12899000 # number of overall MSHR miss cycles 624system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051919 # mshr miss rate for ReadReq accesses 625system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 626system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for demand accesses 627system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for overall accesses 628system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36751.207729 # average ReadReq mshr miss latency 629system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36243.150685 # average WriteReq mshr miss latency 630system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency 631system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency 632system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 633system.cpu.l2cache.replacements::0 0 # number of replacements 634system.cpu.l2cache.replacements::1 0 # number of replacements 635system.cpu.l2cache.replacements::total 0 # number of replacements 636system.cpu.l2cache.tagsinuse 449.601344 # Cycle average of tags in use 637system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 638system.cpu.l2cache.sampled_refs 835 # Sample count of references to valid blocks. 639system.cpu.l2cache.avg_refs 0.003593 # Average number of references to valid blocks. 640system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 641system.cpu.l2cache.occ_blocks::cpu.inst 324.972112 # Average occupied blocks per requestor 642system.cpu.l2cache.occ_blocks::cpu.data 124.629233 # Average occupied blocks per requestor 643system.cpu.l2cache.occ_percent::cpu.inst 0.009917 # Average percentage of cache occupancy 644system.cpu.l2cache.occ_percent::cpu.data 0.003803 # Average percentage of cache occupancy 645system.cpu.l2cache.occ_percent::total 0.013721 # Average percentage of cache occupancy 646system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 647system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 648system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 649system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 650system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 651system.cpu.l2cache.overall_hits::total 3 # number of overall hits 652system.cpu.l2cache.ReadReq_misses::cpu.inst 628 # number of ReadReq misses 653system.cpu.l2cache.ReadReq_misses::cpu.data 207 # number of ReadReq misses 654system.cpu.l2cache.ReadReq_misses::total 835 # number of ReadReq misses 655system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses 656system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses 657system.cpu.l2cache.demand_misses::cpu.inst 628 # number of demand (read+write) misses 658system.cpu.l2cache.demand_misses::cpu.data 353 # number of demand (read+write) misses 659system.cpu.l2cache.demand_misses::total 981 # number of demand (read+write) misses 660system.cpu.l2cache.overall_misses::cpu.inst 628 # number of overall misses 661system.cpu.l2cache.overall_misses::cpu.data 353 # number of overall misses 662system.cpu.l2cache.overall_misses::total 981 # number of overall misses 663system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21636000 # number of ReadReq miss cycles 664system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7216000 # number of ReadReq miss cycles 665system.cpu.l2cache.ReadReq_miss_latency::total 28852000 # number of ReadReq miss cycles 666system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5063500 # number of ReadExReq miss cycles 667system.cpu.l2cache.ReadExReq_miss_latency::total 5063500 # number of ReadExReq miss cycles 668system.cpu.l2cache.demand_miss_latency::cpu.inst 21636000 # number of demand (read+write) miss cycles 669system.cpu.l2cache.demand_miss_latency::cpu.data 12279500 # number of demand (read+write) miss cycles 670system.cpu.l2cache.demand_miss_latency::total 33915500 # number of demand (read+write) miss cycles 671system.cpu.l2cache.overall_miss_latency::cpu.inst 21636000 # number of overall miss cycles 672system.cpu.l2cache.overall_miss_latency::cpu.data 12279500 # number of overall miss cycles 673system.cpu.l2cache.overall_miss_latency::total 33915500 # number of overall miss cycles 674system.cpu.l2cache.ReadReq_accesses::cpu.inst 631 # number of ReadReq accesses(hits+misses) 675system.cpu.l2cache.ReadReq_accesses::cpu.data 207 # number of ReadReq accesses(hits+misses) 676system.cpu.l2cache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) 677system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) 678system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) 679system.cpu.l2cache.demand_accesses::cpu.inst 631 # number of demand (read+write) accesses 680system.cpu.l2cache.demand_accesses::cpu.data 353 # number of demand (read+write) accesses 681system.cpu.l2cache.demand_accesses::total 984 # number of demand (read+write) accesses 682system.cpu.l2cache.overall_accesses::cpu.inst 631 # number of overall (read+write) accesses 683system.cpu.l2cache.overall_accesses::cpu.data 353 # number of overall (read+write) accesses 684system.cpu.l2cache.overall_accesses::total 984 # number of overall (read+write) accesses 685system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995246 # miss rate for ReadReq accesses 686system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 687system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 688system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995246 # miss rate for demand accesses 689system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 690system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995246 # miss rate for overall accesses 691system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 692system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34452.229299 # average ReadReq miss latency 693system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34859.903382 # average ReadReq miss latency 694system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34681.506849 # average ReadExReq miss latency 695system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency 696system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency 697system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency 698system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency 699system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked 700system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 701system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked 702system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 703system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5250 # average number of cycles each access was blocked 704system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 705system.cpu.l2cache.fast_writes 0 # number of fast writes performed 706system.cpu.l2cache.cache_copies 0 # number of cache copies performed 707system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 628 # number of ReadReq MSHR misses 708system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 207 # number of ReadReq MSHR misses 709system.cpu.l2cache.ReadReq_mshr_misses::total 835 # number of ReadReq MSHR misses 710system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses 711system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses 712system.cpu.l2cache.demand_mshr_misses::cpu.inst 628 # number of demand (read+write) MSHR misses 713system.cpu.l2cache.demand_mshr_misses::cpu.data 353 # number of demand (read+write) MSHR misses 714system.cpu.l2cache.demand_mshr_misses::total 981 # number of demand (read+write) MSHR misses 715system.cpu.l2cache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses 716system.cpu.l2cache.overall_mshr_misses::cpu.data 353 # number of overall MSHR misses 717system.cpu.l2cache.overall_mshr_misses::total 981 # number of overall MSHR misses 718system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19659500 # number of ReadReq MSHR miss cycles 719system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6570000 # number of ReadReq MSHR miss cycles 720system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26229500 # number of ReadReq MSHR miss cycles 721system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4611000 # number of ReadExReq MSHR miss cycles 722system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4611000 # number of ReadExReq MSHR miss cycles 723system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19659500 # number of demand (read+write) MSHR miss cycles 724system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11181000 # number of demand (read+write) MSHR miss cycles 725system.cpu.l2cache.demand_mshr_miss_latency::total 30840500 # number of demand (read+write) MSHR miss cycles 726system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19659500 # number of overall MSHR miss cycles 727system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11181000 # number of overall MSHR miss cycles 728system.cpu.l2cache.overall_mshr_miss_latency::total 30840500 # number of overall MSHR miss cycles 729system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for ReadReq accesses 730system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 731system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 732system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for demand accesses 733system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 734system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for overall accesses 735system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 736system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31304.936306 # average ReadReq mshr miss latency 737system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31739.130435 # average ReadReq mshr miss latency 738system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.191781 # average ReadExReq mshr miss latency 739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency 740system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency 742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency 743system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 744 745---------- End Simulation Statistics ---------- 746