stats.txt revision 8835
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000013 # Number of seconds simulated 4sim_ticks 13202000 # Number of ticks simulated 5final_tick 13202000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 91406 # Simulator instruction rate (inst/s) 8host_op_rate 91394 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 94452628 # Simulator tick rate (ticks/s) 10host_mem_usage 210624 # Number of bytes of host memory used 11host_seconds 0.14 # Real time elapsed on the host 12sim_insts 12773 # Number of instructions simulated 13sim_ops 12773 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 62144 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 39936 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 971 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 4707165581 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 3024996213 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 4707165581 # Total bandwidth to/from this memory (bytes/s) 23system.cpu.dtb.fetch_hits 0 # ITB hits 24system.cpu.dtb.fetch_misses 0 # ITB misses 25system.cpu.dtb.fetch_acv 0 # ITB acv 26system.cpu.dtb.fetch_accesses 0 # ITB accesses 27system.cpu.dtb.read_hits 3722 # DTB read hits 28system.cpu.dtb.read_misses 94 # DTB read misses 29system.cpu.dtb.read_acv 0 # DTB read access violations 30system.cpu.dtb.read_accesses 3816 # DTB read accesses 31system.cpu.dtb.write_hits 1984 # DTB write hits 32system.cpu.dtb.write_misses 61 # DTB write misses 33system.cpu.dtb.write_acv 0 # DTB write access violations 34system.cpu.dtb.write_accesses 2045 # DTB write accesses 35system.cpu.dtb.data_hits 5706 # DTB hits 36system.cpu.dtb.data_misses 155 # DTB misses 37system.cpu.dtb.data_acv 0 # DTB access violations 38system.cpu.dtb.data_accesses 5861 # DTB accesses 39system.cpu.itb.fetch_hits 4091 # ITB hits 40system.cpu.itb.fetch_misses 56 # ITB misses 41system.cpu.itb.fetch_acv 0 # ITB acv 42system.cpu.itb.fetch_accesses 4147 # ITB accesses 43system.cpu.itb.read_hits 0 # DTB read hits 44system.cpu.itb.read_misses 0 # DTB read misses 45system.cpu.itb.read_acv 0 # DTB read access violations 46system.cpu.itb.read_accesses 0 # DTB read accesses 47system.cpu.itb.write_hits 0 # DTB write hits 48system.cpu.itb.write_misses 0 # DTB write misses 49system.cpu.itb.write_acv 0 # DTB write access violations 50system.cpu.itb.write_accesses 0 # DTB write accesses 51system.cpu.itb.data_hits 0 # DTB hits 52system.cpu.itb.data_misses 0 # DTB misses 53system.cpu.itb.data_acv 0 # DTB access violations 54system.cpu.itb.data_accesses 0 # DTB accesses 55system.cpu.workload0.num_syscalls 17 # Number of system calls 56system.cpu.workload1.num_syscalls 17 # Number of system calls 57system.cpu.numCycles 26405 # number of cpu cycles simulated 58system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 59system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 60system.cpu.BPredUnit.lookups 5174 # Number of BP lookups 61system.cpu.BPredUnit.condPredicted 2964 # Number of conditional branches predicted 62system.cpu.BPredUnit.condIncorrect 1252 # Number of conditional branches incorrect 63system.cpu.BPredUnit.BTBLookups 3548 # Number of BTB lookups 64system.cpu.BPredUnit.BTBHits 1004 # Number of BTB hits 65system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 66system.cpu.BPredUnit.usedRAS 734 # Number of times the RAS was used to get a target. 67system.cpu.BPredUnit.RASInCorrect 158 # Number of incorrect RAS predictions. 68system.cpu.fetch.icacheStallCycles 1115 # Number of cycles fetch is stalled on an Icache miss 69system.cpu.fetch.Insts 28962 # Number of instructions fetch has processed 70system.cpu.fetch.Branches 5174 # Number of branches that fetch encountered 71system.cpu.fetch.predictedBranches 1738 # Number of branches that fetch has predicted taken 72system.cpu.fetch.Cycles 4987 # Number of cycles fetch has run and was not squashing or blocked 73system.cpu.fetch.SquashCycles 1325 # Number of cycles fetch has spent squashing 74system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 75system.cpu.fetch.CacheLines 4091 # Number of cache lines fetched 76system.cpu.fetch.IcacheSquashes 637 # Number of outstanding Icache misses that were squashed 77system.cpu.fetch.rateDist::samples 20201 # Number of instructions fetched each cycle (Total) 78system.cpu.fetch.rateDist::mean 1.433691 # Number of instructions fetched each cycle (Total) 79system.cpu.fetch.rateDist::stdev 2.801868 # Number of instructions fetched each cycle (Total) 80system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 81system.cpu.fetch.rateDist::0 15214 75.31% 75.31% # Number of instructions fetched each cycle (Total) 82system.cpu.fetch.rateDist::1 449 2.22% 77.54% # Number of instructions fetched each cycle (Total) 83system.cpu.fetch.rateDist::2 365 1.81% 79.34% # Number of instructions fetched each cycle (Total) 84system.cpu.fetch.rateDist::3 384 1.90% 81.24% # Number of instructions fetched each cycle (Total) 85system.cpu.fetch.rateDist::4 390 1.93% 83.17% # Number of instructions fetched each cycle (Total) 86system.cpu.fetch.rateDist::5 328 1.62% 84.80% # Number of instructions fetched each cycle (Total) 87system.cpu.fetch.rateDist::6 404 2.00% 86.80% # Number of instructions fetched each cycle (Total) 88system.cpu.fetch.rateDist::7 329 1.63% 88.43% # Number of instructions fetched each cycle (Total) 89system.cpu.fetch.rateDist::8 2338 11.57% 100.00% # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 92system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.rateDist::total 20201 # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.branchRate 0.195948 # Number of branch fetches per cycle 95system.cpu.fetch.rate 1.096838 # Number of inst fetches per cycle 96system.cpu.decode.IdleCycles 27985 # Number of cycles decode is idle 97system.cpu.decode.BlockedCycles 5533 # Number of cycles decode is blocked 98system.cpu.decode.RunCycles 4328 # Number of cycles decode is running 99system.cpu.decode.UnblockCycles 445 # Number of cycles decode is unblocking 100system.cpu.decode.SquashCycles 1869 # Number of cycles decode is squashing 101system.cpu.decode.BranchResolved 485 # Number of times decode resolved a branch 102system.cpu.decode.BranchMispred 315 # Number of times decode detected a branch misprediction 103system.cpu.decode.DecodedInsts 25962 # Number of instructions handled by decode 104system.cpu.decode.SquashedInsts 512 # Number of squashed instructions handled by decode 105system.cpu.rename.SquashCycles 1869 # Number of cycles rename is squashing 106system.cpu.rename.IdleCycles 28534 # Number of cycles rename is idle 107system.cpu.rename.BlockCycles 2990 # Number of cycles rename is blocking 108system.cpu.rename.serializeStallCycles 752 # count of cycles rename stalled for serializing inst 109system.cpu.rename.RunCycles 4136 # Number of cycles rename is running 110system.cpu.rename.UnblockCycles 1879 # Number of cycles rename is unblocking 111system.cpu.rename.RenamedInsts 24542 # Number of instructions processed by rename 112system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full 113system.cpu.rename.LSQFullEvents 1739 # Number of times rename has blocked due to LSQ full 114system.cpu.rename.RenamedOperands 18358 # Number of destination operands rename has renamed 115system.cpu.rename.RenameLookups 30575 # Number of register rename lookups that rename has made 116system.cpu.rename.int_rename_lookups 30541 # Number of integer rename lookups 117system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups 118system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed 119system.cpu.rename.UndoneMaps 9192 # Number of HB maps that are undone due to squashing 120system.cpu.rename.serializingInsts 52 # count of serializing insts renamed 121system.cpu.rename.tempSerializingInsts 40 # count of temporary serializing insts renamed 122system.cpu.rename.skidInsts 4646 # count of insts added to the skid buffer 123system.cpu.memDep0.insertedLoads 2308 # Number of loads inserted to the mem dependence unit. 124system.cpu.memDep0.insertedStores 1190 # Number of stores inserted to the mem dependence unit. 125system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 126system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 127system.cpu.memDep1.insertedLoads 2319 # Number of loads inserted to the mem dependence unit. 128system.cpu.memDep1.insertedStores 1181 # Number of stores inserted to the mem dependence unit. 129system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads. 130system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. 131system.cpu.iq.iqInstsAdded 22288 # Number of instructions added to the IQ (excludes non-spec) 132system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 133system.cpu.iq.iqInstsIssued 19435 # Number of instructions issued 134system.cpu.iq.iqSquashedInstsIssued 67 # Number of squashed instructions issued 135system.cpu.iq.iqSquashedInstsExamined 8694 # Number of squashed instructions iterated over during squash; mainly for profiling 136system.cpu.iq.iqSquashedOperandsExamined 4709 # Number of squashed operands that are examined and possibly removed from graph 137system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed 138system.cpu.iq.issued_per_cycle::samples 20201 # Number of insts issued each cycle 139system.cpu.iq.issued_per_cycle::mean 0.962081 # Number of insts issued each cycle 140system.cpu.iq.issued_per_cycle::stdev 1.481018 # Number of insts issued each cycle 141system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 142system.cpu.iq.issued_per_cycle::0 11990 59.35% 59.35% # Number of insts issued each cycle 143system.cpu.iq.issued_per_cycle::1 2928 14.49% 73.85% # Number of insts issued each cycle 144system.cpu.iq.issued_per_cycle::2 2232 11.05% 84.90% # Number of insts issued each cycle 145system.cpu.iq.issued_per_cycle::3 1366 6.76% 91.66% # Number of insts issued each cycle 146system.cpu.iq.issued_per_cycle::4 891 4.41% 96.07% # Number of insts issued each cycle 147system.cpu.iq.issued_per_cycle::5 479 2.37% 98.44% # Number of insts issued each cycle 148system.cpu.iq.issued_per_cycle::6 237 1.17% 99.61% # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::7 60 0.30% 99.91% # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::8 18 0.09% 100.00% # Number of insts issued each cycle 151system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 152system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::total 20201 # Number of insts issued each cycle 155system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 156system.cpu.iq.fu_full::IntAlu 9 4.92% 4.92% # attempts to use FU when none available 157system.cpu.iq.fu_full::IntMult 0 0.00% 4.92% # attempts to use FU when none available 158system.cpu.iq.fu_full::IntDiv 0 0.00% 4.92% # attempts to use FU when none available 159system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.92% # attempts to use FU when none available 160system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.92% # attempts to use FU when none available 161system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.92% # attempts to use FU when none available 162system.cpu.iq.fu_full::FloatMult 0 0.00% 4.92% # attempts to use FU when none available 163system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.92% # attempts to use FU when none available 164system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.92% # attempts to use FU when none available 165system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.92% # attempts to use FU when none available 166system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.92% # attempts to use FU when none available 167system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.92% # attempts to use FU when none available 168system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.92% # attempts to use FU when none available 169system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.92% # attempts to use FU when none available 170system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.92% # attempts to use FU when none available 171system.cpu.iq.fu_full::SimdMult 0 0.00% 4.92% # attempts to use FU when none available 172system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.92% # attempts to use FU when none available 173system.cpu.iq.fu_full::SimdShift 0 0.00% 4.92% # attempts to use FU when none available 174system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.92% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.92% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.92% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.92% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.92% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.92% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.92% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.92% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.92% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.92% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.92% # attempts to use FU when none available 185system.cpu.iq.fu_full::MemRead 106 57.92% 62.84% # attempts to use FU when none available 186system.cpu.iq.fu_full::MemWrite 68 37.16% 100.00% # attempts to use FU when none available 187system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 188system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 189system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 190system.cpu.iq.FU_type_0::IntAlu 6617 67.89% 67.91% # Type of FU issued 191system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.92% # Type of FU issued 192system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.92% # Type of FU issued 193system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.94% # Type of FU issued 194system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.94% # Type of FU issued 195system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.94% # Type of FU issued 196system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.94% # Type of FU issued 197system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.94% # Type of FU issued 198system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.94% # Type of FU issued 199system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.94% # Type of FU issued 200system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.94% # Type of FU issued 201system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.94% # Type of FU issued 202system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.94% # Type of FU issued 203system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.94% # Type of FU issued 204system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.94% # Type of FU issued 205system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.94% # Type of FU issued 206system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.94% # Type of FU issued 207system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.94% # Type of FU issued 208system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.94% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.94% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.94% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.94% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.94% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.94% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.94% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.94% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.94% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.94% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.94% # Type of FU issued 219system.cpu.iq.FU_type_0::MemRead 2056 21.09% 89.03% # Type of FU issued 220system.cpu.iq.FU_type_0::MemWrite 1069 10.97% 100.00% # Type of FU issued 221system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 222system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 223system.cpu.iq.FU_type_0::total 9747 # Type of FU issued 224system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued 225system.cpu.iq.FU_type_1::IntAlu 6565 67.76% 67.78% # Type of FU issued 226system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.80% # Type of FU issued 227system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.80% # Type of FU issued 228system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.82% # Type of FU issued 229system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.82% # Type of FU issued 230system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.82% # Type of FU issued 231system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.82% # Type of FU issued 232system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.82% # Type of FU issued 233system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.82% # Type of FU issued 234system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.82% # Type of FU issued 235system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.82% # Type of FU issued 236system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.82% # Type of FU issued 237system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.82% # Type of FU issued 238system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.82% # Type of FU issued 239system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.82% # Type of FU issued 240system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.82% # Type of FU issued 241system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.82% # Type of FU issued 242system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.82% # Type of FU issued 243system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued 244system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.82% # Type of FU issued 245system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued 246system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued 247system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued 248system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued 249system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued 250system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.82% # Type of FU issued 251system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.82% # Type of FU issued 252system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued 253system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued 254system.cpu.iq.FU_type_1::MemRead 2046 21.12% 88.93% # Type of FU issued 255system.cpu.iq.FU_type_1::MemWrite 1072 11.07% 100.00% # Type of FU issued 256system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 257system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued 258system.cpu.iq.FU_type_1::total 9688 # Type of FU issued 259system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued 260system.cpu.iq.FU_type::IntAlu 13182 67.83% 67.85% # Type of FU issued 261system.cpu.iq.FU_type::IntMult 2 0.01% 67.86% # Type of FU issued 262system.cpu.iq.FU_type::IntDiv 0 0.00% 67.86% # Type of FU issued 263system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.88% # Type of FU issued 264system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.88% # Type of FU issued 265system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.88% # Type of FU issued 266system.cpu.iq.FU_type::FloatMult 0 0.00% 67.88% # Type of FU issued 267system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.88% # Type of FU issued 268system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.88% # Type of FU issued 269system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.88% # Type of FU issued 270system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.88% # Type of FU issued 271system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.88% # Type of FU issued 272system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.88% # Type of FU issued 273system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.88% # Type of FU issued 274system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.88% # Type of FU issued 275system.cpu.iq.FU_type::SimdMult 0 0.00% 67.88% # Type of FU issued 276system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.88% # Type of FU issued 277system.cpu.iq.FU_type::SimdShift 0 0.00% 67.88% # Type of FU issued 278system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.88% # Type of FU issued 279system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.88% # Type of FU issued 280system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.88% # Type of FU issued 281system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.88% # Type of FU issued 282system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.88% # Type of FU issued 283system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.88% # Type of FU issued 284system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.88% # Type of FU issued 285system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.88% # Type of FU issued 286system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.88% # Type of FU issued 287system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.88% # Type of FU issued 288system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.88% # Type of FU issued 289system.cpu.iq.FU_type::MemRead 4102 21.11% 88.98% # Type of FU issued 290system.cpu.iq.FU_type::MemWrite 2141 11.02% 100.00% # Type of FU issued 291system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued 292system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued 293system.cpu.iq.FU_type::total 19435 # Type of FU issued 294system.cpu.iq.rate 0.736035 # Inst issue rate 295system.cpu.iq.fu_busy_cnt::0 94 # FU busy when requested 296system.cpu.iq.fu_busy_cnt::1 89 # FU busy when requested 297system.cpu.iq.fu_busy_cnt::total 183 # FU busy when requested 298system.cpu.iq.fu_busy_rate::0 0.004837 # FU busy rate (busy events/executed inst) 299system.cpu.iq.fu_busy_rate::1 0.004579 # FU busy rate (busy events/executed inst) 300system.cpu.iq.fu_busy_rate::total 0.009416 # FU busy rate (busy events/executed inst) 301system.cpu.iq.int_inst_queue_reads 59279 # Number of integer instruction queue reads 302system.cpu.iq.int_inst_queue_writes 31036 # Number of integer instruction queue writes 303system.cpu.iq.int_inst_queue_wakeup_accesses 17747 # Number of integer instruction queue wakeup accesses 304system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads 305system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 306system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses 307system.cpu.iq.int_alu_accesses 19592 # Number of integer alu accesses 308system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses 309system.cpu.iew.lsq.thread0.forwLoads 48 # Number of loads that had data forwarded from stores 310system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 311system.cpu.iew.lsq.thread0.squashedLoads 1123 # Number of loads squashed 312system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 313system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations 314system.cpu.iew.lsq.thread0.squashedStores 325 # Number of stores squashed 315system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 316system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 317system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 318system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 319system.cpu.iew.lsq.thread1.forwLoads 61 # Number of loads that had data forwarded from stores 320system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address 321system.cpu.iew.lsq.thread1.squashedLoads 1134 # Number of loads squashed 322system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 323system.cpu.iew.lsq.thread1.memOrderViolation 14 # Number of memory ordering violations 324system.cpu.iew.lsq.thread1.squashedStores 316 # Number of stores squashed 325system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 326system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 327system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled 328system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 329system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 330system.cpu.iew.iewSquashCycles 1869 # Number of cycles IEW is squashing 331system.cpu.iew.iewBlockCycles 1204 # Number of cycles IEW is blocking 332system.cpu.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking 333system.cpu.iew.iewDispatchedInsts 22477 # Number of instructions dispatched to IQ 334system.cpu.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch 335system.cpu.iew.iewDispLoadInsts 4627 # Number of dispatched load instructions 336system.cpu.iew.iewDispStoreInsts 2371 # Number of dispatched store instructions 337system.cpu.iew.iewDispNonSpecInsts 49 # Number of dispatched non-speculative instructions 338system.cpu.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall 339system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall 340system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations 341system.cpu.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly 342system.cpu.iew.predictedNotTakenIncorrect 882 # Number of branches that were predicted not taken incorrectly 343system.cpu.iew.branchMispredicts 1100 # Number of branch mispredicts detected at execute 344system.cpu.iew.iewExecutedInsts 18425 # Number of executed instructions 345system.cpu.iew.iewExecLoadInsts::0 1901 # Number of load instructions executed 346system.cpu.iew.iewExecLoadInsts::1 1921 # Number of load instructions executed 347system.cpu.iew.iewExecLoadInsts::total 3822 # Number of load instructions executed 348system.cpu.iew.iewExecSquashedInsts 1010 # Number of squashed instructions skipped in execute 349system.cpu.iew.exec_swp::0 0 # number of swp insts executed 350system.cpu.iew.exec_swp::1 0 # number of swp insts executed 351system.cpu.iew.exec_swp::total 0 # number of swp insts executed 352system.cpu.iew.exec_nop::0 75 # number of nop insts executed 353system.cpu.iew.exec_nop::1 65 # number of nop insts executed 354system.cpu.iew.exec_nop::total 140 # number of nop insts executed 355system.cpu.iew.exec_refs::0 2932 # number of memory reference insts executed 356system.cpu.iew.exec_refs::1 2948 # number of memory reference insts executed 357system.cpu.iew.exec_refs::total 5880 # number of memory reference insts executed 358system.cpu.iew.exec_branches::0 1521 # Number of branches executed 359system.cpu.iew.exec_branches::1 1526 # Number of branches executed 360system.cpu.iew.exec_branches::total 3047 # Number of branches executed 361system.cpu.iew.exec_stores::0 1031 # Number of stores executed 362system.cpu.iew.exec_stores::1 1027 # Number of stores executed 363system.cpu.iew.exec_stores::total 2058 # Number of stores executed 364system.cpu.iew.exec_rate 0.697785 # Inst execution rate 365system.cpu.iew.wb_sent::0 9024 # cumulative count of insts sent to commit 366system.cpu.iew.wb_sent::1 8991 # cumulative count of insts sent to commit 367system.cpu.iew.wb_sent::total 18015 # cumulative count of insts sent to commit 368system.cpu.iew.wb_count::0 8913 # cumulative count of insts written-back 369system.cpu.iew.wb_count::1 8854 # cumulative count of insts written-back 370system.cpu.iew.wb_count::total 17767 # cumulative count of insts written-back 371system.cpu.iew.wb_producers::0 4555 # num instructions producing a value 372system.cpu.iew.wb_producers::1 4549 # num instructions producing a value 373system.cpu.iew.wb_producers::total 9104 # num instructions producing a value 374system.cpu.iew.wb_consumers::0 5963 # num instructions consuming a value 375system.cpu.iew.wb_consumers::1 5961 # num instructions consuming a value 376system.cpu.iew.wb_consumers::total 11924 # num instructions consuming a value 377system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ 378system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ 379system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ 380system.cpu.iew.wb_rate::0 0.337550 # insts written-back per cycle 381system.cpu.iew.wb_rate::1 0.335315 # insts written-back per cycle 382system.cpu.iew.wb_rate::total 0.672865 # insts written-back per cycle 383system.cpu.iew.wb_fanout::0 0.763877 # average fanout of values written-back 384system.cpu.iew.wb_fanout::1 0.763127 # average fanout of values written-back 385system.cpu.iew.wb_fanout::total 1.527004 # average fanout of values written-back 386system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ 387system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ 388system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ 389system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions 390system.cpu.commit.commitCommittedOps 12807 # The number of committed instructions 391system.cpu.commit.commitSquashedInsts 9596 # The number of squashed insts skipped by commit 392system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards 393system.cpu.commit.branchMispredicts 953 # The number of times a branch was mispredicted 394system.cpu.commit.committed_per_cycle::samples 20176 # Number of insts commited each cycle 395system.cpu.commit.committed_per_cycle::mean 0.634764 # Number of insts commited each cycle 396system.cpu.commit.committed_per_cycle::stdev 1.436773 # Number of insts commited each cycle 397system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 398system.cpu.commit.committed_per_cycle::0 14631 72.52% 72.52% # Number of insts commited each cycle 399system.cpu.commit.committed_per_cycle::1 2865 14.20% 86.72% # Number of insts commited each cycle 400system.cpu.commit.committed_per_cycle::2 1050 5.20% 91.92% # Number of insts commited each cycle 401system.cpu.commit.committed_per_cycle::3 518 2.57% 94.49% # Number of insts commited each cycle 402system.cpu.commit.committed_per_cycle::4 346 1.71% 96.20% # Number of insts commited each cycle 403system.cpu.commit.committed_per_cycle::5 239 1.18% 97.39% # Number of insts commited each cycle 404system.cpu.commit.committed_per_cycle::6 208 1.03% 98.42% # Number of insts commited each cycle 405system.cpu.commit.committed_per_cycle::7 91 0.45% 98.87% # Number of insts commited each cycle 406system.cpu.commit.committed_per_cycle::8 228 1.13% 100.00% # Number of insts commited each cycle 407system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::total 20176 # Number of insts commited each cycle 411system.cpu.commit.committedInsts::0 6403 # Number of instructions committed 412system.cpu.commit.committedInsts::1 6404 # Number of instructions committed 413system.cpu.commit.committedInsts::total 12807 # Number of instructions committed 414system.cpu.commit.committedOps::0 6403 # Number of ops (including micro ops) committed 415system.cpu.commit.committedOps::1 6404 # Number of ops (including micro ops) committed 416system.cpu.commit.committedOps::total 12807 # Number of ops (including micro ops) committed 417system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 418system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed 419system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed 420system.cpu.commit.refs::0 2050 # Number of memory references committed 421system.cpu.commit.refs::1 2050 # Number of memory references committed 422system.cpu.commit.refs::total 4100 # Number of memory references committed 423system.cpu.commit.loads::0 1185 # Number of loads committed 424system.cpu.commit.loads::1 1185 # Number of loads committed 425system.cpu.commit.loads::total 2370 # Number of loads committed 426system.cpu.commit.membars::0 0 # Number of memory barriers committed 427system.cpu.commit.membars::1 0 # Number of memory barriers committed 428system.cpu.commit.membars::total 0 # Number of memory barriers committed 429system.cpu.commit.branches::0 1051 # Number of branches committed 430system.cpu.commit.branches::1 1051 # Number of branches committed 431system.cpu.commit.branches::total 2102 # Number of branches committed 432system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. 433system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. 434system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. 435system.cpu.commit.int_insts::0 6321 # Number of committed integer instructions. 436system.cpu.commit.int_insts::1 6321 # Number of committed integer instructions. 437system.cpu.commit.int_insts::total 12642 # Number of committed integer instructions. 438system.cpu.commit.function_calls::0 127 # Number of function calls committed. 439system.cpu.commit.function_calls::1 127 # Number of function calls committed. 440system.cpu.commit.function_calls::total 254 # Number of function calls committed. 441system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached 442system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits 443system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits 444system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits 445system.cpu.rob.rob_reads 101307 # The number of ROB reads 446system.cpu.rob.rob_writes 46689 # The number of ROB writes 447system.cpu.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself 448system.cpu.idleCycles 6204 # Total number of cycles that the CPU has spent unscheduled due to idling 449system.cpu.committedInsts::0 6386 # Number of Instructions Simulated 450system.cpu.committedInsts::1 6387 # Number of Instructions Simulated 451system.cpu.committedOps::0 6386 # Number of Ops (including micro ops) Simulated 452system.cpu.committedOps::1 6387 # Number of Ops (including micro ops) Simulated 453system.cpu.committedInsts_total 12773 # Number of Instructions Simulated 454system.cpu.cpi::0 4.134826 # CPI: Cycles Per Instruction 455system.cpu.cpi::1 4.134179 # CPI: Cycles Per Instruction 456system.cpu.cpi_total 2.067251 # CPI: Total CPI of All Threads 457system.cpu.ipc::0 0.241848 # IPC: Instructions Per Cycle 458system.cpu.ipc::1 0.241886 # IPC: Instructions Per Cycle 459system.cpu.ipc_total 0.483734 # IPC: Total IPC of All Threads 460system.cpu.int_regfile_reads 23374 # number of integer regfile reads 461system.cpu.int_regfile_writes 13316 # number of integer regfile writes 462system.cpu.fp_regfile_reads 16 # number of floating regfile reads 463system.cpu.fp_regfile_writes 4 # number of floating regfile writes 464system.cpu.misc_regfile_reads 2 # number of misc regfile reads 465system.cpu.misc_regfile_writes 2 # number of misc regfile writes 466system.cpu.icache.replacements::0 6 # number of replacements 467system.cpu.icache.replacements::1 0 # number of replacements 468system.cpu.icache.replacements::total 6 # number of replacements 469system.cpu.icache.tagsinuse 314.165301 # Cycle average of tags in use 470system.cpu.icache.total_refs 3236 # Total number of references to valid blocks. 471system.cpu.icache.sampled_refs 626 # Sample count of references to valid blocks. 472system.cpu.icache.avg_refs 5.169329 # Average number of references to valid blocks. 473system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 474system.cpu.icache.occ_blocks::cpu.inst 314.165301 # Average occupied blocks per requestor 475system.cpu.icache.occ_percent::cpu.inst 0.153401 # Average percentage of cache occupancy 476system.cpu.icache.occ_percent::total 0.153401 # Average percentage of cache occupancy 477system.cpu.icache.ReadReq_hits::cpu.inst 3236 # number of ReadReq hits 478system.cpu.icache.ReadReq_hits::total 3236 # number of ReadReq hits 479system.cpu.icache.demand_hits::cpu.inst 3236 # number of demand (read+write) hits 480system.cpu.icache.demand_hits::total 3236 # number of demand (read+write) hits 481system.cpu.icache.overall_hits::cpu.inst 3236 # number of overall hits 482system.cpu.icache.overall_hits::total 3236 # number of overall hits 483system.cpu.icache.ReadReq_misses::cpu.inst 855 # number of ReadReq misses 484system.cpu.icache.ReadReq_misses::total 855 # number of ReadReq misses 485system.cpu.icache.demand_misses::cpu.inst 855 # number of demand (read+write) misses 486system.cpu.icache.demand_misses::total 855 # number of demand (read+write) misses 487system.cpu.icache.overall_misses::cpu.inst 855 # number of overall misses 488system.cpu.icache.overall_misses::total 855 # number of overall misses 489system.cpu.icache.ReadReq_miss_latency::cpu.inst 30710500 # number of ReadReq miss cycles 490system.cpu.icache.ReadReq_miss_latency::total 30710500 # number of ReadReq miss cycles 491system.cpu.icache.demand_miss_latency::cpu.inst 30710500 # number of demand (read+write) miss cycles 492system.cpu.icache.demand_miss_latency::total 30710500 # number of demand (read+write) miss cycles 493system.cpu.icache.overall_miss_latency::cpu.inst 30710500 # number of overall miss cycles 494system.cpu.icache.overall_miss_latency::total 30710500 # number of overall miss cycles 495system.cpu.icache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses) 496system.cpu.icache.ReadReq_accesses::total 4091 # number of ReadReq accesses(hits+misses) 497system.cpu.icache.demand_accesses::cpu.inst 4091 # number of demand (read+write) accesses 498system.cpu.icache.demand_accesses::total 4091 # number of demand (read+write) accesses 499system.cpu.icache.overall_accesses::cpu.inst 4091 # number of overall (read+write) accesses 500system.cpu.icache.overall_accesses::total 4091 # number of overall (read+write) accesses 501system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.208995 # miss rate for ReadReq accesses 502system.cpu.icache.demand_miss_rate::cpu.inst 0.208995 # miss rate for demand accesses 503system.cpu.icache.overall_miss_rate::cpu.inst 0.208995 # miss rate for overall accesses 504system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35918.713450 # average ReadReq miss latency 505system.cpu.icache.demand_avg_miss_latency::cpu.inst 35918.713450 # average overall miss latency 506system.cpu.icache.overall_avg_miss_latency::cpu.inst 35918.713450 # average overall miss latency 507system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 508system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 509system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 510system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 511system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 512system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 513system.cpu.icache.fast_writes 0 # number of fast writes performed 514system.cpu.icache.cache_copies 0 # number of cache copies performed 515system.cpu.icache.ReadReq_mshr_hits::cpu.inst 229 # number of ReadReq MSHR hits 516system.cpu.icache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits 517system.cpu.icache.demand_mshr_hits::cpu.inst 229 # number of demand (read+write) MSHR hits 518system.cpu.icache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits 519system.cpu.icache.overall_mshr_hits::cpu.inst 229 # number of overall MSHR hits 520system.cpu.icache.overall_mshr_hits::total 229 # number of overall MSHR hits 521system.cpu.icache.ReadReq_mshr_misses::cpu.inst 626 # number of ReadReq MSHR misses 522system.cpu.icache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses 523system.cpu.icache.demand_mshr_misses::cpu.inst 626 # number of demand (read+write) MSHR misses 524system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses 525system.cpu.icache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses 526system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses 527system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22267000 # number of ReadReq MSHR miss cycles 528system.cpu.icache.ReadReq_mshr_miss_latency::total 22267000 # number of ReadReq MSHR miss cycles 529system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22267000 # number of demand (read+write) MSHR miss cycles 530system.cpu.icache.demand_mshr_miss_latency::total 22267000 # number of demand (read+write) MSHR miss cycles 531system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22267000 # number of overall MSHR miss cycles 532system.cpu.icache.overall_mshr_miss_latency::total 22267000 # number of overall MSHR miss cycles 533system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153019 # mshr miss rate for ReadReq accesses 534system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153019 # mshr miss rate for demand accesses 535system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153019 # mshr miss rate for overall accesses 536system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35570.287540 # average ReadReq mshr miss latency 537system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35570.287540 # average overall mshr miss latency 538system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35570.287540 # average overall mshr miss latency 539system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 540system.cpu.dcache.replacements::0 0 # number of replacements 541system.cpu.dcache.replacements::1 0 # number of replacements 542system.cpu.dcache.replacements::total 0 # number of replacements 543system.cpu.dcache.tagsinuse 216.133399 # Cycle average of tags in use 544system.cpu.dcache.total_refs 4323 # Total number of references to valid blocks. 545system.cpu.dcache.sampled_refs 347 # Sample count of references to valid blocks. 546system.cpu.dcache.avg_refs 12.458213 # Average number of references to valid blocks. 547system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 548system.cpu.dcache.occ_blocks::cpu.data 216.133399 # Average occupied blocks per requestor 549system.cpu.dcache.occ_percent::cpu.data 0.052767 # Average percentage of cache occupancy 550system.cpu.dcache.occ_percent::total 0.052767 # Average percentage of cache occupancy 551system.cpu.dcache.ReadReq_hits::cpu.data 3303 # number of ReadReq hits 552system.cpu.dcache.ReadReq_hits::total 3303 # number of ReadReq hits 553system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits 554system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits 555system.cpu.dcache.demand_hits::cpu.data 4323 # number of demand (read+write) hits 556system.cpu.dcache.demand_hits::total 4323 # number of demand (read+write) hits 557system.cpu.dcache.overall_hits::cpu.data 4323 # number of overall hits 558system.cpu.dcache.overall_hits::total 4323 # number of overall hits 559system.cpu.dcache.ReadReq_misses::cpu.data 308 # number of ReadReq misses 560system.cpu.dcache.ReadReq_misses::total 308 # number of ReadReq misses 561system.cpu.dcache.WriteReq_misses::cpu.data 710 # number of WriteReq misses 562system.cpu.dcache.WriteReq_misses::total 710 # number of WriteReq misses 563system.cpu.dcache.demand_misses::cpu.data 1018 # number of demand (read+write) misses 564system.cpu.dcache.demand_misses::total 1018 # number of demand (read+write) misses 565system.cpu.dcache.overall_misses::cpu.data 1018 # number of overall misses 566system.cpu.dcache.overall_misses::total 1018 # number of overall misses 567system.cpu.dcache.ReadReq_miss_latency::cpu.data 11179500 # number of ReadReq miss cycles 568system.cpu.dcache.ReadReq_miss_latency::total 11179500 # number of ReadReq miss cycles 569system.cpu.dcache.WriteReq_miss_latency::cpu.data 24106500 # number of WriteReq miss cycles 570system.cpu.dcache.WriteReq_miss_latency::total 24106500 # number of WriteReq miss cycles 571system.cpu.dcache.demand_miss_latency::cpu.data 35286000 # number of demand (read+write) miss cycles 572system.cpu.dcache.demand_miss_latency::total 35286000 # number of demand (read+write) miss cycles 573system.cpu.dcache.overall_miss_latency::cpu.data 35286000 # number of overall miss cycles 574system.cpu.dcache.overall_miss_latency::total 35286000 # number of overall miss cycles 575system.cpu.dcache.ReadReq_accesses::cpu.data 3611 # number of ReadReq accesses(hits+misses) 576system.cpu.dcache.ReadReq_accesses::total 3611 # number of ReadReq accesses(hits+misses) 577system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) 578system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) 579system.cpu.dcache.demand_accesses::cpu.data 5341 # number of demand (read+write) accesses 580system.cpu.dcache.demand_accesses::total 5341 # number of demand (read+write) accesses 581system.cpu.dcache.overall_accesses::cpu.data 5341 # number of overall (read+write) accesses 582system.cpu.dcache.overall_accesses::total 5341 # number of overall (read+write) accesses 583system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085295 # miss rate for ReadReq accesses 584system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.410405 # miss rate for WriteReq accesses 585system.cpu.dcache.demand_miss_rate::cpu.data 0.190601 # miss rate for demand accesses 586system.cpu.dcache.overall_miss_rate::cpu.data 0.190601 # miss rate for overall accesses 587system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36297.077922 # average ReadReq miss latency 588system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33952.816901 # average WriteReq miss latency 589system.cpu.dcache.demand_avg_miss_latency::cpu.data 34662.082515 # average overall miss latency 590system.cpu.dcache.overall_avg_miss_latency::cpu.data 34662.082515 # average overall miss latency 591system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 592system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 593system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 594system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 595system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 596system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 597system.cpu.dcache.fast_writes 0 # number of fast writes performed 598system.cpu.dcache.cache_copies 0 # number of cache copies performed 599system.cpu.dcache.ReadReq_mshr_hits::cpu.data 107 # number of ReadReq MSHR hits 600system.cpu.dcache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits 601system.cpu.dcache.WriteReq_mshr_hits::cpu.data 564 # number of WriteReq MSHR hits 602system.cpu.dcache.WriteReq_mshr_hits::total 564 # number of WriteReq MSHR hits 603system.cpu.dcache.demand_mshr_hits::cpu.data 671 # number of demand (read+write) MSHR hits 604system.cpu.dcache.demand_mshr_hits::total 671 # number of demand (read+write) MSHR hits 605system.cpu.dcache.overall_mshr_hits::cpu.data 671 # number of overall MSHR hits 606system.cpu.dcache.overall_mshr_hits::total 671 # number of overall MSHR hits 607system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses 608system.cpu.dcache.ReadReq_mshr_misses::total 201 # number of ReadReq MSHR misses 609system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses 610system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses 611system.cpu.dcache.demand_mshr_misses::cpu.data 347 # number of demand (read+write) MSHR misses 612system.cpu.dcache.demand_mshr_misses::total 347 # number of demand (read+write) MSHR misses 613system.cpu.dcache.overall_mshr_misses::cpu.data 347 # number of overall MSHR misses 614system.cpu.dcache.overall_mshr_misses::total 347 # number of overall MSHR misses 615system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7376000 # number of ReadReq MSHR miss cycles 616system.cpu.dcache.ReadReq_mshr_miss_latency::total 7376000 # number of ReadReq MSHR miss cycles 617system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5298000 # number of WriteReq MSHR miss cycles 618system.cpu.dcache.WriteReq_mshr_miss_latency::total 5298000 # number of WriteReq MSHR miss cycles 619system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12674000 # number of demand (read+write) MSHR miss cycles 620system.cpu.dcache.demand_mshr_miss_latency::total 12674000 # number of demand (read+write) MSHR miss cycles 621system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12674000 # number of overall MSHR miss cycles 622system.cpu.dcache.overall_mshr_miss_latency::total 12674000 # number of overall MSHR miss cycles 623system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055663 # mshr miss rate for ReadReq accesses 624system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 625system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064969 # mshr miss rate for demand accesses 626system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064969 # mshr miss rate for overall accesses 627system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36696.517413 # average ReadReq mshr miss latency 628system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36287.671233 # average WriteReq mshr miss latency 629system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36524.495677 # average overall mshr miss latency 630system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36524.495677 # average overall mshr miss latency 631system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 632system.cpu.l2cache.replacements::0 0 # number of replacements 633system.cpu.l2cache.replacements::1 0 # number of replacements 634system.cpu.l2cache.replacements::total 0 # number of replacements 635system.cpu.l2cache.tagsinuse 435.235373 # Cycle average of tags in use 636system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 637system.cpu.l2cache.sampled_refs 825 # Sample count of references to valid blocks. 638system.cpu.l2cache.avg_refs 0.002424 # Average number of references to valid blocks. 639system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 640system.cpu.l2cache.occ_blocks::cpu.inst 314.499531 # Average occupied blocks per requestor 641system.cpu.l2cache.occ_blocks::cpu.data 120.735842 # Average occupied blocks per requestor 642system.cpu.l2cache.occ_percent::cpu.inst 0.009598 # Average percentage of cache occupancy 643system.cpu.l2cache.occ_percent::cpu.data 0.003685 # Average percentage of cache occupancy 644system.cpu.l2cache.occ_percent::total 0.013282 # Average percentage of cache occupancy 645system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 646system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 647system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 648system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 649system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 650system.cpu.l2cache.overall_hits::total 2 # number of overall hits 651system.cpu.l2cache.ReadReq_misses::cpu.inst 624 # number of ReadReq misses 652system.cpu.l2cache.ReadReq_misses::cpu.data 201 # number of ReadReq misses 653system.cpu.l2cache.ReadReq_misses::total 825 # number of ReadReq misses 654system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses 655system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses 656system.cpu.l2cache.demand_misses::cpu.inst 624 # number of demand (read+write) misses 657system.cpu.l2cache.demand_misses::cpu.data 347 # number of demand (read+write) misses 658system.cpu.l2cache.demand_misses::total 971 # number of demand (read+write) misses 659system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses 660system.cpu.l2cache.overall_misses::cpu.data 347 # number of overall misses 661system.cpu.l2cache.overall_misses::total 971 # number of overall misses 662system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21475000 # number of ReadReq miss cycles 663system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6995000 # number of ReadReq miss cycles 664system.cpu.l2cache.ReadReq_miss_latency::total 28470000 # number of ReadReq miss cycles 665system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5066000 # number of ReadExReq miss cycles 666system.cpu.l2cache.ReadExReq_miss_latency::total 5066000 # number of ReadExReq miss cycles 667system.cpu.l2cache.demand_miss_latency::cpu.inst 21475000 # number of demand (read+write) miss cycles 668system.cpu.l2cache.demand_miss_latency::cpu.data 12061000 # number of demand (read+write) miss cycles 669system.cpu.l2cache.demand_miss_latency::total 33536000 # number of demand (read+write) miss cycles 670system.cpu.l2cache.overall_miss_latency::cpu.inst 21475000 # number of overall miss cycles 671system.cpu.l2cache.overall_miss_latency::cpu.data 12061000 # number of overall miss cycles 672system.cpu.l2cache.overall_miss_latency::total 33536000 # number of overall miss cycles 673system.cpu.l2cache.ReadReq_accesses::cpu.inst 626 # number of ReadReq accesses(hits+misses) 674system.cpu.l2cache.ReadReq_accesses::cpu.data 201 # number of ReadReq accesses(hits+misses) 675system.cpu.l2cache.ReadReq_accesses::total 827 # number of ReadReq accesses(hits+misses) 676system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) 677system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) 678system.cpu.l2cache.demand_accesses::cpu.inst 626 # number of demand (read+write) accesses 679system.cpu.l2cache.demand_accesses::cpu.data 347 # number of demand (read+write) accesses 680system.cpu.l2cache.demand_accesses::total 973 # number of demand (read+write) accesses 681system.cpu.l2cache.overall_accesses::cpu.inst 626 # number of overall (read+write) accesses 682system.cpu.l2cache.overall_accesses::cpu.data 347 # number of overall (read+write) accesses 683system.cpu.l2cache.overall_accesses::total 973 # number of overall (read+write) accesses 684system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses 685system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 686system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 687system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses 688system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 689system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses 690system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 691system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34415.064103 # average ReadReq miss latency 692system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34800.995025 # average ReadReq miss latency 693system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34698.630137 # average ReadExReq miss latency 694system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34415.064103 # average overall miss latency 695system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34757.925072 # average overall miss latency 696system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34415.064103 # average overall miss latency 697system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34757.925072 # average overall miss latency 698system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked 699system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 700system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked 701system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 702system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5250 # average number of cycles each access was blocked 703system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 704system.cpu.l2cache.fast_writes 0 # number of fast writes performed 705system.cpu.l2cache.cache_copies 0 # number of cache copies performed 706system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses 707system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses 708system.cpu.l2cache.ReadReq_mshr_misses::total 825 # number of ReadReq MSHR misses 709system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses 710system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses 711system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses 712system.cpu.l2cache.demand_mshr_misses::cpu.data 347 # number of demand (read+write) MSHR misses 713system.cpu.l2cache.demand_mshr_misses::total 971 # number of demand (read+write) MSHR misses 714system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses 715system.cpu.l2cache.overall_mshr_misses::cpu.data 347 # number of overall MSHR misses 716system.cpu.l2cache.overall_mshr_misses::total 971 # number of overall MSHR misses 717system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19514500 # number of ReadReq MSHR miss cycles 718system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6372500 # number of ReadReq MSHR miss cycles 719system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25887000 # number of ReadReq MSHR miss cycles 720system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4614000 # number of ReadExReq MSHR miss cycles 721system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4614000 # number of ReadExReq MSHR miss cycles 722system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19514500 # number of demand (read+write) MSHR miss cycles 723system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10986500 # number of demand (read+write) MSHR miss cycles 724system.cpu.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles 725system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19514500 # number of overall MSHR miss cycles 726system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10986500 # number of overall MSHR miss cycles 727system.cpu.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles 728system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses 729system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 730system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 731system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses 732system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 733system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses 734system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 735system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31273.237179 # average ReadReq mshr miss latency 736system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31703.980100 # average ReadReq mshr miss latency 737system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31602.739726 # average ReadExReq mshr miss latency 738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31273.237179 # average overall mshr miss latency 739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31661.383285 # average overall mshr miss latency 740system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31273.237179 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31661.383285 # average overall mshr miss latency 742system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 743 744---------- End Simulation Statistics ---------- 745