stats.txt revision 8464
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000013 # Number of seconds simulated 4sim_ticks 13218000 # Number of ticks simulated 5sim_freq 1000000000000 # Frequency of simulated ticks 6host_inst_rate 47211 # Simulator instruction rate (inst/s) 7host_tick_rate 48851159 # Simulator tick rate (ticks/s) 8host_mem_usage 244284 # Number of bytes of host memory used 9host_seconds 0.27 # Real time elapsed on the host 10sim_insts 12773 # Number of instructions simulated 11system.cpu.dtb.fetch_hits 0 # ITB hits 12system.cpu.dtb.fetch_misses 0 # ITB misses 13system.cpu.dtb.fetch_acv 0 # ITB acv 14system.cpu.dtb.fetch_accesses 0 # ITB accesses 15system.cpu.dtb.read_hits 3714 # DTB read hits 16system.cpu.dtb.read_misses 89 # DTB read misses 17system.cpu.dtb.read_acv 0 # DTB read access violations 18system.cpu.dtb.read_accesses 3803 # DTB read accesses 19system.cpu.dtb.write_hits 1992 # DTB write hits 20system.cpu.dtb.write_misses 59 # DTB write misses 21system.cpu.dtb.write_acv 0 # DTB write access violations 22system.cpu.dtb.write_accesses 2051 # DTB write accesses 23system.cpu.dtb.data_hits 5706 # DTB hits 24system.cpu.dtb.data_misses 148 # DTB misses 25system.cpu.dtb.data_acv 0 # DTB access violations 26system.cpu.dtb.data_accesses 5854 # DTB accesses 27system.cpu.itb.fetch_hits 4085 # ITB hits 28system.cpu.itb.fetch_misses 56 # ITB misses 29system.cpu.itb.fetch_acv 0 # ITB acv 30system.cpu.itb.fetch_accesses 4141 # ITB accesses 31system.cpu.itb.read_hits 0 # DTB read hits 32system.cpu.itb.read_misses 0 # DTB read misses 33system.cpu.itb.read_acv 0 # DTB read access violations 34system.cpu.itb.read_accesses 0 # DTB read accesses 35system.cpu.itb.write_hits 0 # DTB write hits 36system.cpu.itb.write_misses 0 # DTB write misses 37system.cpu.itb.write_acv 0 # DTB write access violations 38system.cpu.itb.write_accesses 0 # DTB write accesses 39system.cpu.itb.data_hits 0 # DTB hits 40system.cpu.itb.data_misses 0 # DTB misses 41system.cpu.itb.data_acv 0 # DTB access violations 42system.cpu.itb.data_accesses 0 # DTB accesses 43system.cpu.workload0.num_syscalls 17 # Number of system calls 44system.cpu.workload1.num_syscalls 17 # Number of system calls 45system.cpu.numCycles 26437 # number of cpu cycles simulated 46system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 47system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 48system.cpu.BPredUnit.lookups 5187 # Number of BP lookups 49system.cpu.BPredUnit.condPredicted 2958 # Number of conditional branches predicted 50system.cpu.BPredUnit.condIncorrect 1247 # Number of conditional branches incorrect 51system.cpu.BPredUnit.BTBLookups 3609 # Number of BTB lookups 52system.cpu.BPredUnit.BTBHits 1000 # Number of BTB hits 53system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 54system.cpu.BPredUnit.usedRAS 740 # Number of times the RAS was used to get a target. 55system.cpu.BPredUnit.RASInCorrect 156 # Number of incorrect RAS predictions. 56system.cpu.fetch.icacheStallCycles 1108 # Number of cycles fetch is stalled on an Icache miss 57system.cpu.fetch.Insts 29051 # Number of instructions fetch has processed 58system.cpu.fetch.Branches 5187 # Number of branches that fetch encountered 59system.cpu.fetch.predictedBranches 1740 # Number of branches that fetch has predicted taken 60system.cpu.fetch.Cycles 5000 # Number of cycles fetch has run and was not squashing or blocked 61system.cpu.fetch.SquashCycles 1319 # Number of cycles fetch has spent squashing 62system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 63system.cpu.fetch.CacheLines 4085 # Number of cache lines fetched 64system.cpu.fetch.IcacheSquashes 640 # Number of outstanding Icache misses that were squashed 65system.cpu.fetch.rateDist::samples 20361 # Number of instructions fetched each cycle (Total) 66system.cpu.fetch.rateDist::mean 1.426796 # Number of instructions fetched each cycle (Total) 67system.cpu.fetch.rateDist::stdev 2.797497 # Number of instructions fetched each cycle (Total) 68system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 69system.cpu.fetch.rateDist::0 15361 75.44% 75.44% # Number of instructions fetched each cycle (Total) 70system.cpu.fetch.rateDist::1 451 2.22% 77.66% # Number of instructions fetched each cycle (Total) 71system.cpu.fetch.rateDist::2 362 1.78% 79.44% # Number of instructions fetched each cycle (Total) 72system.cpu.fetch.rateDist::3 388 1.91% 81.34% # Number of instructions fetched each cycle (Total) 73system.cpu.fetch.rateDist::4 391 1.92% 83.26% # Number of instructions fetched each cycle (Total) 74system.cpu.fetch.rateDist::5 325 1.60% 84.86% # Number of instructions fetched each cycle (Total) 75system.cpu.fetch.rateDist::6 409 2.01% 86.87% # Number of instructions fetched each cycle (Total) 76system.cpu.fetch.rateDist::7 323 1.59% 88.45% # Number of instructions fetched each cycle (Total) 77system.cpu.fetch.rateDist::8 2351 11.55% 100.00% # Number of instructions fetched each cycle (Total) 78system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 79system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 80system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 81system.cpu.fetch.rateDist::total 20361 # Number of instructions fetched each cycle (Total) 82system.cpu.fetch.branchRate 0.196202 # Number of branch fetches per cycle 83system.cpu.fetch.rate 1.098877 # Number of inst fetches per cycle 84system.cpu.decode.IdleCycles 28250 # Number of cycles decode is idle 85system.cpu.decode.BlockedCycles 5561 # Number of cycles decode is blocked 86system.cpu.decode.RunCycles 4330 # Number of cycles decode is running 87system.cpu.decode.UnblockCycles 453 # Number of cycles decode is unblocking 88system.cpu.decode.SquashCycles 1870 # Number of cycles decode is squashing 89system.cpu.decode.BranchResolved 485 # Number of times decode resolved a branch 90system.cpu.decode.BranchMispred 311 # Number of times decode detected a branch misprediction 91system.cpu.decode.DecodedInsts 25978 # Number of instructions handled by decode 92system.cpu.decode.SquashedInsts 552 # Number of squashed instructions handled by decode 93system.cpu.rename.SquashCycles 1870 # Number of cycles rename is squashing 94system.cpu.rename.IdleCycles 28803 # Number of cycles rename is idle 95system.cpu.rename.BlockCycles 2995 # Number of cycles rename is blocking 96system.cpu.rename.serializeStallCycles 772 # count of cycles rename stalled for serializing inst 97system.cpu.rename.RunCycles 4141 # Number of cycles rename is running 98system.cpu.rename.UnblockCycles 1883 # Number of cycles rename is unblocking 99system.cpu.rename.RenamedInsts 24541 # Number of instructions processed by rename 100system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full 101system.cpu.rename.LSQFullEvents 1746 # Number of times rename has blocked due to LSQ full 102system.cpu.rename.RenamedOperands 18357 # Number of destination operands rename has renamed 103system.cpu.rename.RenameLookups 30569 # Number of register rename lookups that rename has made 104system.cpu.rename.int_rename_lookups 30535 # Number of integer rename lookups 105system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups 106system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed 107system.cpu.rename.UndoneMaps 9191 # Number of HB maps that are undone due to squashing 108system.cpu.rename.serializingInsts 52 # count of serializing insts renamed 109system.cpu.rename.tempSerializingInsts 40 # count of temporary serializing insts renamed 110system.cpu.rename.skidInsts 4665 # count of insts added to the skid buffer 111system.cpu.memDep0.insertedLoads 2306 # Number of loads inserted to the mem dependence unit. 112system.cpu.memDep0.insertedStores 1192 # Number of stores inserted to the mem dependence unit. 113system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 114system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 115system.cpu.memDep1.insertedLoads 2327 # Number of loads inserted to the mem dependence unit. 116system.cpu.memDep1.insertedStores 1184 # Number of stores inserted to the mem dependence unit. 117system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads. 118system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. 119system.cpu.iq.iqInstsAdded 22275 # Number of instructions added to the IQ (excludes non-spec) 120system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 121system.cpu.iq.iqInstsIssued 19420 # Number of instructions issued 122system.cpu.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued 123system.cpu.iq.iqSquashedInstsExamined 8699 # Number of squashed instructions iterated over during squash; mainly for profiling 124system.cpu.iq.iqSquashedOperandsExamined 4701 # Number of squashed operands that are examined and possibly removed from graph 125system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed 126system.cpu.iq.issued_per_cycle::samples 20361 # Number of insts issued each cycle 127system.cpu.iq.issued_per_cycle::mean 0.953784 # Number of insts issued each cycle 128system.cpu.iq.issued_per_cycle::stdev 1.476295 # Number of insts issued each cycle 129system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 130system.cpu.iq.issued_per_cycle::0 12146 59.65% 59.65% # Number of insts issued each cycle 131system.cpu.iq.issued_per_cycle::1 2930 14.39% 74.04% # Number of insts issued each cycle 132system.cpu.iq.issued_per_cycle::2 2237 10.99% 85.03% # Number of insts issued each cycle 133system.cpu.iq.issued_per_cycle::3 1382 6.79% 91.82% # Number of insts issued each cycle 134system.cpu.iq.issued_per_cycle::4 875 4.30% 96.12% # Number of insts issued each cycle 135system.cpu.iq.issued_per_cycle::5 479 2.35% 98.47% # Number of insts issued each cycle 136system.cpu.iq.issued_per_cycle::6 226 1.11% 99.58% # Number of insts issued each cycle 137system.cpu.iq.issued_per_cycle::7 69 0.34% 99.92% # Number of insts issued each cycle 138system.cpu.iq.issued_per_cycle::8 17 0.08% 100.00% # Number of insts issued each cycle 139system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 140system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 141system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 142system.cpu.iq.issued_per_cycle::total 20361 # Number of insts issued each cycle 143system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 144system.cpu.iq.fu_full::IntAlu 8 4.44% 4.44% # attempts to use FU when none available 145system.cpu.iq.fu_full::IntMult 0 0.00% 4.44% # attempts to use FU when none available 146system.cpu.iq.fu_full::IntDiv 0 0.00% 4.44% # attempts to use FU when none available 147system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.44% # attempts to use FU when none available 148system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.44% # attempts to use FU when none available 149system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.44% # attempts to use FU when none available 150system.cpu.iq.fu_full::FloatMult 0 0.00% 4.44% # attempts to use FU when none available 151system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.44% # attempts to use FU when none available 152system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.44% # attempts to use FU when none available 153system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.44% # attempts to use FU when none available 154system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.44% # attempts to use FU when none available 155system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.44% # attempts to use FU when none available 156system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.44% # attempts to use FU when none available 157system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.44% # attempts to use FU when none available 158system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.44% # attempts to use FU when none available 159system.cpu.iq.fu_full::SimdMult 0 0.00% 4.44% # attempts to use FU when none available 160system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.44% # attempts to use FU when none available 161system.cpu.iq.fu_full::SimdShift 0 0.00% 4.44% # attempts to use FU when none available 162system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.44% # attempts to use FU when none available 163system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.44% # attempts to use FU when none available 164system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.44% # attempts to use FU when none available 165system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.44% # attempts to use FU when none available 166system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.44% # attempts to use FU when none available 167system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.44% # attempts to use FU when none available 168system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.44% # attempts to use FU when none available 169system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.44% # attempts to use FU when none available 170system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.44% # attempts to use FU when none available 171system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.44% # attempts to use FU when none available 172system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.44% # attempts to use FU when none available 173system.cpu.iq.fu_full::MemRead 103 57.22% 61.67% # attempts to use FU when none available 174system.cpu.iq.fu_full::MemWrite 69 38.33% 100.00% # attempts to use FU when none available 175system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 176system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 177system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 178system.cpu.iq.FU_type_0::IntAlu 6596 67.90% 67.92% # Type of FU issued 179system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.93% # Type of FU issued 180system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.93% # Type of FU issued 181system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.95% # Type of FU issued 182system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.95% # Type of FU issued 183system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.95% # Type of FU issued 184system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.95% # Type of FU issued 185system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.95% # Type of FU issued 186system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.95% # Type of FU issued 187system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.95% # Type of FU issued 188system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.95% # Type of FU issued 189system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.95% # Type of FU issued 190system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.95% # Type of FU issued 191system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.95% # Type of FU issued 192system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.95% # Type of FU issued 193system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.95% # Type of FU issued 194system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.95% # Type of FU issued 195system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.95% # Type of FU issued 196system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.95% # Type of FU issued 197system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.95% # Type of FU issued 198system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.95% # Type of FU issued 199system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.95% # Type of FU issued 200system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.95% # Type of FU issued 201system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.95% # Type of FU issued 202system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.95% # Type of FU issued 203system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.95% # Type of FU issued 204system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.95% # Type of FU issued 205system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.95% # Type of FU issued 206system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.95% # Type of FU issued 207system.cpu.iq.FU_type_0::MemRead 2046 21.06% 89.01% # Type of FU issued 208system.cpu.iq.FU_type_0::MemWrite 1068 10.99% 100.00% # Type of FU issued 209system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 210system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 211system.cpu.iq.FU_type_0::total 9715 # Type of FU issued 212system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued 213system.cpu.iq.FU_type_1::IntAlu 6577 67.77% 67.79% # Type of FU issued 214system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.80% # Type of FU issued 215system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.80% # Type of FU issued 216system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.82% # Type of FU issued 217system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.82% # Type of FU issued 218system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.82% # Type of FU issued 219system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.82% # Type of FU issued 220system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.82% # Type of FU issued 221system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.82% # Type of FU issued 222system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.82% # Type of FU issued 223system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.82% # Type of FU issued 224system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.82% # Type of FU issued 225system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.82% # Type of FU issued 226system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.82% # Type of FU issued 227system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.82% # Type of FU issued 228system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.82% # Type of FU issued 229system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.82% # Type of FU issued 230system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.82% # Type of FU issued 231system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued 232system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.82% # Type of FU issued 233system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued 234system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued 235system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued 236system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued 237system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued 238system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.82% # Type of FU issued 239system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.82% # Type of FU issued 240system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued 241system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued 242system.cpu.iq.FU_type_1::MemRead 2049 21.11% 88.93% # Type of FU issued 243system.cpu.iq.FU_type_1::MemWrite 1074 11.07% 100.00% # Type of FU issued 244system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 245system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued 246system.cpu.iq.FU_type_1::total 9705 # Type of FU issued 247system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued 248system.cpu.iq.FU_type::IntAlu 13173 67.83% 67.85% # Type of FU issued 249system.cpu.iq.FU_type::IntMult 2 0.01% 67.86% # Type of FU issued 250system.cpu.iq.FU_type::IntDiv 0 0.00% 67.86% # Type of FU issued 251system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.88% # Type of FU issued 252system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.88% # Type of FU issued 253system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.88% # Type of FU issued 254system.cpu.iq.FU_type::FloatMult 0 0.00% 67.88% # Type of FU issued 255system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.88% # Type of FU issued 256system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.88% # Type of FU issued 257system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.88% # Type of FU issued 258system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.88% # Type of FU issued 259system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.88% # Type of FU issued 260system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.88% # Type of FU issued 261system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.88% # Type of FU issued 262system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.88% # Type of FU issued 263system.cpu.iq.FU_type::SimdMult 0 0.00% 67.88% # Type of FU issued 264system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.88% # Type of FU issued 265system.cpu.iq.FU_type::SimdShift 0 0.00% 67.88% # Type of FU issued 266system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.88% # Type of FU issued 267system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.88% # Type of FU issued 268system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.88% # Type of FU issued 269system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.88% # Type of FU issued 270system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.88% # Type of FU issued 271system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.88% # Type of FU issued 272system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.88% # Type of FU issued 273system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.88% # Type of FU issued 274system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.88% # Type of FU issued 275system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.88% # Type of FU issued 276system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.88% # Type of FU issued 277system.cpu.iq.FU_type::MemRead 4095 21.09% 88.97% # Type of FU issued 278system.cpu.iq.FU_type::MemWrite 2142 11.03% 100.00% # Type of FU issued 279system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued 280system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued 281system.cpu.iq.FU_type::total 19420 # Type of FU issued 282system.cpu.iq.rate 0.734577 # Inst issue rate 283system.cpu.iq.fu_busy_cnt::0 90 # FU busy when requested 284system.cpu.iq.fu_busy_cnt::1 90 # FU busy when requested 285system.cpu.iq.fu_busy_cnt::total 180 # FU busy when requested 286system.cpu.iq.fu_busy_rate::0 0.004634 # FU busy rate (busy events/executed inst) 287system.cpu.iq.fu_busy_rate::1 0.004634 # FU busy rate (busy events/executed inst) 288system.cpu.iq.fu_busy_rate::total 0.009269 # FU busy rate (busy events/executed inst) 289system.cpu.iq.int_inst_queue_reads 59410 # Number of integer instruction queue reads 290system.cpu.iq.int_inst_queue_writes 31025 # Number of integer instruction queue writes 291system.cpu.iq.int_inst_queue_wakeup_accesses 17735 # Number of integer instruction queue wakeup accesses 292system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads 293system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 294system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses 295system.cpu.iq.int_alu_accesses 19574 # Number of integer alu accesses 296system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses 297system.cpu.iew.lsq.thread0.forwLoads 48 # Number of loads that had data forwarded from stores 298system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 299system.cpu.iew.lsq.thread0.squashedLoads 1121 # Number of loads squashed 300system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 301system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations 302system.cpu.iew.lsq.thread0.squashedStores 327 # Number of stores squashed 303system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 304system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 305system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 306system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 307system.cpu.iew.lsq.thread1.forwLoads 64 # Number of loads that had data forwarded from stores 308system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address 309system.cpu.iew.lsq.thread1.squashedLoads 1142 # Number of loads squashed 310system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 311system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations 312system.cpu.iew.lsq.thread1.squashedStores 319 # Number of stores squashed 313system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 314system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 315system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled 316system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 317system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 318system.cpu.iew.iewSquashCycles 1870 # Number of cycles IEW is squashing 319system.cpu.iew.iewBlockCycles 1204 # Number of cycles IEW is blocking 320system.cpu.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking 321system.cpu.iew.iewDispatchedInsts 22464 # Number of instructions dispatched to IQ 322system.cpu.iew.iewDispSquashedInsts 427 # Number of squashed instructions skipped by dispatch 323system.cpu.iew.iewDispLoadInsts 4633 # Number of dispatched load instructions 324system.cpu.iew.iewDispStoreInsts 2376 # Number of dispatched store instructions 325system.cpu.iew.iewDispNonSpecInsts 49 # Number of dispatched non-speculative instructions 326system.cpu.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall 327system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall 328system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations 329system.cpu.iew.predictedTakenIncorrect 214 # Number of branches that were predicted taken incorrectly 330system.cpu.iew.predictedNotTakenIncorrect 883 # Number of branches that were predicted not taken incorrectly 331system.cpu.iew.branchMispredicts 1097 # Number of branch mispredicts detected at execute 332system.cpu.iew.iewExecutedInsts 18405 # Number of executed instructions 333system.cpu.iew.iewExecLoadInsts::0 1891 # Number of load instructions executed 334system.cpu.iew.iewExecLoadInsts::1 1918 # Number of load instructions executed 335system.cpu.iew.iewExecLoadInsts::total 3809 # Number of load instructions executed 336system.cpu.iew.iewExecSquashedInsts 1015 # Number of squashed instructions skipped in execute 337system.cpu.iew.exec_swp::0 0 # number of swp insts executed 338system.cpu.iew.exec_swp::1 0 # number of swp insts executed 339system.cpu.iew.exec_swp::total 0 # number of swp insts executed 340system.cpu.iew.exec_nop::0 75 # number of nop insts executed 341system.cpu.iew.exec_nop::1 65 # number of nop insts executed 342system.cpu.iew.exec_nop::total 140 # number of nop insts executed 343system.cpu.iew.exec_refs::0 2925 # number of memory reference insts executed 344system.cpu.iew.exec_refs::1 2953 # number of memory reference insts executed 345system.cpu.iew.exec_refs::total 5878 # number of memory reference insts executed 346system.cpu.iew.exec_branches::0 1521 # Number of branches executed 347system.cpu.iew.exec_branches::1 1527 # Number of branches executed 348system.cpu.iew.exec_branches::total 3048 # Number of branches executed 349system.cpu.iew.exec_stores::0 1034 # Number of stores executed 350system.cpu.iew.exec_stores::1 1035 # Number of stores executed 351system.cpu.iew.exec_stores::total 2069 # Number of stores executed 352system.cpu.iew.exec_rate 0.696183 # Inst execution rate 353system.cpu.iew.wb_sent::0 9003 # cumulative count of insts sent to commit 354system.cpu.iew.wb_sent::1 9003 # cumulative count of insts sent to commit 355system.cpu.iew.wb_sent::total 18006 # cumulative count of insts sent to commit 356system.cpu.iew.wb_count::0 8892 # cumulative count of insts written-back 357system.cpu.iew.wb_count::1 8863 # cumulative count of insts written-back 358system.cpu.iew.wb_count::total 17755 # cumulative count of insts written-back 359system.cpu.iew.wb_producers::0 4543 # num instructions producing a value 360system.cpu.iew.wb_producers::1 4543 # num instructions producing a value 361system.cpu.iew.wb_producers::total 9086 # num instructions producing a value 362system.cpu.iew.wb_consumers::0 5945 # num instructions consuming a value 363system.cpu.iew.wb_consumers::1 5949 # num instructions consuming a value 364system.cpu.iew.wb_consumers::total 11894 # num instructions consuming a value 365system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ 366system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ 367system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ 368system.cpu.iew.wb_rate::0 0.336347 # insts written-back per cycle 369system.cpu.iew.wb_rate::1 0.335250 # insts written-back per cycle 370system.cpu.iew.wb_rate::total 0.671597 # insts written-back per cycle 371system.cpu.iew.wb_fanout::0 0.764172 # average fanout of values written-back 372system.cpu.iew.wb_fanout::1 0.763658 # average fanout of values written-back 373system.cpu.iew.wb_fanout::total 1.527829 # average fanout of values written-back 374system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ 375system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ 376system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ 377system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions 378system.cpu.commit.commitSquashedInsts 9583 # The number of squashed insts skipped by commit 379system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards 380system.cpu.commit.branchMispredicts 951 # The number of times a branch was mispredicted 381system.cpu.commit.committed_per_cycle::samples 20336 # Number of insts commited each cycle 382system.cpu.commit.committed_per_cycle::mean 0.629770 # Number of insts commited each cycle 383system.cpu.commit.committed_per_cycle::stdev 1.428976 # Number of insts commited each cycle 384system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 385system.cpu.commit.committed_per_cycle::0 14766 72.61% 72.61% # Number of insts commited each cycle 386system.cpu.commit.committed_per_cycle::1 2895 14.24% 86.85% # Number of insts commited each cycle 387system.cpu.commit.committed_per_cycle::2 1050 5.16% 92.01% # Number of insts commited each cycle 388system.cpu.commit.committed_per_cycle::3 514 2.53% 94.54% # Number of insts commited each cycle 389system.cpu.commit.committed_per_cycle::4 350 1.72% 96.26% # Number of insts commited each cycle 390system.cpu.commit.committed_per_cycle::5 235 1.16% 97.41% # Number of insts commited each cycle 391system.cpu.commit.committed_per_cycle::6 212 1.04% 98.46% # Number of insts commited each cycle 392system.cpu.commit.committed_per_cycle::7 89 0.44% 98.89% # Number of insts commited each cycle 393system.cpu.commit.committed_per_cycle::8 225 1.11% 100.00% # Number of insts commited each cycle 394system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 395system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 396system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 397system.cpu.commit.committed_per_cycle::total 20336 # Number of insts commited each cycle 398system.cpu.commit.count::0 6403 # Number of instructions committed 399system.cpu.commit.count::1 6404 # Number of instructions committed 400system.cpu.commit.count::total 12807 # Number of instructions committed 401system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 402system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed 403system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed 404system.cpu.commit.refs::0 2050 # Number of memory references committed 405system.cpu.commit.refs::1 2050 # Number of memory references committed 406system.cpu.commit.refs::total 4100 # Number of memory references committed 407system.cpu.commit.loads::0 1185 # Number of loads committed 408system.cpu.commit.loads::1 1185 # Number of loads committed 409system.cpu.commit.loads::total 2370 # Number of loads committed 410system.cpu.commit.membars::0 0 # Number of memory barriers committed 411system.cpu.commit.membars::1 0 # Number of memory barriers committed 412system.cpu.commit.membars::total 0 # Number of memory barriers committed 413system.cpu.commit.branches::0 1051 # Number of branches committed 414system.cpu.commit.branches::1 1051 # Number of branches committed 415system.cpu.commit.branches::total 2102 # Number of branches committed 416system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. 417system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. 418system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. 419system.cpu.commit.int_insts::0 6321 # Number of committed integer instructions. 420system.cpu.commit.int_insts::1 6321 # Number of committed integer instructions. 421system.cpu.commit.int_insts::total 12642 # Number of committed integer instructions. 422system.cpu.commit.function_calls::0 127 # Number of function calls committed. 423system.cpu.commit.function_calls::1 127 # Number of function calls committed. 424system.cpu.commit.function_calls::total 254 # Number of function calls committed. 425system.cpu.commit.bw_lim_events 225 # number cycles where commit BW limit reached 426system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits 427system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits 428system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits 429system.cpu.rob.rob_reads 101662 # The number of ROB reads 430system.cpu.rob.rob_writes 46661 # The number of ROB writes 431system.cpu.timesIdled 242 # Number of times that the entire CPU went into an idle state and unscheduled itself 432system.cpu.idleCycles 6076 # Total number of cycles that the CPU has spent unscheduled due to idling 433system.cpu.committedInsts::0 6386 # Number of Instructions Simulated 434system.cpu.committedInsts::1 6387 # Number of Instructions Simulated 435system.cpu.committedInsts_total 12773 # Number of Instructions Simulated 436system.cpu.cpi::0 4.139837 # CPI: Cycles Per Instruction 437system.cpu.cpi::1 4.139189 # CPI: Cycles Per Instruction 438system.cpu.cpi_total 2.069757 # CPI: Total CPI of All Threads 439system.cpu.ipc::0 0.241555 # IPC: Instructions Per Cycle 440system.cpu.ipc::1 0.241593 # IPC: Instructions Per Cycle 441system.cpu.ipc_total 0.483149 # IPC: Total IPC of All Threads 442system.cpu.int_regfile_reads 23349 # number of integer regfile reads 443system.cpu.int_regfile_writes 13299 # number of integer regfile writes 444system.cpu.fp_regfile_reads 16 # number of floating regfile reads 445system.cpu.fp_regfile_writes 4 # number of floating regfile writes 446system.cpu.misc_regfile_reads 2 # number of misc regfile reads 447system.cpu.misc_regfile_writes 2 # number of misc regfile writes 448system.cpu.icache.replacements::0 6 # number of replacements 449system.cpu.icache.replacements::1 0 # number of replacements 450system.cpu.icache.replacements::total 6 # number of replacements 451system.cpu.icache.tagsinuse 314.403866 # Cycle average of tags in use 452system.cpu.icache.total_refs 3230 # Total number of references to valid blocks. 453system.cpu.icache.sampled_refs 626 # Sample count of references to valid blocks. 454system.cpu.icache.avg_refs 5.159744 # Average number of references to valid blocks. 455system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 456system.cpu.icache.occ_blocks::0 314.403866 # Average occupied blocks per context 457system.cpu.icache.occ_percent::0 0.153518 # Average percentage of cache occupancy 458system.cpu.icache.ReadReq_hits 3230 # number of ReadReq hits 459system.cpu.icache.demand_hits 3230 # number of demand (read+write) hits 460system.cpu.icache.overall_hits 3230 # number of overall hits 461system.cpu.icache.ReadReq_misses 855 # number of ReadReq misses 462system.cpu.icache.demand_misses 855 # number of demand (read+write) misses 463system.cpu.icache.overall_misses 855 # number of overall misses 464system.cpu.icache.ReadReq_miss_latency::0 30717000 # number of ReadReq miss cycles 465system.cpu.icache.ReadReq_miss_latency::total 30717000 # number of ReadReq miss cycles 466system.cpu.icache.demand_miss_latency::0 30717000 # number of demand (read+write) miss cycles 467system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles 468system.cpu.icache.demand_miss_latency::total 30717000 # number of demand (read+write) miss cycles 469system.cpu.icache.overall_miss_latency::0 30717000 # number of overall miss cycles 470system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles 471system.cpu.icache.overall_miss_latency::total 30717000 # number of overall miss cycles 472system.cpu.icache.ReadReq_accesses 4085 # number of ReadReq accesses(hits+misses) 473system.cpu.icache.demand_accesses 4085 # number of demand (read+write) accesses 474system.cpu.icache.overall_accesses 4085 # number of overall (read+write) accesses 475system.cpu.icache.ReadReq_miss_rate 0.209302 # miss rate for ReadReq accesses 476system.cpu.icache.demand_miss_rate 0.209302 # miss rate for demand accesses 477system.cpu.icache.overall_miss_rate 0.209302 # miss rate for overall accesses 478system.cpu.icache.ReadReq_avg_miss_latency::0 35926.315789 # average ReadReq miss latency 479system.cpu.icache.ReadReq_avg_miss_latency::total 35926.315789 # average ReadReq miss latency 480system.cpu.icache.demand_avg_miss_latency::0 35926.315789 # average overall miss latency 481system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency 482system.cpu.icache.demand_avg_miss_latency::total 35926.315789 # average overall miss latency 483system.cpu.icache.overall_avg_miss_latency::0 35926.315789 # average overall miss latency 484system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency 485system.cpu.icache.overall_avg_miss_latency::total 35926.315789 # average overall miss latency 486system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 487system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 488system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 489system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 490system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 491system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 492system.cpu.icache.fast_writes 0 # number of fast writes performed 493system.cpu.icache.cache_copies 0 # number of cache copies performed 494system.cpu.icache.writebacks::0 0 # number of writebacks 495system.cpu.icache.writebacks::1 0 # number of writebacks 496system.cpu.icache.writebacks::total 0 # number of writebacks 497system.cpu.icache.ReadReq_mshr_hits::0 229 # number of ReadReq MSHR hits 498system.cpu.icache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits 499system.cpu.icache.demand_mshr_hits::0 229 # number of demand (read+write) MSHR hits 500system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits 501system.cpu.icache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits 502system.cpu.icache.overall_mshr_hits::0 229 # number of overall MSHR hits 503system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits 504system.cpu.icache.overall_mshr_hits::total 229 # number of overall MSHR hits 505system.cpu.icache.ReadReq_mshr_misses::0 626 # number of ReadReq MSHR misses 506system.cpu.icache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses 507system.cpu.icache.demand_mshr_misses::0 626 # number of demand (read+write) MSHR misses 508system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses 509system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses 510system.cpu.icache.overall_mshr_misses::0 626 # number of overall MSHR misses 511system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses 512system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses 513system.cpu.icache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses 514system.cpu.icache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses 515system.cpu.icache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses 516system.cpu.icache.ReadReq_mshr_miss_latency::0 22275500 # number of ReadReq MSHR miss cycles 517system.cpu.icache.ReadReq_mshr_miss_latency::total 22275500 # number of ReadReq MSHR miss cycles 518system.cpu.icache.demand_mshr_miss_latency::0 22275500 # number of demand (read+write) MSHR miss cycles 519system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles 520system.cpu.icache.demand_mshr_miss_latency::total 22275500 # number of demand (read+write) MSHR miss cycles 521system.cpu.icache.overall_mshr_miss_latency::0 22275500 # number of overall MSHR miss cycles 522system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles 523system.cpu.icache.overall_mshr_miss_latency::total 22275500 # number of overall MSHR miss cycles 524system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles 525system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles 526system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles 527system.cpu.icache.ReadReq_mshr_miss_rate::0 0.153244 # mshr miss rate for ReadReq accesses 528system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153244 # mshr miss rate for ReadReq accesses 529system.cpu.icache.demand_mshr_miss_rate::0 0.153244 # mshr miss rate for demand accesses 530system.cpu.icache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 531system.cpu.icache.demand_mshr_miss_rate::total 0.153244 # mshr miss rate for demand accesses 532system.cpu.icache.overall_mshr_miss_rate::0 0.153244 # mshr miss rate for overall accesses 533system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 534system.cpu.icache.overall_mshr_miss_rate::total 0.153244 # mshr miss rate for overall accesses 535system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35583.865815 # average ReadReq mshr miss latency 536system.cpu.icache.demand_avg_mshr_miss_latency::0 35583.865815 # average overall mshr miss latency 537system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 538system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 539system.cpu.icache.overall_avg_mshr_miss_latency::0 35583.865815 # average overall mshr miss latency 540system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 541system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 542system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency 543system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency 544system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency 545system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated 546system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated 547system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated 548system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions 549system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions 550system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions 551system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 552system.cpu.dcache.replacements::0 0 # number of replacements 553system.cpu.dcache.replacements::1 0 # number of replacements 554system.cpu.dcache.replacements::total 0 # number of replacements 555system.cpu.dcache.tagsinuse 216.203520 # Cycle average of tags in use 556system.cpu.dcache.total_refs 4314 # Total number of references to valid blocks. 557system.cpu.dcache.sampled_refs 347 # Sample count of references to valid blocks. 558system.cpu.dcache.avg_refs 12.432277 # Average number of references to valid blocks. 559system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 560system.cpu.dcache.occ_blocks::0 216.203520 # Average occupied blocks per context 561system.cpu.dcache.occ_percent::0 0.052784 # Average percentage of cache occupancy 562system.cpu.dcache.ReadReq_hits 3294 # number of ReadReq hits 563system.cpu.dcache.WriteReq_hits 1020 # number of WriteReq hits 564system.cpu.dcache.demand_hits 4314 # number of demand (read+write) hits 565system.cpu.dcache.overall_hits 4314 # number of overall hits 566system.cpu.dcache.ReadReq_misses 306 # number of ReadReq misses 567system.cpu.dcache.WriteReq_misses 710 # number of WriteReq misses 568system.cpu.dcache.demand_misses 1016 # number of demand (read+write) misses 569system.cpu.dcache.overall_misses 1016 # number of overall misses 570system.cpu.dcache.ReadReq_miss_latency::0 11205000 # number of ReadReq miss cycles 571system.cpu.dcache.ReadReq_miss_latency::total 11205000 # number of ReadReq miss cycles 572system.cpu.dcache.WriteReq_miss_latency::0 24076500 # number of WriteReq miss cycles 573system.cpu.dcache.WriteReq_miss_latency::total 24076500 # number of WriteReq miss cycles 574system.cpu.dcache.demand_miss_latency::0 35281500 # number of demand (read+write) miss cycles 575system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles 576system.cpu.dcache.demand_miss_latency::total 35281500 # number of demand (read+write) miss cycles 577system.cpu.dcache.overall_miss_latency::0 35281500 # number of overall miss cycles 578system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles 579system.cpu.dcache.overall_miss_latency::total 35281500 # number of overall miss cycles 580system.cpu.dcache.ReadReq_accesses 3600 # number of ReadReq accesses(hits+misses) 581system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) 582system.cpu.dcache.demand_accesses 5330 # number of demand (read+write) accesses 583system.cpu.dcache.overall_accesses 5330 # number of overall (read+write) accesses 584system.cpu.dcache.ReadReq_miss_rate 0.085000 # miss rate for ReadReq accesses 585system.cpu.dcache.WriteReq_miss_rate 0.410405 # miss rate for WriteReq accesses 586system.cpu.dcache.demand_miss_rate 0.190619 # miss rate for demand accesses 587system.cpu.dcache.overall_miss_rate 0.190619 # miss rate for overall accesses 588system.cpu.dcache.ReadReq_avg_miss_latency::0 36617.647059 # average ReadReq miss latency 589system.cpu.dcache.ReadReq_avg_miss_latency::total 36617.647059 # average ReadReq miss latency 590system.cpu.dcache.WriteReq_avg_miss_latency::0 33910.563380 # average WriteReq miss latency 591system.cpu.dcache.WriteReq_avg_miss_latency::total 33910.563380 # average WriteReq miss latency 592system.cpu.dcache.demand_avg_miss_latency::0 34725.885827 # average overall miss latency 593system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency 594system.cpu.dcache.demand_avg_miss_latency::total 34725.885827 # average overall miss latency 595system.cpu.dcache.overall_avg_miss_latency::0 34725.885827 # average overall miss latency 596system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency 597system.cpu.dcache.overall_avg_miss_latency::total 34725.885827 # average overall miss latency 598system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 599system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 600system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 601system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 602system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 603system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 604system.cpu.dcache.fast_writes 0 # number of fast writes performed 605system.cpu.dcache.cache_copies 0 # number of cache copies performed 606system.cpu.dcache.writebacks::0 0 # number of writebacks 607system.cpu.dcache.writebacks::1 0 # number of writebacks 608system.cpu.dcache.writebacks::total 0 # number of writebacks 609system.cpu.dcache.ReadReq_mshr_hits::0 105 # number of ReadReq MSHR hits 610system.cpu.dcache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits 611system.cpu.dcache.WriteReq_mshr_hits::0 564 # number of WriteReq MSHR hits 612system.cpu.dcache.WriteReq_mshr_hits::total 564 # number of WriteReq MSHR hits 613system.cpu.dcache.demand_mshr_hits::0 669 # number of demand (read+write) MSHR hits 614system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits 615system.cpu.dcache.demand_mshr_hits::total 669 # number of demand (read+write) MSHR hits 616system.cpu.dcache.overall_mshr_hits::0 669 # number of overall MSHR hits 617system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits 618system.cpu.dcache.overall_mshr_hits::total 669 # number of overall MSHR hits 619system.cpu.dcache.ReadReq_mshr_misses::0 201 # number of ReadReq MSHR misses 620system.cpu.dcache.ReadReq_mshr_misses::total 201 # number of ReadReq MSHR misses 621system.cpu.dcache.WriteReq_mshr_misses::0 146 # number of WriteReq MSHR misses 622system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses 623system.cpu.dcache.demand_mshr_misses::0 347 # number of demand (read+write) MSHR misses 624system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses 625system.cpu.dcache.demand_mshr_misses::total 347 # number of demand (read+write) MSHR misses 626system.cpu.dcache.overall_mshr_misses::0 347 # number of overall MSHR misses 627system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses 628system.cpu.dcache.overall_mshr_misses::total 347 # number of overall MSHR misses 629system.cpu.dcache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses 630system.cpu.dcache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses 631system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses 632system.cpu.dcache.ReadReq_mshr_miss_latency::0 7390000 # number of ReadReq MSHR miss cycles 633system.cpu.dcache.ReadReq_mshr_miss_latency::total 7390000 # number of ReadReq MSHR miss cycles 634system.cpu.dcache.WriteReq_mshr_miss_latency::0 5293000 # number of WriteReq MSHR miss cycles 635system.cpu.dcache.WriteReq_mshr_miss_latency::total 5293000 # number of WriteReq MSHR miss cycles 636system.cpu.dcache.demand_mshr_miss_latency::0 12683000 # number of demand (read+write) MSHR miss cycles 637system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles 638system.cpu.dcache.demand_mshr_miss_latency::total 12683000 # number of demand (read+write) MSHR miss cycles 639system.cpu.dcache.overall_mshr_miss_latency::0 12683000 # number of overall MSHR miss cycles 640system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles 641system.cpu.dcache.overall_mshr_miss_latency::total 12683000 # number of overall MSHR miss cycles 642system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles 643system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles 644system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles 645system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.055833 # mshr miss rate for ReadReq accesses 646system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055833 # mshr miss rate for ReadReq accesses 647system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.084393 # mshr miss rate for WriteReq accesses 648system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 649system.cpu.dcache.demand_mshr_miss_rate::0 0.065103 # mshr miss rate for demand accesses 650system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 651system.cpu.dcache.demand_mshr_miss_rate::total 0.065103 # mshr miss rate for demand accesses 652system.cpu.dcache.overall_mshr_miss_rate::0 0.065103 # mshr miss rate for overall accesses 653system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 654system.cpu.dcache.overall_mshr_miss_rate::total 0.065103 # mshr miss rate for overall accesses 655system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36766.169154 # average ReadReq mshr miss latency 656system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36253.424658 # average WriteReq mshr miss latency 657system.cpu.dcache.demand_avg_mshr_miss_latency::0 36550.432277 # average overall mshr miss latency 658system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 659system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 660system.cpu.dcache.overall_avg_mshr_miss_latency::0 36550.432277 # average overall mshr miss latency 661system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 662system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 663system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency 664system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency 665system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency 666system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated 667system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated 668system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated 669system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions 670system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions 671system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions 672system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 673system.cpu.l2cache.replacements::0 0 # number of replacements 674system.cpu.l2cache.replacements::1 0 # number of replacements 675system.cpu.l2cache.replacements::total 0 # number of replacements 676system.cpu.l2cache.tagsinuse 435.485428 # Cycle average of tags in use 677system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 678system.cpu.l2cache.sampled_refs 825 # Sample count of references to valid blocks. 679system.cpu.l2cache.avg_refs 0.002424 # Average number of references to valid blocks. 680system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 681system.cpu.l2cache.occ_blocks::0 435.485428 # Average occupied blocks per context 682system.cpu.l2cache.occ_percent::0 0.013290 # Average percentage of cache occupancy 683system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits 684system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits 685system.cpu.l2cache.overall_hits 2 # number of overall hits 686system.cpu.l2cache.ReadReq_misses 825 # number of ReadReq misses 687system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses 688system.cpu.l2cache.demand_misses 971 # number of demand (read+write) misses 689system.cpu.l2cache.overall_misses 971 # number of overall misses 690system.cpu.l2cache.ReadReq_miss_latency::0 28485000 # number of ReadReq miss cycles 691system.cpu.l2cache.ReadReq_miss_latency::total 28485000 # number of ReadReq miss cycles 692system.cpu.l2cache.ReadExReq_miss_latency::0 5065500 # number of ReadExReq miss cycles 693system.cpu.l2cache.ReadExReq_miss_latency::total 5065500 # number of ReadExReq miss cycles 694system.cpu.l2cache.demand_miss_latency::0 33550500 # number of demand (read+write) miss cycles 695system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles 696system.cpu.l2cache.demand_miss_latency::total 33550500 # number of demand (read+write) miss cycles 697system.cpu.l2cache.overall_miss_latency::0 33550500 # number of overall miss cycles 698system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles 699system.cpu.l2cache.overall_miss_latency::total 33550500 # number of overall miss cycles 700system.cpu.l2cache.ReadReq_accesses 827 # number of ReadReq accesses(hits+misses) 701system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) 702system.cpu.l2cache.demand_accesses 973 # number of demand (read+write) accesses 703system.cpu.l2cache.overall_accesses 973 # number of overall (read+write) accesses 704system.cpu.l2cache.ReadReq_miss_rate 0.997582 # miss rate for ReadReq accesses 705system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 706system.cpu.l2cache.demand_miss_rate 0.997945 # miss rate for demand accesses 707system.cpu.l2cache.overall_miss_rate 0.997945 # miss rate for overall accesses 708system.cpu.l2cache.ReadReq_avg_miss_latency::0 34527.272727 # average ReadReq miss latency 709system.cpu.l2cache.ReadReq_avg_miss_latency::total 34527.272727 # average ReadReq miss latency 710system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34695.205479 # average ReadExReq miss latency 711system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34695.205479 # average ReadExReq miss latency 712system.cpu.l2cache.demand_avg_miss_latency::0 34552.523172 # average overall miss latency 713system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency 714system.cpu.l2cache.demand_avg_miss_latency::total 34552.523172 # average overall miss latency 715system.cpu.l2cache.overall_avg_miss_latency::0 34552.523172 # average overall miss latency 716system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency 717system.cpu.l2cache.overall_avg_miss_latency::total 34552.523172 # average overall miss latency 718system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked 719system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 720system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked 721system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 722system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5250 # average number of cycles each access was blocked 723system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 724system.cpu.l2cache.fast_writes 0 # number of fast writes performed 725system.cpu.l2cache.cache_copies 0 # number of cache copies performed 726system.cpu.l2cache.writebacks::0 0 # number of writebacks 727system.cpu.l2cache.writebacks::1 0 # number of writebacks 728system.cpu.l2cache.writebacks::total 0 # number of writebacks 729system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits 730system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits 731system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits 732system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits 733system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits 734system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits 735system.cpu.l2cache.ReadReq_mshr_misses::0 825 # number of ReadReq MSHR misses 736system.cpu.l2cache.ReadReq_mshr_misses::total 825 # number of ReadReq MSHR misses 737system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses 738system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses 739system.cpu.l2cache.demand_mshr_misses::0 971 # number of demand (read+write) MSHR misses 740system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses 741system.cpu.l2cache.demand_mshr_misses::total 971 # number of demand (read+write) MSHR misses 742system.cpu.l2cache.overall_mshr_misses::0 971 # number of overall MSHR misses 743system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses 744system.cpu.l2cache.overall_mshr_misses::total 971 # number of overall MSHR misses 745system.cpu.l2cache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses 746system.cpu.l2cache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses 747system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses 748system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25905000 # number of ReadReq MSHR miss cycles 749system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25905000 # number of ReadReq MSHR miss cycles 750system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4613500 # number of ReadExReq MSHR miss cycles 751system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4613500 # number of ReadExReq MSHR miss cycles 752system.cpu.l2cache.demand_mshr_miss_latency::0 30518500 # number of demand (read+write) MSHR miss cycles 753system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles 754system.cpu.l2cache.demand_mshr_miss_latency::total 30518500 # number of demand (read+write) MSHR miss cycles 755system.cpu.l2cache.overall_mshr_miss_latency::0 30518500 # number of overall MSHR miss cycles 756system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles 757system.cpu.l2cache.overall_mshr_miss_latency::total 30518500 # number of overall MSHR miss cycles 758system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles 759system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles 760system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles 761system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997582 # mshr miss rate for ReadReq accesses 762system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997582 # mshr miss rate for ReadReq accesses 763system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses 764system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 765system.cpu.l2cache.demand_mshr_miss_rate::0 0.997945 # mshr miss rate for demand accesses 766system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 767system.cpu.l2cache.demand_mshr_miss_rate::total 0.997945 # mshr miss rate for demand accesses 768system.cpu.l2cache.overall_mshr_miss_rate::0 0.997945 # mshr miss rate for overall accesses 769system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 770system.cpu.l2cache.overall_mshr_miss_rate::total 0.997945 # mshr miss rate for overall accesses 771system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31400 # average ReadReq mshr miss latency 772system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31599.315068 # average ReadExReq mshr miss latency 773system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31429.969104 # average overall mshr miss latency 774system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 775system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 776system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31429.969104 # average overall mshr miss latency 777system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 778system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 779system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency 780system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency 781system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency 782system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated 783system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated 784system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated 785system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions 786system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions 787system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions 788system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 789 790---------- End Simulation Statistics ---------- 791