stats.txt revision 8241
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 136040 # Simulator instruction rate (inst/s) 4host_mem_usage 204288 # Number of bytes of host memory used 5host_seconds 0.09 # Real time elapsed on the host 6host_tick_rate 149415554 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 12773 # Number of instructions simulated 9sim_seconds 0.000014 # Number of seconds simulated 10sim_ticks 14058000 # Number of ticks simulated 11system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 12system.cpu.BPredUnit.BTBHits 845 # Number of BTB hits 13system.cpu.BPredUnit.BTBLookups 4555 # Number of BTB lookups 14system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions. 15system.cpu.BPredUnit.condIncorrect 1551 # Number of conditional branches incorrect 16system.cpu.BPredUnit.condPredicted 3023 # Number of conditional branches predicted 17system.cpu.BPredUnit.lookups 5318 # Number of BP lookups 18system.cpu.BPredUnit.usedRAS 660 # Number of times the RAS was used to get a target. 19system.cpu.commit.branchMispredicts 1135 # The number of times a branch was mispredicted 20system.cpu.commit.branches::0 1051 # Number of branches committed 21system.cpu.commit.branches::1 1051 # Number of branches committed 22system.cpu.commit.branches::total 2102 # Number of branches committed 23system.cpu.commit.bw_lim_events 151 # number cycles where commit BW limit reached 24system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits 25system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits 26system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits 27system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions 28system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards 29system.cpu.commit.commitSquashedInsts 10106 # The number of squashed insts skipped by commit 30system.cpu.commit.committed_per_cycle::samples 22336 # Number of insts commited each cycle 31system.cpu.commit.committed_per_cycle::mean 0.573379 # Number of insts commited each cycle 32system.cpu.commit.committed_per_cycle::stdev 1.337408 # Number of insts commited each cycle 33system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 34system.cpu.commit.committed_per_cycle::0 16656 74.57% 74.57% # Number of insts commited each cycle 35system.cpu.commit.committed_per_cycle::1 2886 12.92% 87.49% # Number of insts commited each cycle 36system.cpu.commit.committed_per_cycle::2 1149 5.14% 92.64% # Number of insts commited each cycle 37system.cpu.commit.committed_per_cycle::3 571 2.56% 95.19% # Number of insts commited each cycle 38system.cpu.commit.committed_per_cycle::4 362 1.62% 96.81% # Number of insts commited each cycle 39system.cpu.commit.committed_per_cycle::5 238 1.07% 97.88% # Number of insts commited each cycle 40system.cpu.commit.committed_per_cycle::6 197 0.88% 98.76% # Number of insts commited each cycle 41system.cpu.commit.committed_per_cycle::7 126 0.56% 99.32% # Number of insts commited each cycle 42system.cpu.commit.committed_per_cycle::8 151 0.68% 100.00% # Number of insts commited each cycle 43system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 44system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 45system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 46system.cpu.commit.committed_per_cycle::total 22336 # Number of insts commited each cycle 47system.cpu.commit.count::0 6404 # Number of instructions committed 48system.cpu.commit.count::1 6403 # Number of instructions committed 49system.cpu.commit.count::total 12807 # Number of instructions committed 50system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. 51system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. 52system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. 53system.cpu.commit.function_calls::0 127 # Number of function calls committed. 54system.cpu.commit.function_calls::1 127 # Number of function calls committed. 55system.cpu.commit.function_calls::total 254 # Number of function calls committed. 56system.cpu.commit.int_insts::0 6321 # Number of committed integer instructions. 57system.cpu.commit.int_insts::1 6321 # Number of committed integer instructions. 58system.cpu.commit.int_insts::total 12642 # Number of committed integer instructions. 59system.cpu.commit.loads::0 1185 # Number of loads committed 60system.cpu.commit.loads::1 1185 # Number of loads committed 61system.cpu.commit.loads::total 2370 # Number of loads committed 62system.cpu.commit.membars::0 0 # Number of memory barriers committed 63system.cpu.commit.membars::1 0 # Number of memory barriers committed 64system.cpu.commit.membars::total 0 # Number of memory barriers committed 65system.cpu.commit.refs::0 2050 # Number of memory references committed 66system.cpu.commit.refs::1 2050 # Number of memory references committed 67system.cpu.commit.refs::total 4100 # Number of memory references committed 68system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 69system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed 70system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed 71system.cpu.committedInsts::0 6387 # Number of Instructions Simulated 72system.cpu.committedInsts::1 6386 # Number of Instructions Simulated 73system.cpu.committedInsts_total 12773 # Number of Instructions Simulated 74system.cpu.cpi::0 4.402223 # CPI: Cycles Per Instruction 75system.cpu.cpi::1 4.402913 # CPI: Cycles Per Instruction 76system.cpu.cpi_total 2.201284 # CPI: Total CPI of All Threads 77system.cpu.dcache.ReadReq_accesses 3727 # number of ReadReq accesses(hits+misses) 78system.cpu.dcache.ReadReq_avg_miss_latency::0 36433.554817 # average ReadReq miss latency 79system.cpu.dcache.ReadReq_avg_miss_latency::total 36433.554817 # average ReadReq miss latency 80system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36821.782178 # average ReadReq mshr miss latency 81system.cpu.dcache.ReadReq_hits 3426 # number of ReadReq hits 82system.cpu.dcache.ReadReq_miss_latency::0 10966500 # number of ReadReq miss cycles 83system.cpu.dcache.ReadReq_miss_latency::total 10966500 # number of ReadReq miss cycles 84system.cpu.dcache.ReadReq_miss_rate 0.080762 # miss rate for ReadReq accesses 85system.cpu.dcache.ReadReq_misses 301 # number of ReadReq misses 86system.cpu.dcache.ReadReq_mshr_hits::0 99 # number of ReadReq MSHR hits 87system.cpu.dcache.ReadReq_mshr_hits::total 99 # number of ReadReq MSHR hits 88system.cpu.dcache.ReadReq_mshr_miss_latency::0 7438000 # number of ReadReq MSHR miss cycles 89system.cpu.dcache.ReadReq_mshr_miss_latency::total 7438000 # number of ReadReq MSHR miss cycles 90system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.054199 # mshr miss rate for ReadReq accesses 91system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054199 # mshr miss rate for ReadReq accesses 92system.cpu.dcache.ReadReq_mshr_misses::0 202 # number of ReadReq MSHR misses 93system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses 94system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) 95system.cpu.dcache.WriteReq_avg_miss_latency::0 32498.595506 # average WriteReq miss latency 96system.cpu.dcache.WriteReq_avg_miss_latency::total 32498.595506 # average WriteReq miss latency 97system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 35993.150685 # average WriteReq mshr miss latency 98system.cpu.dcache.WriteReq_hits 1018 # number of WriteReq hits 99system.cpu.dcache.WriteReq_miss_latency::0 23139000 # number of WriteReq miss cycles 100system.cpu.dcache.WriteReq_miss_latency::total 23139000 # number of WriteReq miss cycles 101system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses 102system.cpu.dcache.WriteReq_misses 712 # number of WriteReq misses 103system.cpu.dcache.WriteReq_mshr_hits::0 566 # number of WriteReq MSHR hits 104system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits 105system.cpu.dcache.WriteReq_mshr_miss_latency::0 5255000 # number of WriteReq MSHR miss cycles 106system.cpu.dcache.WriteReq_mshr_miss_latency::total 5255000 # number of WriteReq MSHR miss cycles 107system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.084393 # mshr miss rate for WriteReq accesses 108system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 109system.cpu.dcache.WriteReq_mshr_misses::0 146 # number of WriteReq MSHR misses 110system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses 111system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 112system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 113system.cpu.dcache.avg_refs 12.770115 # Average number of references to valid blocks. 114system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 115system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 116system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 117system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 118system.cpu.dcache.cache_copies 0 # number of cache copies performed 119system.cpu.dcache.demand_accesses 5457 # number of demand (read+write) accesses 120system.cpu.dcache.demand_avg_miss_latency::0 33667.818361 # average overall miss latency 121system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency 122system.cpu.dcache.demand_avg_miss_latency::total 33667.818361 # average overall miss latency 123system.cpu.dcache.demand_avg_mshr_miss_latency::0 36474.137931 # average overall mshr miss latency 124system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 125system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 126system.cpu.dcache.demand_hits 4444 # number of demand (read+write) hits 127system.cpu.dcache.demand_miss_latency::0 34105500 # number of demand (read+write) miss cycles 128system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles 129system.cpu.dcache.demand_miss_latency::total 34105500 # number of demand (read+write) miss cycles 130system.cpu.dcache.demand_miss_rate 0.185633 # miss rate for demand accesses 131system.cpu.dcache.demand_misses 1013 # number of demand (read+write) misses 132system.cpu.dcache.demand_mshr_hits::0 665 # number of demand (read+write) MSHR hits 133system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits 134system.cpu.dcache.demand_mshr_hits::total 665 # number of demand (read+write) MSHR hits 135system.cpu.dcache.demand_mshr_miss_latency::0 12693000 # number of demand (read+write) MSHR miss cycles 136system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles 137system.cpu.dcache.demand_mshr_miss_latency::total 12693000 # number of demand (read+write) MSHR miss cycles 138system.cpu.dcache.demand_mshr_miss_rate::0 0.063771 # mshr miss rate for demand accesses 139system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 140system.cpu.dcache.demand_mshr_miss_rate::total 0.063771 # mshr miss rate for demand accesses 141system.cpu.dcache.demand_mshr_misses::0 348 # number of demand (read+write) MSHR misses 142system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses 143system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses 144system.cpu.dcache.fast_writes 0 # number of fast writes performed 145system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated 146system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated 147system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated 148system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 149system.cpu.dcache.occ_blocks::0 220.347711 # Average occupied blocks per context 150system.cpu.dcache.occ_percent::0 0.053796 # Average percentage of cache occupancy 151system.cpu.dcache.overall_accesses 5457 # number of overall (read+write) accesses 152system.cpu.dcache.overall_avg_miss_latency::0 33667.818361 # average overall miss latency 153system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency 154system.cpu.dcache.overall_avg_miss_latency::total 33667.818361 # average overall miss latency 155system.cpu.dcache.overall_avg_mshr_miss_latency::0 36474.137931 # average overall mshr miss latency 156system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 157system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 158system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency 159system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency 160system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency 161system.cpu.dcache.overall_hits 4444 # number of overall hits 162system.cpu.dcache.overall_miss_latency::0 34105500 # number of overall miss cycles 163system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles 164system.cpu.dcache.overall_miss_latency::total 34105500 # number of overall miss cycles 165system.cpu.dcache.overall_miss_rate 0.185633 # miss rate for overall accesses 166system.cpu.dcache.overall_misses 1013 # number of overall misses 167system.cpu.dcache.overall_mshr_hits::0 665 # number of overall MSHR hits 168system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits 169system.cpu.dcache.overall_mshr_hits::total 665 # number of overall MSHR hits 170system.cpu.dcache.overall_mshr_miss_latency::0 12693000 # number of overall MSHR miss cycles 171system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles 172system.cpu.dcache.overall_mshr_miss_latency::total 12693000 # number of overall MSHR miss cycles 173system.cpu.dcache.overall_mshr_miss_rate::0 0.063771 # mshr miss rate for overall accesses 174system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 175system.cpu.dcache.overall_mshr_miss_rate::total 0.063771 # mshr miss rate for overall accesses 176system.cpu.dcache.overall_mshr_misses::0 348 # number of overall MSHR misses 177system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses 178system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses 179system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles 180system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles 181system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles 182system.cpu.dcache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses 183system.cpu.dcache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses 184system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses 185system.cpu.dcache.replacements::0 0 # number of replacements 186system.cpu.dcache.replacements::1 0 # number of replacements 187system.cpu.dcache.replacements::total 0 # number of replacements 188system.cpu.dcache.sampled_refs 348 # Sample count of references to valid blocks. 189system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions 190system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions 191system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions 192system.cpu.dcache.tagsinuse 220.347711 # Cycle average of tags in use 193system.cpu.dcache.total_refs 4444 # Total number of references to valid blocks. 194system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 195system.cpu.dcache.writebacks::0 0 # number of writebacks 196system.cpu.dcache.writebacks::1 0 # number of writebacks 197system.cpu.dcache.writebacks::total 0 # number of writebacks 198system.cpu.decode.BlockedCycles 4700 # Number of cycles decode is blocked 199system.cpu.decode.BranchMispred 432 # Number of times decode detected a branch misprediction 200system.cpu.decode.BranchResolved 582 # Number of times decode resolved a branch 201system.cpu.decode.DecodedInsts 26467 # Number of instructions handled by decode 202system.cpu.decode.IdleCycles 33032 # Number of cycles decode is idle 203system.cpu.decode.RunCycles 4744 # Number of cycles decode is running 204system.cpu.decode.SquashCycles 1971 # Number of cycles decode is squashing 205system.cpu.decode.SquashedInsts 600 # Number of squashed instructions handled by decode 206system.cpu.decode.UnblockCycles 114 # Number of cycles decode is unblocking 207system.cpu.dtb.data_accesses 6011 # DTB accesses 208system.cpu.dtb.data_acv 0 # DTB access violations 209system.cpu.dtb.data_hits 5860 # DTB hits 210system.cpu.dtb.data_misses 151 # DTB misses 211system.cpu.dtb.fetch_accesses 0 # ITB accesses 212system.cpu.dtb.fetch_acv 0 # ITB acv 213system.cpu.dtb.fetch_hits 0 # ITB hits 214system.cpu.dtb.fetch_misses 0 # ITB misses 215system.cpu.dtb.read_accesses 3932 # DTB read accesses 216system.cpu.dtb.read_acv 0 # DTB read access violations 217system.cpu.dtb.read_hits 3840 # DTB read hits 218system.cpu.dtb.read_misses 92 # DTB read misses 219system.cpu.dtb.write_accesses 2079 # DTB write accesses 220system.cpu.dtb.write_acv 0 # DTB write access violations 221system.cpu.dtb.write_hits 2020 # DTB write hits 222system.cpu.dtb.write_misses 59 # DTB write misses 223system.cpu.fetch.Branches 5318 # Number of branches that fetch encountered 224system.cpu.fetch.CacheLines 3965 # Number of cache lines fetched 225system.cpu.fetch.Cycles 5044 # Number of cycles fetch has run and was not squashing or blocked 226system.cpu.fetch.IcacheSquashes 575 # Number of outstanding Icache misses that were squashed 227system.cpu.fetch.Insts 29681 # Number of instructions fetch has processed 228system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 229system.cpu.fetch.SquashCycles 1624 # Number of cycles fetch has spent squashing 230system.cpu.fetch.branchRate 0.189138 # Number of branch fetches per cycle 231system.cpu.fetch.icacheStallCycles 3965 # Number of cycles fetch is stalled on an Icache miss 232system.cpu.fetch.predictedBranches 1505 # Number of branches that fetch has predicted taken 233system.cpu.fetch.rate 1.055625 # Number of inst fetches per cycle 234system.cpu.fetch.rateDist::samples 22371 # Number of instructions fetched each cycle (Total) 235system.cpu.fetch.rateDist::mean 1.326762 # Number of instructions fetched each cycle (Total) 236system.cpu.fetch.rateDist::stdev 2.728526 # Number of instructions fetched each cycle (Total) 237system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 238system.cpu.fetch.rateDist::0 17327 77.45% 77.45% # Number of instructions fetched each cycle (Total) 239system.cpu.fetch.rateDist::1 412 1.84% 79.29% # Number of instructions fetched each cycle (Total) 240system.cpu.fetch.rateDist::2 325 1.45% 80.75% # Number of instructions fetched each cycle (Total) 241system.cpu.fetch.rateDist::3 422 1.89% 82.63% # Number of instructions fetched each cycle (Total) 242system.cpu.fetch.rateDist::4 410 1.83% 84.47% # Number of instructions fetched each cycle (Total) 243system.cpu.fetch.rateDist::5 313 1.40% 85.87% # Number of instructions fetched each cycle (Total) 244system.cpu.fetch.rateDist::6 439 1.96% 87.83% # Number of instructions fetched each cycle (Total) 245system.cpu.fetch.rateDist::7 270 1.21% 89.03% # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.rateDist::8 2453 10.97% 100.00% # Number of instructions fetched each cycle (Total) 247system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 250system.cpu.fetch.rateDist::total 22371 # Number of instructions fetched each cycle (Total) 251system.cpu.fp_regfile_reads 16 # number of floating regfile reads 252system.cpu.fp_regfile_writes 4 # number of floating regfile writes 253system.cpu.icache.ReadReq_accesses 3965 # number of ReadReq accesses(hits+misses) 254system.cpu.icache.ReadReq_avg_miss_latency::0 36242.350061 # average ReadReq miss latency 255system.cpu.icache.ReadReq_avg_miss_latency::total 36242.350061 # average ReadReq miss latency 256system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35491.100324 # average ReadReq mshr miss latency 257system.cpu.icache.ReadReq_hits 3148 # number of ReadReq hits 258system.cpu.icache.ReadReq_miss_latency::0 29610000 # number of ReadReq miss cycles 259system.cpu.icache.ReadReq_miss_latency::total 29610000 # number of ReadReq miss cycles 260system.cpu.icache.ReadReq_miss_rate 0.206053 # miss rate for ReadReq accesses 261system.cpu.icache.ReadReq_misses 817 # number of ReadReq misses 262system.cpu.icache.ReadReq_mshr_hits::0 199 # number of ReadReq MSHR hits 263system.cpu.icache.ReadReq_mshr_hits::total 199 # number of ReadReq MSHR hits 264system.cpu.icache.ReadReq_mshr_miss_latency::0 21933500 # number of ReadReq MSHR miss cycles 265system.cpu.icache.ReadReq_mshr_miss_latency::total 21933500 # number of ReadReq MSHR miss cycles 266system.cpu.icache.ReadReq_mshr_miss_rate::0 0.155864 # mshr miss rate for ReadReq accesses 267system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155864 # mshr miss rate for ReadReq accesses 268system.cpu.icache.ReadReq_mshr_misses::0 618 # number of ReadReq MSHR misses 269system.cpu.icache.ReadReq_mshr_misses::total 618 # number of ReadReq MSHR misses 270system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 271system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 272system.cpu.icache.avg_refs 5.093851 # Average number of references to valid blocks. 273system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 274system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 275system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 276system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 277system.cpu.icache.cache_copies 0 # number of cache copies performed 278system.cpu.icache.demand_accesses 3965 # number of demand (read+write) accesses 279system.cpu.icache.demand_avg_miss_latency::0 36242.350061 # average overall miss latency 280system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency 281system.cpu.icache.demand_avg_miss_latency::total 36242.350061 # average overall miss latency 282system.cpu.icache.demand_avg_mshr_miss_latency::0 35491.100324 # average overall mshr miss latency 283system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 284system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 285system.cpu.icache.demand_hits 3148 # number of demand (read+write) hits 286system.cpu.icache.demand_miss_latency::0 29610000 # number of demand (read+write) miss cycles 287system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles 288system.cpu.icache.demand_miss_latency::total 29610000 # number of demand (read+write) miss cycles 289system.cpu.icache.demand_miss_rate 0.206053 # miss rate for demand accesses 290system.cpu.icache.demand_misses 817 # number of demand (read+write) misses 291system.cpu.icache.demand_mshr_hits::0 199 # number of demand (read+write) MSHR hits 292system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits 293system.cpu.icache.demand_mshr_hits::total 199 # number of demand (read+write) MSHR hits 294system.cpu.icache.demand_mshr_miss_latency::0 21933500 # number of demand (read+write) MSHR miss cycles 295system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles 296system.cpu.icache.demand_mshr_miss_latency::total 21933500 # number of demand (read+write) MSHR miss cycles 297system.cpu.icache.demand_mshr_miss_rate::0 0.155864 # mshr miss rate for demand accesses 298system.cpu.icache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 299system.cpu.icache.demand_mshr_miss_rate::total 0.155864 # mshr miss rate for demand accesses 300system.cpu.icache.demand_mshr_misses::0 618 # number of demand (read+write) MSHR misses 301system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses 302system.cpu.icache.demand_mshr_misses::total 618 # number of demand (read+write) MSHR misses 303system.cpu.icache.fast_writes 0 # number of fast writes performed 304system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated 305system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated 306system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated 307system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 308system.cpu.icache.occ_blocks::0 318.780075 # Average occupied blocks per context 309system.cpu.icache.occ_percent::0 0.155654 # Average percentage of cache occupancy 310system.cpu.icache.overall_accesses 3965 # number of overall (read+write) accesses 311system.cpu.icache.overall_avg_miss_latency::0 36242.350061 # average overall miss latency 312system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency 313system.cpu.icache.overall_avg_miss_latency::total 36242.350061 # average overall miss latency 314system.cpu.icache.overall_avg_mshr_miss_latency::0 35491.100324 # average overall mshr miss latency 315system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 316system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 317system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency 318system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency 319system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency 320system.cpu.icache.overall_hits 3148 # number of overall hits 321system.cpu.icache.overall_miss_latency::0 29610000 # number of overall miss cycles 322system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles 323system.cpu.icache.overall_miss_latency::total 29610000 # number of overall miss cycles 324system.cpu.icache.overall_miss_rate 0.206053 # miss rate for overall accesses 325system.cpu.icache.overall_misses 817 # number of overall misses 326system.cpu.icache.overall_mshr_hits::0 199 # number of overall MSHR hits 327system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits 328system.cpu.icache.overall_mshr_hits::total 199 # number of overall MSHR hits 329system.cpu.icache.overall_mshr_miss_latency::0 21933500 # number of overall MSHR miss cycles 330system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles 331system.cpu.icache.overall_mshr_miss_latency::total 21933500 # number of overall MSHR miss cycles 332system.cpu.icache.overall_mshr_miss_rate::0 0.155864 # mshr miss rate for overall accesses 333system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 334system.cpu.icache.overall_mshr_miss_rate::total 0.155864 # mshr miss rate for overall accesses 335system.cpu.icache.overall_mshr_misses::0 618 # number of overall MSHR misses 336system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses 337system.cpu.icache.overall_mshr_misses::total 618 # number of overall MSHR misses 338system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles 339system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles 340system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles 341system.cpu.icache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses 342system.cpu.icache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses 343system.cpu.icache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses 344system.cpu.icache.replacements::0 6 # number of replacements 345system.cpu.icache.replacements::1 0 # number of replacements 346system.cpu.icache.replacements::total 6 # number of replacements 347system.cpu.icache.sampled_refs 618 # Sample count of references to valid blocks. 348system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions 349system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions 350system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions 351system.cpu.icache.tagsinuse 318.780075 # Cycle average of tags in use 352system.cpu.icache.total_refs 3148 # Total number of references to valid blocks. 353system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 354system.cpu.icache.writebacks::0 0 # number of writebacks 355system.cpu.icache.writebacks::1 0 # number of writebacks 356system.cpu.icache.writebacks::total 0 # number of writebacks 357system.cpu.idleCycles 5746 # Total number of cycles that the CPU has spent unscheduled due to idling 358system.cpu.iew.branchMispredicts 1313 # Number of branch mispredicts detected at execute 359system.cpu.iew.exec_branches::0 1549 # Number of branches executed 360system.cpu.iew.exec_branches::1 1545 # Number of branches executed 361system.cpu.iew.exec_branches::total 3094 # Number of branches executed 362system.cpu.iew.exec_nop::0 67 # number of nop insts executed 363system.cpu.iew.exec_nop::1 70 # number of nop insts executed 364system.cpu.iew.exec_nop::total 137 # number of nop insts executed 365system.cpu.iew.exec_rate 0.665505 # Inst execution rate 366system.cpu.iew.exec_refs::0 3042 # number of memory reference insts executed 367system.cpu.iew.exec_refs::1 2988 # number of memory reference insts executed 368system.cpu.iew.exec_refs::total 6030 # number of memory reference insts executed 369system.cpu.iew.exec_stores::0 1059 # Number of stores executed 370system.cpu.iew.exec_stores::1 1037 # Number of stores executed 371system.cpu.iew.exec_stores::total 2096 # Number of stores executed 372system.cpu.iew.exec_swp::0 0 # number of swp insts executed 373system.cpu.iew.exec_swp::1 0 # number of swp insts executed 374system.cpu.iew.exec_swp::total 0 # number of swp insts executed 375system.cpu.iew.iewBlockCycles 965 # Number of cycles IEW is blocking 376system.cpu.iew.iewDispLoadInsts 4691 # Number of dispatched load instructions 377system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions 378system.cpu.iew.iewDispSquashedInsts 813 # Number of squashed instructions skipped by dispatch 379system.cpu.iew.iewDispStoreInsts 2450 # Number of dispatched store instructions 380system.cpu.iew.iewDispatchedInsts 22978 # Number of instructions dispatched to IQ 381system.cpu.iew.iewExecLoadInsts::0 1983 # Number of load instructions executed 382system.cpu.iew.iewExecLoadInsts::1 1951 # Number of load instructions executed 383system.cpu.iew.iewExecLoadInsts::total 3934 # Number of load instructions executed 384system.cpu.iew.iewExecSquashedInsts 1099 # Number of squashed instructions skipped in execute 385system.cpu.iew.iewExecutedInsts 18712 # Number of executed instructions 386system.cpu.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall 387system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 388system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall 389system.cpu.iew.iewSquashCycles 1971 # Number of cycles IEW is squashing 390system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking 391system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 392system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 393system.cpu.iew.lsq.thread.0.forwLoads 56 # Number of loads that had data forwarded from stores 394system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 395system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 396system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 397system.cpu.iew.lsq.thread.0.memOrderViolation 15 # Number of memory ordering violations 398system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled 399system.cpu.iew.lsq.thread.0.squashedLoads 1178 # Number of loads squashed 400system.cpu.iew.lsq.thread.0.squashedStores 386 # Number of stores squashed 401system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 402system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 403system.cpu.iew.lsq.thread.1.forwLoads 55 # Number of loads that had data forwarded from stores 404system.cpu.iew.lsq.thread.1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed 405system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address 406system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 407system.cpu.iew.lsq.thread.1.memOrderViolation 13 # Number of memory ordering violations 408system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled 409system.cpu.iew.lsq.thread.1.squashedLoads 1143 # Number of loads squashed 410system.cpu.iew.lsq.thread.1.squashedStores 334 # Number of stores squashed 411system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations 412system.cpu.iew.predictedNotTakenIncorrect 1056 # Number of branches that were predicted not taken incorrectly 413system.cpu.iew.predictedTakenIncorrect 257 # Number of branches that were predicted taken incorrectly 414system.cpu.iew.wb_consumers::0 5857 # num instructions consuming a value 415system.cpu.iew.wb_consumers::1 5876 # num instructions consuming a value 416system.cpu.iew.wb_consumers::total 11733 # num instructions consuming a value 417system.cpu.iew.wb_count::0 9007 # cumulative count of insts written-back 418system.cpu.iew.wb_count::1 9010 # cumulative count of insts written-back 419system.cpu.iew.wb_count::total 18017 # cumulative count of insts written-back 420system.cpu.iew.wb_fanout::0 0.769336 # average fanout of values written-back 421system.cpu.iew.wb_fanout::1 0.769401 # average fanout of values written-back 422system.cpu.iew.wb_fanout::total 1.538737 # average fanout of values written-back 423system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ 424system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ 425system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ 426system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ 427system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ 428system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ 429system.cpu.iew.wb_producers::0 4506 # num instructions producing a value 430system.cpu.iew.wb_producers::1 4521 # num instructions producing a value 431system.cpu.iew.wb_producers::total 9027 # num instructions producing a value 432system.cpu.iew.wb_rate::0 0.320340 # insts written-back per cycle 433system.cpu.iew.wb_rate::1 0.320447 # insts written-back per cycle 434system.cpu.iew.wb_rate::total 0.640787 # insts written-back per cycle 435system.cpu.iew.wb_sent::0 9150 # cumulative count of insts sent to commit 436system.cpu.iew.wb_sent::1 9113 # cumulative count of insts sent to commit 437system.cpu.iew.wb_sent::total 18263 # cumulative count of insts sent to commit 438system.cpu.int_regfile_reads 23704 # number of integer regfile reads 439system.cpu.int_regfile_writes 13551 # number of integer regfile writes 440system.cpu.ipc::0 0.227158 # IPC: Instructions Per Cycle 441system.cpu.ipc::1 0.227122 # IPC: Instructions Per Cycle 442system.cpu.ipc_total 0.454280 # IPC: Total IPC of All Threads 443system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 444system.cpu.iq.FU_type_0::IntAlu 6672 67.35% 67.37% # Type of FU issued 445system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.38% # Type of FU issued 446system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.38% # Type of FU issued 447system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.40% # Type of FU issued 448system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.40% # Type of FU issued 449system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.40% # Type of FU issued 450system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.40% # Type of FU issued 451system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.40% # Type of FU issued 452system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.40% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.40% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.40% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.40% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.40% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.40% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.40% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.40% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.40% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.40% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.40% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.40% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.40% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.40% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.40% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.40% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.40% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.40% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.40% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.40% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.40% # Type of FU issued 473system.cpu.iq.FU_type_0::MemRead 2121 21.41% 88.81% # Type of FU issued 474system.cpu.iq.FU_type_0::MemWrite 1109 11.19% 100.00% # Type of FU issued 475system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 476system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 477system.cpu.iq.FU_type_0::total 9907 # Type of FU issued 478system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued 479system.cpu.iq.FU_type_1::IntAlu 6738 68.03% 68.05% # Type of FU issued 480system.cpu.iq.FU_type_1::IntMult 1 0.01% 68.06% # Type of FU issued 481system.cpu.iq.FU_type_1::IntDiv 0 0.00% 68.06% # Type of FU issued 482system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 68.08% # Type of FU issued 483system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 68.08% # Type of FU issued 484system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 68.08% # Type of FU issued 485system.cpu.iq.FU_type_1::FloatMult 0 0.00% 68.08% # Type of FU issued 486system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 68.08% # Type of FU issued 487system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 68.08% # Type of FU issued 488system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 68.08% # Type of FU issued 489system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 68.08% # Type of FU issued 490system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 68.08% # Type of FU issued 491system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 68.08% # Type of FU issued 492system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 68.08% # Type of FU issued 493system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 68.08% # Type of FU issued 494system.cpu.iq.FU_type_1::SimdMult 0 0.00% 68.08% # Type of FU issued 495system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 68.08% # Type of FU issued 496system.cpu.iq.FU_type_1::SimdShift 0 0.00% 68.08% # Type of FU issued 497system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued 498system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 68.08% # Type of FU issued 499system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 68.08% # Type of FU issued 500system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued 501system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 68.08% # Type of FU issued 502system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 68.08% # Type of FU issued 503system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued 504system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 68.08% # Type of FU issued 505system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 68.08% # Type of FU issued 506system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 68.08% # Type of FU issued 507system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 68.08% # Type of FU issued 508system.cpu.iq.FU_type_1::MemRead 2064 20.84% 88.92% # Type of FU issued 509system.cpu.iq.FU_type_1::MemWrite 1097 11.08% 100.00% # Type of FU issued 510system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 511system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued 512system.cpu.iq.FU_type_1::total 9904 # Type of FU issued 513system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued 514system.cpu.iq.FU_type::IntAlu 13410 67.69% 67.71% # Type of FU issued 515system.cpu.iq.FU_type::IntMult 2 0.01% 67.72% # Type of FU issued 516system.cpu.iq.FU_type::IntDiv 0 0.00% 67.72% # Type of FU issued 517system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.74% # Type of FU issued 518system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.74% # Type of FU issued 519system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.74% # Type of FU issued 520system.cpu.iq.FU_type::FloatMult 0 0.00% 67.74% # Type of FU issued 521system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.74% # Type of FU issued 522system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.74% # Type of FU issued 523system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.74% # Type of FU issued 524system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.74% # Type of FU issued 525system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.74% # Type of FU issued 526system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.74% # Type of FU issued 527system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.74% # Type of FU issued 528system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.74% # Type of FU issued 529system.cpu.iq.FU_type::SimdMult 0 0.00% 67.74% # Type of FU issued 530system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.74% # Type of FU issued 531system.cpu.iq.FU_type::SimdShift 0 0.00% 67.74% # Type of FU issued 532system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.74% # Type of FU issued 533system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.74% # Type of FU issued 534system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.74% # Type of FU issued 535system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.74% # Type of FU issued 536system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.74% # Type of FU issued 537system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.74% # Type of FU issued 538system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.74% # Type of FU issued 539system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.74% # Type of FU issued 540system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.74% # Type of FU issued 541system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.74% # Type of FU issued 542system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.74% # Type of FU issued 543system.cpu.iq.FU_type::MemRead 4185 21.12% 88.86% # Type of FU issued 544system.cpu.iq.FU_type::MemWrite 2206 11.14% 100.00% # Type of FU issued 545system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued 546system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued 547system.cpu.iq.FU_type::total 19811 # Type of FU issued 548system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses 549system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads 550system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses 551system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 552system.cpu.iq.fu_busy_cnt::0 76 # FU busy when requested 553system.cpu.iq.fu_busy_cnt::1 88 # FU busy when requested 554system.cpu.iq.fu_busy_cnt::total 164 # FU busy when requested 555system.cpu.iq.fu_busy_rate::0 0.003836 # FU busy rate (busy events/executed inst) 556system.cpu.iq.fu_busy_rate::1 0.004442 # FU busy rate (busy events/executed inst) 557system.cpu.iq.fu_busy_rate::total 0.008278 # FU busy rate (busy events/executed inst) 558system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 559system.cpu.iq.fu_full::IntAlu 10 6.10% 6.10% # attempts to use FU when none available 560system.cpu.iq.fu_full::IntMult 0 0.00% 6.10% # attempts to use FU when none available 561system.cpu.iq.fu_full::IntDiv 0 0.00% 6.10% # attempts to use FU when none available 562system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.10% # attempts to use FU when none available 563system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.10% # attempts to use FU when none available 564system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.10% # attempts to use FU when none available 565system.cpu.iq.fu_full::FloatMult 0 0.00% 6.10% # attempts to use FU when none available 566system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.10% # attempts to use FU when none available 567system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.10% # attempts to use FU when none available 568system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.10% # attempts to use FU when none available 569system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.10% # attempts to use FU when none available 570system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.10% # attempts to use FU when none available 571system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.10% # attempts to use FU when none available 572system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.10% # attempts to use FU when none available 573system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.10% # attempts to use FU when none available 574system.cpu.iq.fu_full::SimdMult 0 0.00% 6.10% # attempts to use FU when none available 575system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.10% # attempts to use FU when none available 576system.cpu.iq.fu_full::SimdShift 0 0.00% 6.10% # attempts to use FU when none available 577system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.10% # attempts to use FU when none available 578system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.10% # attempts to use FU when none available 579system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.10% # attempts to use FU when none available 580system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.10% # attempts to use FU when none available 581system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.10% # attempts to use FU when none available 582system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.10% # attempts to use FU when none available 583system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.10% # attempts to use FU when none available 584system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.10% # attempts to use FU when none available 585system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.10% # attempts to use FU when none available 586system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.10% # attempts to use FU when none available 587system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.10% # attempts to use FU when none available 588system.cpu.iq.fu_full::MemRead 90 54.88% 60.98% # attempts to use FU when none available 589system.cpu.iq.fu_full::MemWrite 64 39.02% 100.00% # attempts to use FU when none available 590system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 591system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 592system.cpu.iq.int_alu_accesses 19949 # Number of integer alu accesses 593system.cpu.iq.int_inst_queue_reads 62191 # Number of integer instruction queue reads 594system.cpu.iq.int_inst_queue_wakeup_accesses 17997 # Number of integer instruction queue wakeup accesses 595system.cpu.iq.int_inst_queue_writes 31607 # Number of integer instruction queue writes 596system.cpu.iq.iqInstsAdded 22795 # Number of instructions added to the IQ (excludes non-spec) 597system.cpu.iq.iqInstsIssued 19811 # Number of instructions issued 598system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ 599system.cpu.iq.iqSquashedInstsExamined 8766 # Number of squashed instructions iterated over during squash; mainly for profiling 600system.cpu.iq.iqSquashedInstsIssued 76 # Number of squashed instructions issued 601system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 602system.cpu.iq.iqSquashedOperandsExamined 4974 # Number of squashed operands that are examined and possibly removed from graph 603system.cpu.iq.issued_per_cycle::samples 22371 # Number of insts issued each cycle 604system.cpu.iq.issued_per_cycle::mean 0.885566 # Number of insts issued each cycle 605system.cpu.iq.issued_per_cycle::stdev 1.449509 # Number of insts issued each cycle 606system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 607system.cpu.iq.issued_per_cycle::0 13920 62.22% 62.22% # Number of insts issued each cycle 608system.cpu.iq.issued_per_cycle::1 3143 14.05% 76.27% # Number of insts issued each cycle 609system.cpu.iq.issued_per_cycle::2 2295 10.26% 86.53% # Number of insts issued each cycle 610system.cpu.iq.issued_per_cycle::3 1308 5.85% 92.38% # Number of insts issued each cycle 611system.cpu.iq.issued_per_cycle::4 818 3.66% 96.04% # Number of insts issued each cycle 612system.cpu.iq.issued_per_cycle::5 557 2.49% 98.52% # Number of insts issued each cycle 613system.cpu.iq.issued_per_cycle::6 231 1.03% 99.56% # Number of insts issued each cycle 614system.cpu.iq.issued_per_cycle::7 81 0.36% 99.92% # Number of insts issued each cycle 615system.cpu.iq.issued_per_cycle::8 18 0.08% 100.00% # Number of insts issued each cycle 616system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 617system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 618system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 619system.cpu.iq.issued_per_cycle::total 22371 # Number of insts issued each cycle 620system.cpu.iq.rate 0.704592 # Inst issue rate 621system.cpu.itb.data_accesses 0 # DTB accesses 622system.cpu.itb.data_acv 0 # DTB access violations 623system.cpu.itb.data_hits 0 # DTB hits 624system.cpu.itb.data_misses 0 # DTB misses 625system.cpu.itb.fetch_accesses 4020 # ITB accesses 626system.cpu.itb.fetch_acv 0 # ITB acv 627system.cpu.itb.fetch_hits 3965 # ITB hits 628system.cpu.itb.fetch_misses 55 # ITB misses 629system.cpu.itb.read_accesses 0 # DTB read accesses 630system.cpu.itb.read_acv 0 # DTB read access violations 631system.cpu.itb.read_hits 0 # DTB read hits 632system.cpu.itb.read_misses 0 # DTB read misses 633system.cpu.itb.write_accesses 0 # DTB write accesses 634system.cpu.itb.write_acv 0 # DTB write access violations 635system.cpu.itb.write_hits 0 # DTB write hits 636system.cpu.itb.write_misses 0 # DTB write misses 637system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) 638system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34506.849315 # average ReadExReq miss latency 639system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34506.849315 # average ReadExReq miss latency 640system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31441.780822 # average ReadExReq mshr miss latency 641system.cpu.l2cache.ReadExReq_miss_latency::0 5038000 # number of ReadExReq miss cycles 642system.cpu.l2cache.ReadExReq_miss_latency::total 5038000 # number of ReadExReq miss cycles 643system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 644system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses 645system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4590500 # number of ReadExReq MSHR miss cycles 646system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4590500 # number of ReadExReq MSHR miss cycles 647system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses 648system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 649system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses 650system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses 651system.cpu.l2cache.ReadReq_accesses 820 # number of ReadReq accesses(hits+misses) 652system.cpu.l2cache.ReadReq_avg_miss_latency::0 34518.948655 # average ReadReq miss latency 653system.cpu.l2cache.ReadReq_avg_miss_latency::total 34518.948655 # average ReadReq miss latency 654system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31380.195599 # average ReadReq mshr miss latency 655system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits 656system.cpu.l2cache.ReadReq_miss_latency::0 28236500 # number of ReadReq miss cycles 657system.cpu.l2cache.ReadReq_miss_latency::total 28236500 # number of ReadReq miss cycles 658system.cpu.l2cache.ReadReq_miss_rate 0.997561 # miss rate for ReadReq accesses 659system.cpu.l2cache.ReadReq_misses 818 # number of ReadReq misses 660system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25669000 # number of ReadReq MSHR miss cycles 661system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25669000 # number of ReadReq MSHR miss cycles 662system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997561 # mshr miss rate for ReadReq accesses 663system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997561 # mshr miss rate for ReadReq accesses 664system.cpu.l2cache.ReadReq_mshr_misses::0 818 # number of ReadReq MSHR misses 665system.cpu.l2cache.ReadReq_mshr_misses::total 818 # number of ReadReq MSHR misses 666system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6750 # average number of cycles each access was blocked 667system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 668system.cpu.l2cache.avg_refs 0.002445 # Average number of references to valid blocks. 669system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked 670system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 671system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked 672system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 673system.cpu.l2cache.cache_copies 0 # number of cache copies performed 674system.cpu.l2cache.demand_accesses 966 # number of demand (read+write) accesses 675system.cpu.l2cache.demand_avg_miss_latency::0 34517.116183 # average overall miss latency 676system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency 677system.cpu.l2cache.demand_avg_miss_latency::total 34517.116183 # average overall miss latency 678system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31389.522822 # average overall mshr miss latency 679system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 680system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 681system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits 682system.cpu.l2cache.demand_miss_latency::0 33274500 # number of demand (read+write) miss cycles 683system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles 684system.cpu.l2cache.demand_miss_latency::total 33274500 # number of demand (read+write) miss cycles 685system.cpu.l2cache.demand_miss_rate 0.997930 # miss rate for demand accesses 686system.cpu.l2cache.demand_misses 964 # number of demand (read+write) misses 687system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits 688system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits 689system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits 690system.cpu.l2cache.demand_mshr_miss_latency::0 30259500 # number of demand (read+write) MSHR miss cycles 691system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles 692system.cpu.l2cache.demand_mshr_miss_latency::total 30259500 # number of demand (read+write) MSHR miss cycles 693system.cpu.l2cache.demand_mshr_miss_rate::0 0.997930 # mshr miss rate for demand accesses 694system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 695system.cpu.l2cache.demand_mshr_miss_rate::total 0.997930 # mshr miss rate for demand accesses 696system.cpu.l2cache.demand_mshr_misses::0 964 # number of demand (read+write) MSHR misses 697system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses 698system.cpu.l2cache.demand_mshr_misses::total 964 # number of demand (read+write) MSHR misses 699system.cpu.l2cache.fast_writes 0 # number of fast writes performed 700system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated 701system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated 702system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated 703system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 704system.cpu.l2cache.occ_blocks::0 441.662390 # Average occupied blocks per context 705system.cpu.l2cache.occ_percent::0 0.013478 # Average percentage of cache occupancy 706system.cpu.l2cache.overall_accesses 966 # number of overall (read+write) accesses 707system.cpu.l2cache.overall_avg_miss_latency::0 34517.116183 # average overall miss latency 708system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency 709system.cpu.l2cache.overall_avg_miss_latency::total 34517.116183 # average overall miss latency 710system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31389.522822 # average overall mshr miss latency 711system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 712system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 713system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency 714system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency 715system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency 716system.cpu.l2cache.overall_hits 2 # number of overall hits 717system.cpu.l2cache.overall_miss_latency::0 33274500 # number of overall miss cycles 718system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles 719system.cpu.l2cache.overall_miss_latency::total 33274500 # number of overall miss cycles 720system.cpu.l2cache.overall_miss_rate 0.997930 # miss rate for overall accesses 721system.cpu.l2cache.overall_misses 964 # number of overall misses 722system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits 723system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits 724system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits 725system.cpu.l2cache.overall_mshr_miss_latency::0 30259500 # number of overall MSHR miss cycles 726system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles 727system.cpu.l2cache.overall_mshr_miss_latency::total 30259500 # number of overall MSHR miss cycles 728system.cpu.l2cache.overall_mshr_miss_rate::0 0.997930 # mshr miss rate for overall accesses 729system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 730system.cpu.l2cache.overall_mshr_miss_rate::total 0.997930 # mshr miss rate for overall accesses 731system.cpu.l2cache.overall_mshr_misses::0 964 # number of overall MSHR misses 732system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses 733system.cpu.l2cache.overall_mshr_misses::total 964 # number of overall MSHR misses 734system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles 735system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles 736system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles 737system.cpu.l2cache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses 738system.cpu.l2cache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses 739system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses 740system.cpu.l2cache.replacements::0 0 # number of replacements 741system.cpu.l2cache.replacements::1 0 # number of replacements 742system.cpu.l2cache.replacements::total 0 # number of replacements 743system.cpu.l2cache.sampled_refs 818 # Sample count of references to valid blocks. 744system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions 745system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions 746system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions 747system.cpu.l2cache.tagsinuse 441.662390 # Cycle average of tags in use 748system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 749system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 750system.cpu.l2cache.writebacks::0 0 # number of writebacks 751system.cpu.l2cache.writebacks::1 0 # number of writebacks 752system.cpu.l2cache.writebacks::total 0 # number of writebacks 753system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. 754system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 755system.cpu.memDep0.insertedLoads 2363 # Number of loads inserted to the mem dependence unit. 756system.cpu.memDep0.insertedStores 1251 # Number of stores inserted to the mem dependence unit. 757system.cpu.memDep1.conflictingLoads 0 # Number of conflicting loads. 758system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. 759system.cpu.memDep1.insertedLoads 2328 # Number of loads inserted to the mem dependence unit. 760system.cpu.memDep1.insertedStores 1199 # Number of stores inserted to the mem dependence unit. 761system.cpu.misc_regfile_reads 2 # number of misc regfile reads 762system.cpu.misc_regfile_writes 2 # number of misc regfile writes 763system.cpu.numCycles 28117 # number of cpu cycles simulated 764system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 765system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 766system.cpu.rename.BlockCycles 2820 # Number of cycles rename is blocking 767system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed 768system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 769system.cpu.rename.IdleCycles 33480 # Number of cycles rename is idle 770system.cpu.rename.LSQFullEvents 1251 # Number of times rename has blocked due to LSQ full 771system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 772system.cpu.rename.RenameLookups 31536 # Number of register rename lookups that rename has made 773system.cpu.rename.RenamedInsts 25241 # Number of instructions processed by rename 774system.cpu.rename.RenamedOperands 18899 # Number of destination operands rename has renamed 775system.cpu.rename.RunCycles 4323 # Number of cycles rename is running 776system.cpu.rename.SquashCycles 1971 # Number of cycles rename is squashing 777system.cpu.rename.UnblockCycles 1300 # Number of cycles rename is unblocking 778system.cpu.rename.UndoneMaps 9733 # Number of HB maps that are undone due to squashing 779system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups 780system.cpu.rename.int_rename_lookups 31502 # Number of integer rename lookups 781system.cpu.rename.serializeStallCycles 667 # count of cycles rename stalled for serializing inst 782system.cpu.rename.serializingInsts 50 # count of serializing insts renamed 783system.cpu.rename.skidInsts 3351 # count of insts added to the skid buffer 784system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 785system.cpu.rob.rob_reads 106938 # The number of ROB reads 786system.cpu.rob.rob_writes 47804 # The number of ROB writes 787system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself 788system.cpu.workload0.num_syscalls 17 # Number of system calls 789system.cpu.workload1.num_syscalls 17 # Number of system calls 790 791---------- End Simulation Statistics ---------- 792