stats.txt revision 9978
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000024 # Number of seconds simulated 4sim_ticks 24229500 # Number of ticks simulated 5final_tick 24229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 81251 # Simulator instruction rate (inst/s) 8host_op_rate 81244 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 154440285 # Simulator tick rate (ticks/s) 10host_mem_usage 227736 # Number of bytes of host memory used 11host_seconds 0.16 # Real time elapsed on the host 12sim_insts 12745 # Number of instructions simulated 13sim_ops 12745 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 22464 # Number of bytes read from this memory 16system.physmem.bytes_read::total 62400 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 39936 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 39936 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 624 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 351 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 975 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1648238717 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 927134278 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2575372996 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1648238717 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1648238717 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1648238717 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 927134278 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2575372996 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 975 # Number of read requests accepted 31system.physmem.writeReqs 0 # Number of write requests accepted 32system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue 33system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 34system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM 35system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 36system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 37system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side 38system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 39system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 40system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 41system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 42system.physmem.perBankRdBursts::0 82 # Per bank write bursts 43system.physmem.perBankRdBursts::1 153 # Per bank write bursts 44system.physmem.perBankRdBursts::2 77 # Per bank write bursts 45system.physmem.perBankRdBursts::3 60 # Per bank write bursts 46system.physmem.perBankRdBursts::4 87 # Per bank write bursts 47system.physmem.perBankRdBursts::5 49 # Per bank write bursts 48system.physmem.perBankRdBursts::6 32 # Per bank write bursts 49system.physmem.perBankRdBursts::7 49 # Per bank write bursts 50system.physmem.perBankRdBursts::8 42 # Per bank write bursts 51system.physmem.perBankRdBursts::9 39 # Per bank write bursts 52system.physmem.perBankRdBursts::10 30 # Per bank write bursts 53system.physmem.perBankRdBursts::11 33 # Per bank write bursts 54system.physmem.perBankRdBursts::12 15 # Per bank write bursts 55system.physmem.perBankRdBursts::13 121 # Per bank write bursts 56system.physmem.perBankRdBursts::14 70 # Per bank write bursts 57system.physmem.perBankRdBursts::15 36 # Per bank write bursts 58system.physmem.perBankWrBursts::0 0 # Per bank write bursts 59system.physmem.perBankWrBursts::1 0 # Per bank write bursts 60system.physmem.perBankWrBursts::2 0 # Per bank write bursts 61system.physmem.perBankWrBursts::3 0 # Per bank write bursts 62system.physmem.perBankWrBursts::4 0 # Per bank write bursts 63system.physmem.perBankWrBursts::5 0 # Per bank write bursts 64system.physmem.perBankWrBursts::6 0 # Per bank write bursts 65system.physmem.perBankWrBursts::7 0 # Per bank write bursts 66system.physmem.perBankWrBursts::8 0 # Per bank write bursts 67system.physmem.perBankWrBursts::9 0 # Per bank write bursts 68system.physmem.perBankWrBursts::10 0 # Per bank write bursts 69system.physmem.perBankWrBursts::11 0 # Per bank write bursts 70system.physmem.perBankWrBursts::12 0 # Per bank write bursts 71system.physmem.perBankWrBursts::13 0 # Per bank write bursts 72system.physmem.perBankWrBursts::14 0 # Per bank write bursts 73system.physmem.perBankWrBursts::15 0 # Per bank write bursts 74system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 75system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 76system.physmem.totGap 24081000 # Total gap between requests 77system.physmem.readPktSize::0 0 # Read request sizes (log2) 78system.physmem.readPktSize::1 0 # Read request sizes (log2) 79system.physmem.readPktSize::2 0 # Read request sizes (log2) 80system.physmem.readPktSize::3 0 # Read request sizes (log2) 81system.physmem.readPktSize::4 0 # Read request sizes (log2) 82system.physmem.readPktSize::5 0 # Read request sizes (log2) 83system.physmem.readPktSize::6 975 # Read request sizes (log2) 84system.physmem.writePktSize::0 0 # Write request sizes (log2) 85system.physmem.writePktSize::1 0 # Write request sizes (log2) 86system.physmem.writePktSize::2 0 # Write request sizes (log2) 87system.physmem.writePktSize::3 0 # Write request sizes (log2) 88system.physmem.writePktSize::4 0 # Write request sizes (log2) 89system.physmem.writePktSize::5 0 # Write request sizes (log2) 90system.physmem.writePktSize::6 0 # Write request sizes (log2) 91system.physmem.rdQLenPdf::0 344 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::1 370 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::3 70 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 123system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 155system.physmem.bytesPerActivate::samples 217 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::mean 271.926267 # Bytes accessed per row activation 157system.physmem.bytesPerActivate::gmean 156.688517 # Bytes accessed per row activation 158system.physmem.bytesPerActivate::stdev 360.951821 # Bytes accessed per row activation 159system.physmem.bytesPerActivate::64 92 42.40% 42.40% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::128 33 15.21% 57.60% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::192 21 9.68% 67.28% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::256 20 9.22% 76.50% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::320 3 1.38% 77.88% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::384 8 3.69% 81.57% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::448 3 1.38% 82.95% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::512 4 1.84% 84.79% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::576 4 1.84% 86.64% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::640 4 1.84% 88.48% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::704 5 2.30% 90.78% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::768 4 1.84% 92.63% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::832 2 0.92% 93.55% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::896 2 0.92% 94.47% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::960 3 1.38% 95.85% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1024 1 0.46% 96.31% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1408 2 0.92% 97.24% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1536 2 0.92% 98.16% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1600 1 0.46% 98.62% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1856 2 0.92% 99.54% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::2304 1 0.46% 100.00% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::total 217 # Bytes accessed per row activation 181system.physmem.totQLat 9442250 # Total ticks spent queuing 182system.physmem.totMemAccLat 31257250 # Total ticks spent from burst creation until serviced by the DRAM 183system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers 184system.physmem.totBankLat 16940000 # Total ticks spent accessing banks 185system.physmem.avgQLat 9684.36 # Average queueing delay per DRAM burst 186system.physmem.avgBankLat 17374.36 # Average bank access latency per DRAM burst 187system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 188system.physmem.avgMemAccLat 32058.72 # Average memory access latency per DRAM burst 189system.physmem.avgRdBW 2575.37 # Average DRAM read bandwidth in MiByte/s 190system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 191system.physmem.avgRdBWSys 2575.37 # Average system read bandwidth in MiByte/s 192system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 193system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 194system.physmem.busUtil 20.12 # Data bus utilization in percentage 195system.physmem.busUtilRead 20.12 # Data bus utilization in percentage for reads 196system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 197system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing 198system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 199system.physmem.readRowHits 758 # Number of row buffer hits during reads 200system.physmem.writeRowHits 0 # Number of row buffer hits during writes 201system.physmem.readRowHitRate 77.74 # Row buffer hit rate for reads 202system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 203system.physmem.avgGap 24698.46 # Average gap between requests 204system.physmem.pageHitRate 77.74 # Row buffer hit rate, read and write combined 205system.physmem.prechargeAllPercent 0.09 # Percentage of time for which DRAM has all the banks in precharge state 206system.membus.throughput 2575372996 # Throughput (bytes/s) 207system.membus.trans_dist::ReadReq 829 # Transaction distribution 208system.membus.trans_dist::ReadResp 829 # Transaction distribution 209system.membus.trans_dist::ReadExReq 146 # Transaction distribution 210system.membus.trans_dist::ReadExResp 146 # Transaction distribution 211system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes) 212system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes) 213system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes) 214system.membus.tot_pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes) 215system.membus.data_through_bus 62400 # Total data (bytes) 216system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 217system.membus.reqLayer0.occupancy 1237000 # Layer occupancy (ticks) 218system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) 219system.membus.respLayer1.occupancy 9059500 # Layer occupancy (ticks) 220system.membus.respLayer1.utilization 37.4 # Layer utilization (%) 221system.cpu.branchPred.lookups 6676 # Number of BP lookups 222system.cpu.branchPred.condPredicted 3773 # Number of conditional branches predicted 223system.cpu.branchPred.condIncorrect 1441 # Number of conditional branches incorrect 224system.cpu.branchPred.BTBLookups 4746 # Number of BTB lookups 225system.cpu.branchPred.BTBHits 873 # Number of BTB hits 226system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 227system.cpu.branchPred.BTBHitPct 18.394437 # BTB Hit Percentage 228system.cpu.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. 229system.cpu.branchPred.RASInCorrect 179 # Number of incorrect RAS predictions. 230system.cpu.dtb.fetch_hits 0 # ITB hits 231system.cpu.dtb.fetch_misses 0 # ITB misses 232system.cpu.dtb.fetch_acv 0 # ITB acv 233system.cpu.dtb.fetch_accesses 0 # ITB accesses 234system.cpu.dtb.read_hits 4588 # DTB read hits 235system.cpu.dtb.read_misses 111 # DTB read misses 236system.cpu.dtb.read_acv 0 # DTB read access violations 237system.cpu.dtb.read_accesses 4699 # DTB read accesses 238system.cpu.dtb.write_hits 2013 # DTB write hits 239system.cpu.dtb.write_misses 87 # DTB write misses 240system.cpu.dtb.write_acv 0 # DTB write access violations 241system.cpu.dtb.write_accesses 2100 # DTB write accesses 242system.cpu.dtb.data_hits 6601 # DTB hits 243system.cpu.dtb.data_misses 198 # DTB misses 244system.cpu.dtb.data_acv 0 # DTB access violations 245system.cpu.dtb.data_accesses 6799 # DTB accesses 246system.cpu.itb.fetch_hits 5373 # ITB hits 247system.cpu.itb.fetch_misses 57 # ITB misses 248system.cpu.itb.fetch_acv 0 # ITB acv 249system.cpu.itb.fetch_accesses 5430 # ITB accesses 250system.cpu.itb.read_hits 0 # DTB read hits 251system.cpu.itb.read_misses 0 # DTB read misses 252system.cpu.itb.read_acv 0 # DTB read access violations 253system.cpu.itb.read_accesses 0 # DTB read accesses 254system.cpu.itb.write_hits 0 # DTB write hits 255system.cpu.itb.write_misses 0 # DTB write misses 256system.cpu.itb.write_acv 0 # DTB write access violations 257system.cpu.itb.write_accesses 0 # DTB write accesses 258system.cpu.itb.data_hits 0 # DTB hits 259system.cpu.itb.data_misses 0 # DTB misses 260system.cpu.itb.data_acv 0 # DTB access violations 261system.cpu.itb.data_accesses 0 # DTB accesses 262system.cpu.workload0.num_syscalls 17 # Number of system calls 263system.cpu.workload1.num_syscalls 17 # Number of system calls 264system.cpu.numCycles 48460 # number of cpu cycles simulated 265system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 266system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 267system.cpu.fetch.icacheStallCycles 1592 # Number of cycles fetch is stalled on an Icache miss 268system.cpu.fetch.Insts 37136 # Number of instructions fetch has processed 269system.cpu.fetch.Branches 6676 # Number of branches that fetch encountered 270system.cpu.fetch.predictedBranches 1759 # Number of branches that fetch has predicted taken 271system.cpu.fetch.Cycles 6223 # Number of cycles fetch has run and was not squashing or blocked 272system.cpu.fetch.SquashCycles 1834 # Number of cycles fetch has spent squashing 273system.cpu.fetch.MiscStallCycles 325 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 274system.cpu.fetch.CacheLines 5373 # Number of cache lines fetched 275system.cpu.fetch.IcacheSquashes 890 # Number of outstanding Icache misses that were squashed 276system.cpu.fetch.rateDist::samples 29553 # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.rateDist::mean 1.256590 # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::stdev 2.686803 # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 280system.cpu.fetch.rateDist::0 23330 78.94% 78.94% # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::1 540 1.83% 80.77% # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::2 380 1.29% 82.06% # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::3 444 1.50% 83.56% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::4 426 1.44% 85.00% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::5 410 1.39% 86.39% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::6 457 1.55% 87.93% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::7 520 1.76% 89.69% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::8 3046 10.31% 100.00% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::total 29553 # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.branchRate 0.137763 # Number of branch fetches per cycle 294system.cpu.fetch.rate 0.766323 # Number of inst fetches per cycle 295system.cpu.decode.IdleCycles 40475 # Number of cycles decode is idle 296system.cpu.decode.BlockedCycles 9887 # Number of cycles decode is blocked 297system.cpu.decode.RunCycles 5338 # Number of cycles decode is running 298system.cpu.decode.UnblockCycles 491 # Number of cycles decode is unblocking 299system.cpu.decode.SquashCycles 2736 # Number of cycles decode is squashing 300system.cpu.decode.BranchResolved 565 # Number of times decode resolved a branch 301system.cpu.decode.BranchMispred 333 # Number of times decode detected a branch misprediction 302system.cpu.decode.DecodedInsts 32705 # Number of instructions handled by decode 303system.cpu.decode.SquashedInsts 703 # Number of squashed instructions handled by decode 304system.cpu.rename.SquashCycles 2736 # Number of cycles rename is squashing 305system.cpu.rename.IdleCycles 41176 # Number of cycles rename is idle 306system.cpu.rename.BlockCycles 6161 # Number of cycles rename is blocking 307system.cpu.rename.serializeStallCycles 1585 # count of cycles rename stalled for serializing inst 308system.cpu.rename.RunCycles 5023 # Number of cycles rename is running 309system.cpu.rename.UnblockCycles 2246 # Number of cycles rename is unblocking 310system.cpu.rename.RenamedInsts 30191 # Number of instructions processed by rename 311system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full 312system.cpu.rename.LSQFullEvents 2292 # Number of times rename has blocked due to LSQ full 313system.cpu.rename.RenamedOperands 22672 # Number of destination operands rename has renamed 314system.cpu.rename.RenameLookups 37159 # Number of register rename lookups that rename has made 315system.cpu.rename.int_rename_lookups 37141 # Number of integer rename lookups 316system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 317system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed 318system.cpu.rename.UndoneMaps 13532 # Number of HB maps that are undone due to squashing 319system.cpu.rename.serializingInsts 49 # count of serializing insts renamed 320system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed 321system.cpu.rename.skidInsts 6118 # count of insts added to the skid buffer 322system.cpu.memDep0.insertedLoads 2970 # Number of loads inserted to the mem dependence unit. 323system.cpu.memDep0.insertedStores 1346 # Number of stores inserted to the mem dependence unit. 324system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. 325system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 326system.cpu.memDep1.insertedLoads 3035 # Number of loads inserted to the mem dependence unit. 327system.cpu.memDep1.insertedStores 1382 # Number of stores inserted to the mem dependence unit. 328system.cpu.memDep1.conflictingLoads 1 # Number of conflicting loads. 329system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. 330system.cpu.iq.iqInstsAdded 26321 # Number of instructions added to the IQ (excludes non-spec) 331system.cpu.iq.iqNonSpecInstsAdded 79 # Number of non-speculative instructions added to the IQ 332system.cpu.iq.iqInstsIssued 21626 # Number of instructions issued 333system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued 334system.cpu.iq.iqSquashedInstsExamined 12553 # Number of squashed instructions iterated over during squash; mainly for profiling 335system.cpu.iq.iqSquashedOperandsExamined 8051 # Number of squashed operands that are examined and possibly removed from graph 336system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed 337system.cpu.iq.issued_per_cycle::samples 29553 # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::mean 0.731770 # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::stdev 1.328577 # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::0 20214 68.40% 68.40% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::1 3351 11.34% 79.74% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::2 2621 8.87% 88.61% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::3 1590 5.38% 93.99% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::4 1011 3.42% 97.41% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::5 474 1.60% 99.01% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::6 217 0.73% 99.75% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::7 53 0.18% 99.93% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::8 22 0.07% 100.00% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::total 29553 # Number of insts issued each cycle 354system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 355system.cpu.iq.fu_full::IntAlu 9 4.86% 4.86% # attempts to use FU when none available 356system.cpu.iq.fu_full::IntMult 0 0.00% 4.86% # attempts to use FU when none available 357system.cpu.iq.fu_full::IntDiv 0 0.00% 4.86% # attempts to use FU when none available 358system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.86% # attempts to use FU when none available 359system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.86% # attempts to use FU when none available 360system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.86% # attempts to use FU when none available 361system.cpu.iq.fu_full::FloatMult 0 0.00% 4.86% # attempts to use FU when none available 362system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.86% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.86% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.86% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.86% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.86% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.86% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.86% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.86% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdMult 0 0.00% 4.86% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.86% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdShift 0 0.00% 4.86% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.86% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.86% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.86% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.86% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.86% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.86% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.86% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.86% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.86% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.86% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.86% # attempts to use FU when none available 384system.cpu.iq.fu_full::MemRead 107 57.84% 62.70% # attempts to use FU when none available 385system.cpu.iq.fu_full::MemWrite 69 37.30% 100.00% # attempts to use FU when none available 386system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 387system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 388system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 389system.cpu.iq.FU_type_0::IntAlu 7076 65.52% 65.54% # Type of FU issued 390system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.55% # Type of FU issued 391system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.55% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.56% # Type of FU issued 393system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.56% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.56% # Type of FU issued 395system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.56% # Type of FU issued 396system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.56% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued 418system.cpu.iq.FU_type_0::MemRead 2585 23.94% 89.50% # Type of FU issued 419system.cpu.iq.FU_type_0::MemWrite 1134 10.50% 100.00% # Type of FU issued 420system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 421system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 422system.cpu.iq.FU_type_0::total 10800 # Type of FU issued 423system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued 424system.cpu.iq.FU_type_1::IntAlu 7137 65.92% 65.94% # Type of FU issued 425system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.95% # Type of FU issued 426system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.95% # Type of FU issued 427system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.97% # Type of FU issued 428system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.97% # Type of FU issued 429system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.97% # Type of FU issued 430system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.97% # Type of FU issued 431system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.97% # Type of FU issued 432system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.97% # Type of FU issued 433system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.97% # Type of FU issued 434system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.97% # Type of FU issued 435system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.97% # Type of FU issued 436system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.97% # Type of FU issued 437system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.97% # Type of FU issued 438system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.97% # Type of FU issued 439system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.97% # Type of FU issued 440system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.97% # Type of FU issued 441system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.97% # Type of FU issued 442system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.97% # Type of FU issued 443system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.97% # Type of FU issued 444system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.97% # Type of FU issued 445system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.97% # Type of FU issued 446system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.97% # Type of FU issued 447system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.97% # Type of FU issued 448system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.97% # Type of FU issued 449system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.97% # Type of FU issued 450system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.97% # Type of FU issued 451system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.97% # Type of FU issued 452system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.97% # Type of FU issued 453system.cpu.iq.FU_type_1::MemRead 2587 23.90% 89.87% # Type of FU issued 454system.cpu.iq.FU_type_1::MemWrite 1097 10.13% 100.00% # Type of FU issued 455system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 456system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued 457system.cpu.iq.FU_type_1::total 10826 # Type of FU issued 458system.cpu.iq.FU_type::total 21626 0.00% 0.00% # Type of FU issued 459system.cpu.iq.rate 0.446265 # Inst issue rate 460system.cpu.iq.fu_busy_cnt::0 88 # FU busy when requested 461system.cpu.iq.fu_busy_cnt::1 97 # FU busy when requested 462system.cpu.iq.fu_busy_cnt::total 185 # FU busy when requested 463system.cpu.iq.fu_busy_rate::0 0.004069 # FU busy rate (busy events/executed inst) 464system.cpu.iq.fu_busy_rate::1 0.004485 # FU busy rate (busy events/executed inst) 465system.cpu.iq.fu_busy_rate::total 0.008555 # FU busy rate (busy events/executed inst) 466system.cpu.iq.int_inst_queue_reads 73079 # Number of integer instruction queue reads 467system.cpu.iq.int_inst_queue_writes 38962 # Number of integer instruction queue writes 468system.cpu.iq.int_inst_queue_wakeup_accesses 18683 # Number of integer instruction queue wakeup accesses 469system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads 470system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 471system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses 472system.cpu.iq.int_alu_accesses 21785 # Number of integer alu accesses 473system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses 474system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores 475system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 476system.cpu.iew.lsq.thread0.squashedLoads 1787 # Number of loads squashed 477system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 478system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations 479system.cpu.iew.lsq.thread0.squashedStores 481 # Number of stores squashed 480system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 481system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 482system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 483system.cpu.iew.lsq.thread0.cacheBlocked 350 # Number of times an access to memory failed due to the cache being blocked 484system.cpu.iew.lsq.thread1.forwLoads 47 # Number of loads that had data forwarded from stores 485system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address 486system.cpu.iew.lsq.thread1.squashedLoads 1852 # Number of loads squashed 487system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 488system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations 489system.cpu.iew.lsq.thread1.squashedStores 517 # Number of stores squashed 490system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 491system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 492system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled 493system.cpu.iew.lsq.thread1.cacheBlocked 408 # Number of times an access to memory failed due to the cache being blocked 494system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 495system.cpu.iew.iewSquashCycles 2736 # Number of cycles IEW is squashing 496system.cpu.iew.iewBlockCycles 2954 # Number of cycles IEW is blocking 497system.cpu.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking 498system.cpu.iew.iewDispatchedInsts 26599 # Number of instructions dispatched to IQ 499system.cpu.iew.iewDispSquashedInsts 599 # Number of squashed instructions skipped by dispatch 500system.cpu.iew.iewDispLoadInsts 6005 # Number of dispatched load instructions 501system.cpu.iew.iewDispStoreInsts 2728 # Number of dispatched store instructions 502system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions 503system.cpu.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall 504system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 505system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations 506system.cpu.iew.predictedTakenIncorrect 236 # Number of branches that were predicted taken incorrectly 507system.cpu.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly 508system.cpu.iew.branchMispredicts 1303 # Number of branch mispredicts detected at execute 509system.cpu.iew.iewExecutedInsts 20164 # Number of executed instructions 510system.cpu.iew.iewExecLoadInsts::0 2351 # Number of load instructions executed 511system.cpu.iew.iewExecLoadInsts::1 2366 # Number of load instructions executed 512system.cpu.iew.iewExecLoadInsts::total 4717 # Number of load instructions executed 513system.cpu.iew.iewExecSquashedInsts 1462 # Number of squashed instructions skipped in execute 514system.cpu.iew.exec_swp::0 0 # number of swp insts executed 515system.cpu.iew.exec_swp::1 0 # number of swp insts executed 516system.cpu.iew.exec_swp::total 0 # number of swp insts executed 517system.cpu.iew.exec_nop::0 109 # number of nop insts executed 518system.cpu.iew.exec_nop::1 90 # number of nop insts executed 519system.cpu.iew.exec_nop::total 199 # number of nop insts executed 520system.cpu.iew.exec_refs::0 3417 # number of memory reference insts executed 521system.cpu.iew.exec_refs::1 3414 # number of memory reference insts executed 522system.cpu.iew.exec_refs::total 6831 # number of memory reference insts executed 523system.cpu.iew.exec_branches::0 1584 # Number of branches executed 524system.cpu.iew.exec_branches::1 1595 # Number of branches executed 525system.cpu.iew.exec_branches::total 3179 # Number of branches executed 526system.cpu.iew.exec_stores::0 1066 # Number of stores executed 527system.cpu.iew.exec_stores::1 1048 # Number of stores executed 528system.cpu.iew.exec_stores::total 2114 # Number of stores executed 529system.cpu.iew.exec_rate 0.416096 # Inst execution rate 530system.cpu.iew.wb_sent::0 9509 # cumulative count of insts sent to commit 531system.cpu.iew.wb_sent::1 9507 # cumulative count of insts sent to commit 532system.cpu.iew.wb_sent::total 19016 # cumulative count of insts sent to commit 533system.cpu.iew.wb_count::0 9333 # cumulative count of insts written-back 534system.cpu.iew.wb_count::1 9370 # cumulative count of insts written-back 535system.cpu.iew.wb_count::total 18703 # cumulative count of insts written-back 536system.cpu.iew.wb_producers::0 4798 # num instructions producing a value 537system.cpu.iew.wb_producers::1 4829 # num instructions producing a value 538system.cpu.iew.wb_producers::total 9627 # num instructions producing a value 539system.cpu.iew.wb_consumers::0 6247 # num instructions consuming a value 540system.cpu.iew.wb_consumers::1 6319 # num instructions consuming a value 541system.cpu.iew.wb_consumers::total 12566 # num instructions consuming a value 542system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ 543system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ 544system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ 545system.cpu.iew.wb_rate::0 0.192592 # insts written-back per cycle 546system.cpu.iew.wb_rate::1 0.193355 # insts written-back per cycle 547system.cpu.iew.wb_rate::total 0.385947 # insts written-back per cycle 548system.cpu.iew.wb_fanout::0 0.768049 # average fanout of values written-back 549system.cpu.iew.wb_fanout::1 0.764203 # average fanout of values written-back 550system.cpu.iew.wb_fanout::total 0.766115 # average fanout of values written-back 551system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ 552system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ 553system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ 554system.cpu.commit.commitSquashedInsts 13828 # The number of squashed insts skipped by commit 555system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards 556system.cpu.commit.branchMispredicts 1125 # The number of times a branch was mispredicted 557system.cpu.commit.committed_per_cycle::samples 29486 # Number of insts commited each cycle 558system.cpu.commit.committed_per_cycle::mean 0.433392 # Number of insts commited each cycle 559system.cpu.commit.committed_per_cycle::stdev 1.196069 # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::0 23745 80.53% 80.53% # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::1 3040 10.31% 90.84% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::2 1123 3.81% 94.65% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::3 504 1.71% 96.36% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::4 341 1.16% 97.51% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::5 269 0.91% 98.43% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::6 187 0.63% 99.06% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::7 66 0.22% 99.28% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::8 211 0.72% 100.00% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::total 29486 # Number of insts commited each cycle 574system.cpu.commit.committedInsts::0 6390 # Number of instructions committed 575system.cpu.commit.committedInsts::1 6389 # Number of instructions committed 576system.cpu.commit.committedInsts::total 12779 # Number of instructions committed 577system.cpu.commit.committedOps::0 6390 # Number of ops (including micro ops) committed 578system.cpu.commit.committedOps::1 6389 # Number of ops (including micro ops) committed 579system.cpu.commit.committedOps::total 12779 # Number of ops (including micro ops) committed 580system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 581system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed 582system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed 583system.cpu.commit.refs::0 2048 # Number of memory references committed 584system.cpu.commit.refs::1 2048 # Number of memory references committed 585system.cpu.commit.refs::total 4096 # Number of memory references committed 586system.cpu.commit.loads::0 1183 # Number of loads committed 587system.cpu.commit.loads::1 1183 # Number of loads committed 588system.cpu.commit.loads::total 2366 # Number of loads committed 589system.cpu.commit.membars::0 0 # Number of memory barriers committed 590system.cpu.commit.membars::1 0 # Number of memory barriers committed 591system.cpu.commit.membars::total 0 # Number of memory barriers committed 592system.cpu.commit.branches::0 1050 # Number of branches committed 593system.cpu.commit.branches::1 1050 # Number of branches committed 594system.cpu.commit.branches::total 2100 # Number of branches committed 595system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. 596system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. 597system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. 598system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions. 599system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions. 600system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions. 601system.cpu.commit.function_calls::0 127 # Number of function calls committed. 602system.cpu.commit.function_calls::1 127 # Number of function calls committed. 603system.cpu.commit.function_calls::total 254 # Number of function calls committed. 604system.cpu.commit.bw_lim_events 211 # number cycles where commit BW limit reached 605system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits 606system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits 607system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits 608system.cpu.rob.rob_reads 132694 # The number of ROB reads 609system.cpu.rob.rob_writes 55968 # The number of ROB writes 610system.cpu.timesIdled 379 # Number of times that the entire CPU went into an idle state and unscheduled itself 611system.cpu.idleCycles 18907 # Total number of cycles that the CPU has spent unscheduled due to idling 612system.cpu.committedInsts::0 6373 # Number of Instructions Simulated 613system.cpu.committedInsts::1 6372 # Number of Instructions Simulated 614system.cpu.committedOps::0 6373 # Number of Ops (including micro ops) Simulated 615system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated 616system.cpu.committedInsts_total 12745 # Number of Instructions Simulated 617system.cpu.cpi::0 7.603954 # CPI: Cycles Per Instruction 618system.cpu.cpi::1 7.605148 # CPI: Cycles Per Instruction 619system.cpu.cpi_total 3.802275 # CPI: Total CPI of All Threads 620system.cpu.ipc::0 0.131511 # IPC: Instructions Per Cycle 621system.cpu.ipc::1 0.131490 # IPC: Instructions Per Cycle 622system.cpu.ipc_total 0.263000 # IPC: Total IPC of All Threads 623system.cpu.int_regfile_reads 25291 # number of integer regfile reads 624system.cpu.int_regfile_writes 14128 # number of integer regfile writes 625system.cpu.fp_regfile_reads 16 # number of floating regfile reads 626system.cpu.fp_regfile_writes 4 # number of floating regfile writes 627system.cpu.misc_regfile_reads 2 # number of misc regfile reads 628system.cpu.misc_regfile_writes 2 # number of misc regfile writes 629system.cpu.toL2Bus.throughput 2580655812 # Throughput (bytes/s) 630system.cpu.toL2Bus.trans_dist::ReadReq 831 # Transaction distribution 631system.cpu.toL2Bus.trans_dist::ReadResp 831 # Transaction distribution 632system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution 633system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution 634system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252 # Packet count per connected master and slave (bytes) 635system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes) 636system.cpu.toL2Bus.pkt_count::total 1954 # Packet count per connected master and slave (bytes) 637system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40064 # Cumulative packet size per connected master and slave (bytes) 638system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes) 639system.cpu.toL2Bus.tot_pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes) 640system.cpu.toL2Bus.data_through_bus 62528 # Total data (bytes) 641system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 642system.cpu.toL2Bus.reqLayer0.occupancy 488500 # Layer occupancy (ticks) 643system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) 644system.cpu.toL2Bus.respLayer0.occupancy 1029500 # Layer occupancy (ticks) 645system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%) 646system.cpu.toL2Bus.respLayer1.occupancy 562500 # Layer occupancy (ticks) 647system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 648system.cpu.icache.tags.replacements::0 6 # number of replacements 649system.cpu.icache.tags.replacements::1 0 # number of replacements 650system.cpu.icache.tags.replacements::total 6 # number of replacements 651system.cpu.icache.tags.tagsinuse 312.493120 # Cycle average of tags in use 652system.cpu.icache.tags.total_refs 4319 # Total number of references to valid blocks. 653system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks. 654system.cpu.icache.tags.avg_refs 6.899361 # Average number of references to valid blocks. 655system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 656system.cpu.icache.tags.occ_blocks::cpu.inst 312.493120 # Average occupied blocks per requestor 657system.cpu.icache.tags.occ_percent::cpu.inst 0.152585 # Average percentage of cache occupancy 658system.cpu.icache.tags.occ_percent::total 0.152585 # Average percentage of cache occupancy 659system.cpu.icache.ReadReq_hits::cpu.inst 4319 # number of ReadReq hits 660system.cpu.icache.ReadReq_hits::total 4319 # number of ReadReq hits 661system.cpu.icache.demand_hits::cpu.inst 4319 # number of demand (read+write) hits 662system.cpu.icache.demand_hits::total 4319 # number of demand (read+write) hits 663system.cpu.icache.overall_hits::cpu.inst 4319 # number of overall hits 664system.cpu.icache.overall_hits::total 4319 # number of overall hits 665system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses 666system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses 667system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses 668system.cpu.icache.demand_misses::total 1049 # number of demand (read+write) misses 669system.cpu.icache.overall_misses::cpu.inst 1049 # number of overall misses 670system.cpu.icache.overall_misses::total 1049 # number of overall misses 671system.cpu.icache.ReadReq_miss_latency::cpu.inst 69934495 # number of ReadReq miss cycles 672system.cpu.icache.ReadReq_miss_latency::total 69934495 # number of ReadReq miss cycles 673system.cpu.icache.demand_miss_latency::cpu.inst 69934495 # number of demand (read+write) miss cycles 674system.cpu.icache.demand_miss_latency::total 69934495 # number of demand (read+write) miss cycles 675system.cpu.icache.overall_miss_latency::cpu.inst 69934495 # number of overall miss cycles 676system.cpu.icache.overall_miss_latency::total 69934495 # number of overall miss cycles 677system.cpu.icache.ReadReq_accesses::cpu.inst 5368 # number of ReadReq accesses(hits+misses) 678system.cpu.icache.ReadReq_accesses::total 5368 # number of ReadReq accesses(hits+misses) 679system.cpu.icache.demand_accesses::cpu.inst 5368 # number of demand (read+write) accesses 680system.cpu.icache.demand_accesses::total 5368 # number of demand (read+write) accesses 681system.cpu.icache.overall_accesses::cpu.inst 5368 # number of overall (read+write) accesses 682system.cpu.icache.overall_accesses::total 5368 # number of overall (read+write) accesses 683system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195417 # miss rate for ReadReq accesses 684system.cpu.icache.ReadReq_miss_rate::total 0.195417 # miss rate for ReadReq accesses 685system.cpu.icache.demand_miss_rate::cpu.inst 0.195417 # miss rate for demand accesses 686system.cpu.icache.demand_miss_rate::total 0.195417 # miss rate for demand accesses 687system.cpu.icache.overall_miss_rate::cpu.inst 0.195417 # miss rate for overall accesses 688system.cpu.icache.overall_miss_rate::total 0.195417 # miss rate for overall accesses 689system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66667.774071 # average ReadReq miss latency 690system.cpu.icache.ReadReq_avg_miss_latency::total 66667.774071 # average ReadReq miss latency 691system.cpu.icache.demand_avg_miss_latency::cpu.inst 66667.774071 # average overall miss latency 692system.cpu.icache.demand_avg_miss_latency::total 66667.774071 # average overall miss latency 693system.cpu.icache.overall_avg_miss_latency::cpu.inst 66667.774071 # average overall miss latency 694system.cpu.icache.overall_avg_miss_latency::total 66667.774071 # average overall miss latency 695system.cpu.icache.blocked_cycles::no_mshrs 2561 # number of cycles access was blocked 696system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 697system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked 698system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 699system.cpu.icache.avg_blocked_cycles::no_mshrs 44.155172 # average number of cycles each access was blocked 700system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 701system.cpu.icache.fast_writes 0 # number of fast writes performed 702system.cpu.icache.cache_copies 0 # number of cache copies performed 703system.cpu.icache.ReadReq_mshr_hits::cpu.inst 423 # number of ReadReq MSHR hits 704system.cpu.icache.ReadReq_mshr_hits::total 423 # number of ReadReq MSHR hits 705system.cpu.icache.demand_mshr_hits::cpu.inst 423 # number of demand (read+write) MSHR hits 706system.cpu.icache.demand_mshr_hits::total 423 # number of demand (read+write) MSHR hits 707system.cpu.icache.overall_mshr_hits::cpu.inst 423 # number of overall MSHR hits 708system.cpu.icache.overall_mshr_hits::total 423 # number of overall MSHR hits 709system.cpu.icache.ReadReq_mshr_misses::cpu.inst 626 # number of ReadReq MSHR misses 710system.cpu.icache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses 711system.cpu.icache.demand_mshr_misses::cpu.inst 626 # number of demand (read+write) MSHR misses 712system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses 713system.cpu.icache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses 714system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses 715system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46953746 # number of ReadReq MSHR miss cycles 716system.cpu.icache.ReadReq_mshr_miss_latency::total 46953746 # number of ReadReq MSHR miss cycles 717system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46953746 # number of demand (read+write) MSHR miss cycles 718system.cpu.icache.demand_mshr_miss_latency::total 46953746 # number of demand (read+write) MSHR miss cycles 719system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46953746 # number of overall MSHR miss cycles 720system.cpu.icache.overall_mshr_miss_latency::total 46953746 # number of overall MSHR miss cycles 721system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for ReadReq accesses 722system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116617 # mshr miss rate for ReadReq accesses 723system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for demand accesses 724system.cpu.icache.demand_mshr_miss_rate::total 0.116617 # mshr miss rate for demand accesses 725system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for overall accesses 726system.cpu.icache.overall_mshr_miss_rate::total 0.116617 # mshr miss rate for overall accesses 727system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75005.984026 # average ReadReq mshr miss latency 728system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75005.984026 # average ReadReq mshr miss latency 729system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75005.984026 # average overall mshr miss latency 730system.cpu.icache.demand_avg_mshr_miss_latency::total 75005.984026 # average overall mshr miss latency 731system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75005.984026 # average overall mshr miss latency 732system.cpu.icache.overall_avg_mshr_miss_latency::total 75005.984026 # average overall mshr miss latency 733system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 734system.cpu.l2cache.tags.replacements::0 0 # number of replacements 735system.cpu.l2cache.tags.replacements::1 0 # number of replacements 736system.cpu.l2cache.tags.replacements::total 0 # number of replacements 737system.cpu.l2cache.tags.tagsinuse 433.166095 # Cycle average of tags in use 738system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 739system.cpu.l2cache.tags.sampled_refs 829 # Sample count of references to valid blocks. 740system.cpu.l2cache.tags.avg_refs 0.002413 # Average number of references to valid blocks. 741system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 742system.cpu.l2cache.tags.occ_blocks::cpu.inst 313.001767 # Average occupied blocks per requestor 743system.cpu.l2cache.tags.occ_blocks::cpu.data 120.164328 # Average occupied blocks per requestor 744system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009552 # Average percentage of cache occupancy 745system.cpu.l2cache.tags.occ_percent::cpu.data 0.003667 # Average percentage of cache occupancy 746system.cpu.l2cache.tags.occ_percent::total 0.013219 # Average percentage of cache occupancy 747system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 748system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 749system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 750system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 751system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 752system.cpu.l2cache.overall_hits::total 2 # number of overall hits 753system.cpu.l2cache.ReadReq_misses::cpu.inst 624 # number of ReadReq misses 754system.cpu.l2cache.ReadReq_misses::cpu.data 205 # number of ReadReq misses 755system.cpu.l2cache.ReadReq_misses::total 829 # number of ReadReq misses 756system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses 757system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses 758system.cpu.l2cache.demand_misses::cpu.inst 624 # number of demand (read+write) misses 759system.cpu.l2cache.demand_misses::cpu.data 351 # number of demand (read+write) misses 760system.cpu.l2cache.demand_misses::total 975 # number of demand (read+write) misses 761system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses 762system.cpu.l2cache.overall_misses::cpu.data 351 # number of overall misses 763system.cpu.l2cache.overall_misses::total 975 # number of overall misses 764system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46304000 # number of ReadReq miss cycles 765system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16910000 # number of ReadReq miss cycles 766system.cpu.l2cache.ReadReq_miss_latency::total 63214000 # number of ReadReq miss cycles 767system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11874500 # number of ReadExReq miss cycles 768system.cpu.l2cache.ReadExReq_miss_latency::total 11874500 # number of ReadExReq miss cycles 769system.cpu.l2cache.demand_miss_latency::cpu.inst 46304000 # number of demand (read+write) miss cycles 770system.cpu.l2cache.demand_miss_latency::cpu.data 28784500 # number of demand (read+write) miss cycles 771system.cpu.l2cache.demand_miss_latency::total 75088500 # number of demand (read+write) miss cycles 772system.cpu.l2cache.overall_miss_latency::cpu.inst 46304000 # number of overall miss cycles 773system.cpu.l2cache.overall_miss_latency::cpu.data 28784500 # number of overall miss cycles 774system.cpu.l2cache.overall_miss_latency::total 75088500 # number of overall miss cycles 775system.cpu.l2cache.ReadReq_accesses::cpu.inst 626 # number of ReadReq accesses(hits+misses) 776system.cpu.l2cache.ReadReq_accesses::cpu.data 205 # number of ReadReq accesses(hits+misses) 777system.cpu.l2cache.ReadReq_accesses::total 831 # number of ReadReq accesses(hits+misses) 778system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) 779system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) 780system.cpu.l2cache.demand_accesses::cpu.inst 626 # number of demand (read+write) accesses 781system.cpu.l2cache.demand_accesses::cpu.data 351 # number of demand (read+write) accesses 782system.cpu.l2cache.demand_accesses::total 977 # number of demand (read+write) accesses 783system.cpu.l2cache.overall_accesses::cpu.inst 626 # number of overall (read+write) accesses 784system.cpu.l2cache.overall_accesses::cpu.data 351 # number of overall (read+write) accesses 785system.cpu.l2cache.overall_accesses::total 977 # number of overall (read+write) accesses 786system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses 787system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 788system.cpu.l2cache.ReadReq_miss_rate::total 0.997593 # miss rate for ReadReq accesses 789system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 790system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 791system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses 792system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 793system.cpu.l2cache.demand_miss_rate::total 0.997953 # miss rate for demand accesses 794system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses 795system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 796system.cpu.l2cache.overall_miss_rate::total 0.997953 # miss rate for overall accesses 797system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74205.128205 # average ReadReq miss latency 798system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82487.804878 # average ReadReq miss latency 799system.cpu.l2cache.ReadReq_avg_miss_latency::total 76253.317250 # average ReadReq miss latency 800system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81332.191781 # average ReadExReq miss latency 801system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81332.191781 # average ReadExReq miss latency 802system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74205.128205 # average overall miss latency 803system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82007.122507 # average overall miss latency 804system.cpu.l2cache.demand_avg_miss_latency::total 77013.846154 # average overall miss latency 805system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74205.128205 # average overall miss latency 806system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82007.122507 # average overall miss latency 807system.cpu.l2cache.overall_avg_miss_latency::total 77013.846154 # average overall miss latency 808system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 809system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 810system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 811system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 812system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 813system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 814system.cpu.l2cache.fast_writes 0 # number of fast writes performed 815system.cpu.l2cache.cache_copies 0 # number of cache copies performed 816system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses 817system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses 818system.cpu.l2cache.ReadReq_mshr_misses::total 829 # number of ReadReq MSHR misses 819system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses 820system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses 821system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses 822system.cpu.l2cache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses 823system.cpu.l2cache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses 824system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses 825system.cpu.l2cache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses 826system.cpu.l2cache.overall_mshr_misses::total 975 # number of overall MSHR misses 827system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38522500 # number of ReadReq MSHR miss cycles 828system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14387500 # number of ReadReq MSHR miss cycles 829system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52910000 # number of ReadReq MSHR miss cycles 830system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10067500 # number of ReadExReq MSHR miss cycles 831system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10067500 # number of ReadExReq MSHR miss cycles 832system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38522500 # number of demand (read+write) MSHR miss cycles 833system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24455000 # number of demand (read+write) MSHR miss cycles 834system.cpu.l2cache.demand_mshr_miss_latency::total 62977500 # number of demand (read+write) MSHR miss cycles 835system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38522500 # number of overall MSHR miss cycles 836system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24455000 # number of overall MSHR miss cycles 837system.cpu.l2cache.overall_mshr_miss_latency::total 62977500 # number of overall MSHR miss cycles 838system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses 839system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 840system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997593 # mshr miss rate for ReadReq accesses 841system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 842system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 843system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses 844system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 845system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses 846system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses 847system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 848system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses 849system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61734.775641 # average ReadReq mshr miss latency 850system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70182.926829 # average ReadReq mshr miss latency 851system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63823.884198 # average ReadReq mshr miss latency 852system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68955.479452 # average ReadExReq mshr miss latency 853system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68955.479452 # average ReadExReq mshr miss latency 854system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61734.775641 # average overall mshr miss latency 855system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69672.364672 # average overall mshr miss latency 856system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64592.307692 # average overall mshr miss latency 857system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61734.775641 # average overall mshr miss latency 858system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69672.364672 # average overall mshr miss latency 859system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64592.307692 # average overall mshr miss latency 860system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 861system.cpu.dcache.tags.replacements::0 0 # number of replacements 862system.cpu.dcache.tags.replacements::1 0 # number of replacements 863system.cpu.dcache.tags.replacements::total 0 # number of replacements 864system.cpu.dcache.tags.tagsinuse 214.018929 # Cycle average of tags in use 865system.cpu.dcache.tags.total_refs 4470 # Total number of references to valid blocks. 866system.cpu.dcache.tags.sampled_refs 351 # Sample count of references to valid blocks. 867system.cpu.dcache.tags.avg_refs 12.735043 # Average number of references to valid blocks. 868system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 869system.cpu.dcache.tags.occ_blocks::cpu.data 214.018929 # Average occupied blocks per requestor 870system.cpu.dcache.tags.occ_percent::cpu.data 0.052251 # Average percentage of cache occupancy 871system.cpu.dcache.tags.occ_percent::total 0.052251 # Average percentage of cache occupancy 872system.cpu.dcache.ReadReq_hits::cpu.data 3448 # number of ReadReq hits 873system.cpu.dcache.ReadReq_hits::total 3448 # number of ReadReq hits 874system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits 875system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits 876system.cpu.dcache.demand_hits::cpu.data 4470 # number of demand (read+write) hits 877system.cpu.dcache.demand_hits::total 4470 # number of demand (read+write) hits 878system.cpu.dcache.overall_hits::cpu.data 4470 # number of overall hits 879system.cpu.dcache.overall_hits::total 4470 # number of overall hits 880system.cpu.dcache.ReadReq_misses::cpu.data 329 # number of ReadReq misses 881system.cpu.dcache.ReadReq_misses::total 329 # number of ReadReq misses 882system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses 883system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses 884system.cpu.dcache.demand_misses::cpu.data 1037 # number of demand (read+write) misses 885system.cpu.dcache.demand_misses::total 1037 # number of demand (read+write) misses 886system.cpu.dcache.overall_misses::cpu.data 1037 # number of overall misses 887system.cpu.dcache.overall_misses::total 1037 # number of overall misses 888system.cpu.dcache.ReadReq_miss_latency::cpu.data 23849750 # number of ReadReq miss cycles 889system.cpu.dcache.ReadReq_miss_latency::total 23849750 # number of ReadReq miss cycles 890system.cpu.dcache.WriteReq_miss_latency::cpu.data 50904202 # number of WriteReq miss cycles 891system.cpu.dcache.WriteReq_miss_latency::total 50904202 # number of WriteReq miss cycles 892system.cpu.dcache.demand_miss_latency::cpu.data 74753952 # number of demand (read+write) miss cycles 893system.cpu.dcache.demand_miss_latency::total 74753952 # number of demand (read+write) miss cycles 894system.cpu.dcache.overall_miss_latency::cpu.data 74753952 # number of overall miss cycles 895system.cpu.dcache.overall_miss_latency::total 74753952 # number of overall miss cycles 896system.cpu.dcache.ReadReq_accesses::cpu.data 3777 # number of ReadReq accesses(hits+misses) 897system.cpu.dcache.ReadReq_accesses::total 3777 # number of ReadReq accesses(hits+misses) 898system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) 899system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) 900system.cpu.dcache.demand_accesses::cpu.data 5507 # number of demand (read+write) accesses 901system.cpu.dcache.demand_accesses::total 5507 # number of demand (read+write) accesses 902system.cpu.dcache.overall_accesses::cpu.data 5507 # number of overall (read+write) accesses 903system.cpu.dcache.overall_accesses::total 5507 # number of overall (read+write) accesses 904system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087106 # miss rate for ReadReq accesses 905system.cpu.dcache.ReadReq_miss_rate::total 0.087106 # miss rate for ReadReq accesses 906system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses 907system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses 908system.cpu.dcache.demand_miss_rate::cpu.data 0.188306 # miss rate for demand accesses 909system.cpu.dcache.demand_miss_rate::total 0.188306 # miss rate for demand accesses 910system.cpu.dcache.overall_miss_rate::cpu.data 0.188306 # miss rate for overall accesses 911system.cpu.dcache.overall_miss_rate::total 0.188306 # miss rate for overall accesses 912system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72491.641337 # average ReadReq miss latency 913system.cpu.dcache.ReadReq_avg_miss_latency::total 72491.641337 # average ReadReq miss latency 914system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71898.590395 # average WriteReq miss latency 915system.cpu.dcache.WriteReq_avg_miss_latency::total 71898.590395 # average WriteReq miss latency 916system.cpu.dcache.demand_avg_miss_latency::cpu.data 72086.742527 # average overall miss latency 917system.cpu.dcache.demand_avg_miss_latency::total 72086.742527 # average overall miss latency 918system.cpu.dcache.overall_avg_miss_latency::cpu.data 72086.742527 # average overall miss latency 919system.cpu.dcache.overall_avg_miss_latency::total 72086.742527 # average overall miss latency 920system.cpu.dcache.blocked_cycles::no_mshrs 4541 # number of cycles access was blocked 921system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 922system.cpu.dcache.blocked::no_mshrs 118 # number of cycles access was blocked 923system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 924system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.483051 # average number of cycles each access was blocked 925system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 926system.cpu.dcache.fast_writes 0 # number of fast writes performed 927system.cpu.dcache.cache_copies 0 # number of cache copies performed 928system.cpu.dcache.ReadReq_mshr_hits::cpu.data 124 # number of ReadReq MSHR hits 929system.cpu.dcache.ReadReq_mshr_hits::total 124 # number of ReadReq MSHR hits 930system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits 931system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits 932system.cpu.dcache.demand_mshr_hits::cpu.data 686 # number of demand (read+write) MSHR hits 933system.cpu.dcache.demand_mshr_hits::total 686 # number of demand (read+write) MSHR hits 934system.cpu.dcache.overall_mshr_hits::cpu.data 686 # number of overall MSHR hits 935system.cpu.dcache.overall_mshr_hits::total 686 # number of overall MSHR hits 936system.cpu.dcache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses 937system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses 938system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses 939system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses 940system.cpu.dcache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses 941system.cpu.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 942system.cpu.dcache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses 943system.cpu.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses 944system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17123000 # number of ReadReq MSHR miss cycles 945system.cpu.dcache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles 946system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12022996 # number of WriteReq MSHR miss cycles 947system.cpu.dcache.WriteReq_mshr_miss_latency::total 12022996 # number of WriteReq MSHR miss cycles 948system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29145996 # number of demand (read+write) MSHR miss cycles 949system.cpu.dcache.demand_mshr_miss_latency::total 29145996 # number of demand (read+write) MSHR miss cycles 950system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29145996 # number of overall MSHR miss cycles 951system.cpu.dcache.overall_mshr_miss_latency::total 29145996 # number of overall MSHR miss cycles 952system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054276 # mshr miss rate for ReadReq accesses 953system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054276 # mshr miss rate for ReadReq accesses 954system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 955system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 956system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063737 # mshr miss rate for demand accesses 957system.cpu.dcache.demand_mshr_miss_rate::total 0.063737 # mshr miss rate for demand accesses 958system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063737 # mshr miss rate for overall accesses 959system.cpu.dcache.overall_mshr_miss_rate::total 0.063737 # mshr miss rate for overall accesses 960system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83526.829268 # average ReadReq mshr miss latency 961system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83526.829268 # average ReadReq mshr miss latency 962system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82349.287671 # average WriteReq mshr miss latency 963system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82349.287671 # average WriteReq mshr miss latency 964system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83037.025641 # average overall mshr miss latency 965system.cpu.dcache.demand_avg_mshr_miss_latency::total 83037.025641 # average overall mshr miss latency 966system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83037.025641 # average overall mshr miss latency 967system.cpu.dcache.overall_avg_mshr_miss_latency::total 83037.025641 # average overall mshr miss latency 968system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 969 970---------- End Simulation Statistics ---------- 971