stats.txt revision 9490
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000024 # Number of seconds simulated 4sim_ticks 24473000 # Number of ticks simulated 5final_tick 24473000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 4068 # Simulator instruction rate (inst/s) 8host_op_rate 4068 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 7811345 # Simulator tick rate (ticks/s) 10host_mem_usage 226312 # Number of bytes of host memory used 11host_seconds 3.13 # Real time elapsed on the host 12sim_insts 12745 # Number of instructions simulated 13sim_ops 12745 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 22272 # Number of bytes read from this memory 16system.physmem.bytes_read::total 62080 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 39808 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 39808 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 622 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 348 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 970 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1626608916 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 910064152 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2536673068 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1626608916 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1626608916 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1626608916 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 910064152 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2536673068 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 970 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 970 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 62080 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 62080 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 101 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 34 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 45 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 100 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 103 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 116 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 66 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 88 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 21 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 60 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 91 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 24326500 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 970 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes 89system.physmem.writePktSize::6 0 # categorize write packet sizes 90system.physmem.writePktSize::7 0 # categorize write packet sizes 91system.physmem.writePktSize::8 0 # categorize write packet sizes 92system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 101system.physmem.rdQLenPdf::0 166 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 260 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 254 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 86 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 29 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 134system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 167system.physmem.totQLat 22646466 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 53470216 # Sum of mem lat for all requests 169system.physmem.totBusLat 4850000 # Total cycles spent in databus access 170system.physmem.totBankLat 25973750 # Total cycles spent in bank access 171system.physmem.avgQLat 23346.87 # Average queueing delay per request 172system.physmem.avgBankLat 26777.06 # Average bank access latency per request 173system.physmem.avgBusLat 5000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 55123.93 # Average memory access latency 175system.physmem.avgRdBW 2536.67 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 2536.67 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 19.82 # Data bus utilization in percentage 181system.physmem.avgRdQLen 2.18 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 450 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 46.39 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 187system.physmem.avgGap 25078.87 # Average gap between requests 188system.cpu.branchPred.lookups 6101 # Number of BP lookups 189system.cpu.branchPred.condPredicted 3457 # Number of conditional branches predicted 190system.cpu.branchPred.condIncorrect 1231 # Number of conditional branches incorrect 191system.cpu.branchPred.BTBLookups 4432 # Number of BTB lookups 192system.cpu.branchPred.BTBHits 1023 # Number of BTB hits 193system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 194system.cpu.branchPred.BTBHitPct 23.082130 # BTB Hit Percentage 195system.cpu.branchPred.usedRAS 800 # Number of times the RAS was used to get a target. 196system.cpu.branchPred.RASInCorrect 163 # Number of incorrect RAS predictions. 197system.cpu.dtb.fetch_hits 0 # ITB hits 198system.cpu.dtb.fetch_misses 0 # ITB misses 199system.cpu.dtb.fetch_acv 0 # ITB acv 200system.cpu.dtb.fetch_accesses 0 # ITB accesses 201system.cpu.dtb.read_hits 4461 # DTB read hits 202system.cpu.dtb.read_misses 100 # DTB read misses 203system.cpu.dtb.read_acv 0 # DTB read access violations 204system.cpu.dtb.read_accesses 4561 # DTB read accesses 205system.cpu.dtb.write_hits 2022 # DTB write hits 206system.cpu.dtb.write_misses 83 # DTB write misses 207system.cpu.dtb.write_acv 0 # DTB write access violations 208system.cpu.dtb.write_accesses 2105 # DTB write accesses 209system.cpu.dtb.data_hits 6483 # DTB hits 210system.cpu.dtb.data_misses 183 # DTB misses 211system.cpu.dtb.data_acv 0 # DTB access violations 212system.cpu.dtb.data_accesses 6666 # DTB accesses 213system.cpu.itb.fetch_hits 4836 # ITB hits 214system.cpu.itb.fetch_misses 49 # ITB misses 215system.cpu.itb.fetch_acv 0 # ITB acv 216system.cpu.itb.fetch_accesses 4885 # ITB accesses 217system.cpu.itb.read_hits 0 # DTB read hits 218system.cpu.itb.read_misses 0 # DTB read misses 219system.cpu.itb.read_acv 0 # DTB read access violations 220system.cpu.itb.read_accesses 0 # DTB read accesses 221system.cpu.itb.write_hits 0 # DTB write hits 222system.cpu.itb.write_misses 0 # DTB write misses 223system.cpu.itb.write_acv 0 # DTB write access violations 224system.cpu.itb.write_accesses 0 # DTB write accesses 225system.cpu.itb.data_hits 0 # DTB hits 226system.cpu.itb.data_misses 0 # DTB misses 227system.cpu.itb.data_acv 0 # DTB access violations 228system.cpu.itb.data_accesses 0 # DTB accesses 229system.cpu.workload0.num_syscalls 17 # Number of system calls 230system.cpu.workload1.num_syscalls 17 # Number of system calls 231system.cpu.numCycles 48947 # number of cpu cycles simulated 232system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 233system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 234system.cpu.fetch.icacheStallCycles 1376 # Number of cycles fetch is stalled on an Icache miss 235system.cpu.fetch.Insts 33899 # Number of instructions fetch has processed 236system.cpu.fetch.Branches 6101 # Number of branches that fetch encountered 237system.cpu.fetch.predictedBranches 1823 # Number of branches that fetch has predicted taken 238system.cpu.fetch.Cycles 5733 # Number of cycles fetch has run and was not squashing or blocked 239system.cpu.fetch.SquashCycles 1590 # Number of cycles fetch has spent squashing 240system.cpu.fetch.MiscStallCycles 519 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 241system.cpu.fetch.CacheLines 4836 # Number of cache lines fetched 242system.cpu.fetch.IcacheSquashes 811 # Number of outstanding Icache misses that were squashed 243system.cpu.fetch.rateDist::samples 28070 # Number of instructions fetched each cycle (Total) 244system.cpu.fetch.rateDist::mean 1.207659 # Number of instructions fetched each cycle (Total) 245system.cpu.fetch.rateDist::stdev 2.639587 # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 247system.cpu.fetch.rateDist::0 22337 79.58% 79.58% # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::1 523 1.86% 81.44% # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::2 359 1.28% 82.72% # Number of instructions fetched each cycle (Total) 250system.cpu.fetch.rateDist::3 389 1.39% 84.10% # Number of instructions fetched each cycle (Total) 251system.cpu.fetch.rateDist::4 440 1.57% 85.67% # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::5 399 1.42% 87.09% # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::6 440 1.57% 88.66% # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::7 368 1.31% 89.97% # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::8 2815 10.03% 100.00% # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::total 28070 # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.branchRate 0.124645 # Number of branch fetches per cycle 261system.cpu.fetch.rate 0.692565 # Number of inst fetches per cycle 262system.cpu.decode.IdleCycles 38855 # Number of cycles decode is idle 263system.cpu.decode.BlockedCycles 9028 # Number of cycles decode is blocked 264system.cpu.decode.RunCycles 4956 # Number of cycles decode is running 265system.cpu.decode.UnblockCycles 477 # Number of cycles decode is unblocking 266system.cpu.decode.SquashCycles 2426 # Number of cycles decode is squashing 267system.cpu.decode.BranchResolved 492 # Number of times decode resolved a branch 268system.cpu.decode.BranchMispred 289 # Number of times decode detected a branch misprediction 269system.cpu.decode.DecodedInsts 30419 # Number of instructions handled by decode 270system.cpu.decode.SquashedInsts 546 # Number of squashed instructions handled by decode 271system.cpu.rename.SquashCycles 2426 # Number of cycles rename is squashing 272system.cpu.rename.IdleCycles 39473 # Number of cycles rename is idle 273system.cpu.rename.BlockCycles 6021 # Number of cycles rename is blocking 274system.cpu.rename.serializeStallCycles 969 # count of cycles rename stalled for serializing inst 275system.cpu.rename.RunCycles 4731 # Number of cycles rename is running 276system.cpu.rename.UnblockCycles 2122 # Number of cycles rename is unblocking 277system.cpu.rename.RenamedInsts 28264 # Number of instructions processed by rename 278system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full 279system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 280system.cpu.rename.LSQFullEvents 2059 # Number of times rename has blocked due to LSQ full 281system.cpu.rename.RenamedOperands 21243 # Number of destination operands rename has renamed 282system.cpu.rename.RenameLookups 34749 # Number of register rename lookups that rename has made 283system.cpu.rename.int_rename_lookups 34715 # Number of integer rename lookups 284system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups 285system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed 286system.cpu.rename.UndoneMaps 12103 # Number of HB maps that are undone due to squashing 287system.cpu.rename.serializingInsts 49 # count of serializing insts renamed 288system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed 289system.cpu.rename.skidInsts 5573 # count of insts added to the skid buffer 290system.cpu.memDep0.insertedLoads 2924 # Number of loads inserted to the mem dependence unit. 291system.cpu.memDep0.insertedStores 1330 # Number of stores inserted to the mem dependence unit. 292system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. 293system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 294system.cpu.memDep1.insertedLoads 2736 # Number of loads inserted to the mem dependence unit. 295system.cpu.memDep1.insertedStores 1292 # Number of stores inserted to the mem dependence unit. 296system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads. 297system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. 298system.cpu.iq.iqInstsAdded 25104 # Number of instructions added to the IQ (excludes non-spec) 299system.cpu.iq.iqNonSpecInstsAdded 73 # Number of non-speculative instructions added to the IQ 300system.cpu.iq.iqInstsIssued 20875 # Number of instructions issued 301system.cpu.iq.iqSquashedInstsIssued 70 # Number of squashed instructions issued 302system.cpu.iq.iqSquashedInstsExamined 11589 # Number of squashed instructions iterated over during squash; mainly for profiling 303system.cpu.iq.iqSquashedOperandsExamined 7157 # Number of squashed operands that are examined and possibly removed from graph 304system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed 305system.cpu.iq.issued_per_cycle::samples 28070 # Number of insts issued each cycle 306system.cpu.iq.issued_per_cycle::mean 0.743677 # Number of insts issued each cycle 307system.cpu.iq.issued_per_cycle::stdev 1.323333 # Number of insts issued each cycle 308system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 309system.cpu.iq.issued_per_cycle::0 18893 67.31% 67.31% # Number of insts issued each cycle 310system.cpu.iq.issued_per_cycle::1 3427 12.21% 79.52% # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::2 2538 9.04% 88.56% # Number of insts issued each cycle 312system.cpu.iq.issued_per_cycle::3 1546 5.51% 94.06% # Number of insts issued each cycle 313system.cpu.iq.issued_per_cycle::4 945 3.37% 97.43% # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::5 459 1.64% 99.07% # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::6 189 0.67% 99.74% # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::7 59 0.21% 99.95% # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle 318system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::total 28070 # Number of insts issued each cycle 322system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 323system.cpu.iq.fu_full::IntAlu 6 3.64% 3.64% # attempts to use FU when none available 324system.cpu.iq.fu_full::IntMult 0 0.00% 3.64% # attempts to use FU when none available 325system.cpu.iq.fu_full::IntDiv 0 0.00% 3.64% # attempts to use FU when none available 326system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.64% # attempts to use FU when none available 327system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.64% # attempts to use FU when none available 328system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.64% # attempts to use FU when none available 329system.cpu.iq.fu_full::FloatMult 0 0.00% 3.64% # attempts to use FU when none available 330system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.64% # attempts to use FU when none available 331system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.64% # attempts to use FU when none available 332system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.64% # attempts to use FU when none available 333system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.64% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.64% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.64% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.64% # attempts to use FU when none available 337system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.64% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdMult 0 0.00% 3.64% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.64% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdShift 0 0.00% 3.64% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.64% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.64% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.64% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.64% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.64% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.64% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.64% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.64% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.64% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.64% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.64% # attempts to use FU when none available 352system.cpu.iq.fu_full::MemRead 98 59.39% 63.03% # attempts to use FU when none available 353system.cpu.iq.fu_full::MemWrite 61 36.97% 100.00% # attempts to use FU when none available 354system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 355system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 356system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 357system.cpu.iq.FU_type_0::IntAlu 6970 65.71% 65.73% # Type of FU issued 358system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.74% # Type of FU issued 359system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.74% # Type of FU issued 360system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.76% # Type of FU issued 361system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.76% # Type of FU issued 362system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.76% # Type of FU issued 363system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.76% # Type of FU issued 364system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.76% # Type of FU issued 365system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.76% # Type of FU issued 366system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.76% # Type of FU issued 367system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.76% # Type of FU issued 368system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.76% # Type of FU issued 369system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.76% # Type of FU issued 370system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.76% # Type of FU issued 371system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.76% # Type of FU issued 372system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.76% # Type of FU issued 373system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.76% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.76% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.76% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.76% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.76% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.76% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.76% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.76% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.76% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.76% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.76% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.76% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.76% # Type of FU issued 386system.cpu.iq.FU_type_0::MemRead 2525 23.81% 89.56% # Type of FU issued 387system.cpu.iq.FU_type_0::MemWrite 1107 10.44% 100.00% # Type of FU issued 388system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 389system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 390system.cpu.iq.FU_type_0::total 10607 # Type of FU issued 391system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued 392system.cpu.iq.FU_type_1::IntAlu 6762 65.86% 65.87% # Type of FU issued 393system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.88% # Type of FU issued 394system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.88% # Type of FU issued 395system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.90% # Type of FU issued 396system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.90% # Type of FU issued 397system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.90% # Type of FU issued 398system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.90% # Type of FU issued 399system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.90% # Type of FU issued 400system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.90% # Type of FU issued 401system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.90% # Type of FU issued 402system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.90% # Type of FU issued 403system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.90% # Type of FU issued 404system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.90% # Type of FU issued 405system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.90% # Type of FU issued 406system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.90% # Type of FU issued 407system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.90% # Type of FU issued 408system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.90% # Type of FU issued 409system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.90% # Type of FU issued 410system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.90% # Type of FU issued 411system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.90% # Type of FU issued 412system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.90% # Type of FU issued 413system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.90% # Type of FU issued 414system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.90% # Type of FU issued 415system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.90% # Type of FU issued 416system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.90% # Type of FU issued 417system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.90% # Type of FU issued 418system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.90% # Type of FU issued 419system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.90% # Type of FU issued 420system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.90% # Type of FU issued 421system.cpu.iq.FU_type_1::MemRead 2394 23.32% 89.22% # Type of FU issued 422system.cpu.iq.FU_type_1::MemWrite 1107 10.78% 100.00% # Type of FU issued 423system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 424system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued 425system.cpu.iq.FU_type_1::total 10268 # Type of FU issued 426system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued 427system.cpu.iq.FU_type::IntAlu 13732 65.78% 65.80% # Type of FU issued 428system.cpu.iq.FU_type::IntMult 2 0.01% 65.81% # Type of FU issued 429system.cpu.iq.FU_type::IntDiv 0 0.00% 65.81% # Type of FU issued 430system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.83% # Type of FU issued 431system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.83% # Type of FU issued 432system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.83% # Type of FU issued 433system.cpu.iq.FU_type::FloatMult 0 0.00% 65.83% # Type of FU issued 434system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.83% # Type of FU issued 435system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.83% # Type of FU issued 436system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.83% # Type of FU issued 437system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.83% # Type of FU issued 438system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.83% # Type of FU issued 439system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.83% # Type of FU issued 440system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.83% # Type of FU issued 441system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.83% # Type of FU issued 442system.cpu.iq.FU_type::SimdMult 0 0.00% 65.83% # Type of FU issued 443system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.83% # Type of FU issued 444system.cpu.iq.FU_type::SimdShift 0 0.00% 65.83% # Type of FU issued 445system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.83% # Type of FU issued 446system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.83% # Type of FU issued 447system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.83% # Type of FU issued 448system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.83% # Type of FU issued 449system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.83% # Type of FU issued 450system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.83% # Type of FU issued 451system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.83% # Type of FU issued 452system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.83% # Type of FU issued 453system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.83% # Type of FU issued 454system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.83% # Type of FU issued 455system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.83% # Type of FU issued 456system.cpu.iq.FU_type::MemRead 4919 23.56% 89.39% # Type of FU issued 457system.cpu.iq.FU_type::MemWrite 2214 10.61% 100.00% # Type of FU issued 458system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued 459system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued 460system.cpu.iq.FU_type::total 20875 # Type of FU issued 461system.cpu.iq.rate 0.426482 # Inst issue rate 462system.cpu.iq.fu_busy_cnt::0 83 # FU busy when requested 463system.cpu.iq.fu_busy_cnt::1 82 # FU busy when requested 464system.cpu.iq.fu_busy_cnt::total 165 # FU busy when requested 465system.cpu.iq.fu_busy_rate::0 0.003976 # FU busy rate (busy events/executed inst) 466system.cpu.iq.fu_busy_rate::1 0.003928 # FU busy rate (busy events/executed inst) 467system.cpu.iq.fu_busy_rate::total 0.007904 # FU busy rate (busy events/executed inst) 468system.cpu.iq.int_inst_queue_reads 70014 # Number of integer instruction queue reads 469system.cpu.iq.int_inst_queue_writes 36770 # Number of integer instruction queue writes 470system.cpu.iq.int_inst_queue_wakeup_accesses 18228 # Number of integer instruction queue wakeup accesses 471system.cpu.iq.fp_inst_queue_reads 41 # Number of floating instruction queue reads 472system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 473system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses 474system.cpu.iq.int_alu_accesses 21015 # Number of integer alu accesses 475system.cpu.iq.fp_alu_accesses 21 # Number of floating point alu accesses 476system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores 477system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 478system.cpu.iew.lsq.thread0.squashedLoads 1741 # Number of loads squashed 479system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 480system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations 481system.cpu.iew.lsq.thread0.squashedStores 465 # Number of stores squashed 482system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 483system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 484system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 485system.cpu.iew.lsq.thread0.cacheBlocked 427 # Number of times an access to memory failed due to the cache being blocked 486system.cpu.iew.lsq.thread1.forwLoads 57 # Number of loads that had data forwarded from stores 487system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address 488system.cpu.iew.lsq.thread1.squashedLoads 1553 # Number of loads squashed 489system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 490system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations 491system.cpu.iew.lsq.thread1.squashedStores 427 # Number of stores squashed 492system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 493system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 494system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled 495system.cpu.iew.lsq.thread1.cacheBlocked 302 # Number of times an access to memory failed due to the cache being blocked 496system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 497system.cpu.iew.iewSquashCycles 2426 # Number of cycles IEW is squashing 498system.cpu.iew.iewBlockCycles 2850 # Number of cycles IEW is blocking 499system.cpu.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking 500system.cpu.iew.iewDispatchedInsts 25356 # Number of instructions dispatched to IQ 501system.cpu.iew.iewDispSquashedInsts 534 # Number of squashed instructions skipped by dispatch 502system.cpu.iew.iewDispLoadInsts 5660 # Number of dispatched load instructions 503system.cpu.iew.iewDispStoreInsts 2622 # Number of dispatched store instructions 504system.cpu.iew.iewDispNonSpecInsts 73 # Number of dispatched non-speculative instructions 505system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall 506system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall 507system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations 508system.cpu.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly 509system.cpu.iew.predictedNotTakenIncorrect 905 # Number of branches that were predicted not taken incorrectly 510system.cpu.iew.branchMispredicts 1123 # Number of branch mispredicts detected at execute 511system.cpu.iew.iewExecutedInsts 19630 # Number of executed instructions 512system.cpu.iew.iewExecLoadInsts::0 2348 # Number of load instructions executed 513system.cpu.iew.iewExecLoadInsts::1 2224 # Number of load instructions executed 514system.cpu.iew.iewExecLoadInsts::total 4572 # Number of load instructions executed 515system.cpu.iew.iewExecSquashedInsts 1245 # Number of squashed instructions skipped in execute 516system.cpu.iew.exec_swp::0 0 # number of swp insts executed 517system.cpu.iew.exec_swp::1 0 # number of swp insts executed 518system.cpu.iew.exec_swp::total 0 # number of swp insts executed 519system.cpu.iew.exec_nop::0 98 # number of nop insts executed 520system.cpu.iew.exec_nop::1 81 # number of nop insts executed 521system.cpu.iew.exec_nop::total 179 # number of nop insts executed 522system.cpu.iew.exec_refs::0 3414 # number of memory reference insts executed 523system.cpu.iew.exec_refs::1 3275 # number of memory reference insts executed 524system.cpu.iew.exec_refs::total 6689 # number of memory reference insts executed 525system.cpu.iew.exec_branches::0 1527 # Number of branches executed 526system.cpu.iew.exec_branches::1 1521 # Number of branches executed 527system.cpu.iew.exec_branches::total 3048 # Number of branches executed 528system.cpu.iew.exec_stores::0 1066 # Number of stores executed 529system.cpu.iew.exec_stores::1 1051 # Number of stores executed 530system.cpu.iew.exec_stores::total 2117 # Number of stores executed 531system.cpu.iew.exec_rate 0.401046 # Inst execution rate 532system.cpu.iew.wb_sent::0 9349 # cumulative count of insts sent to commit 533system.cpu.iew.wb_sent::1 9181 # cumulative count of insts sent to commit 534system.cpu.iew.wb_sent::total 18530 # cumulative count of insts sent to commit 535system.cpu.iew.wb_count::0 9210 # cumulative count of insts written-back 536system.cpu.iew.wb_count::1 9038 # cumulative count of insts written-back 537system.cpu.iew.wb_count::total 18248 # cumulative count of insts written-back 538system.cpu.iew.wb_producers::0 4725 # num instructions producing a value 539system.cpu.iew.wb_producers::1 4632 # num instructions producing a value 540system.cpu.iew.wb_producers::total 9357 # num instructions producing a value 541system.cpu.iew.wb_consumers::0 6193 # num instructions consuming a value 542system.cpu.iew.wb_consumers::1 6064 # num instructions consuming a value 543system.cpu.iew.wb_consumers::total 12257 # num instructions consuming a value 544system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ 545system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ 546system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ 547system.cpu.iew.wb_rate::0 0.188163 # insts written-back per cycle 548system.cpu.iew.wb_rate::1 0.184649 # insts written-back per cycle 549system.cpu.iew.wb_rate::total 0.372811 # insts written-back per cycle 550system.cpu.iew.wb_fanout::0 0.762958 # average fanout of values written-back 551system.cpu.iew.wb_fanout::1 0.763852 # average fanout of values written-back 552system.cpu.iew.wb_fanout::total 0.763401 # average fanout of values written-back 553system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ 554system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ 555system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ 556system.cpu.commit.commitSquashedInsts 12589 # The number of squashed insts skipped by commit 557system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards 558system.cpu.commit.branchMispredicts 957 # The number of times a branch was mispredicted 559system.cpu.commit.committed_per_cycle::samples 28025 # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::mean 0.455986 # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::stdev 1.237353 # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::0 22265 79.45% 79.45% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::1 3171 11.31% 90.76% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::2 1034 3.69% 94.45% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::3 483 1.72% 96.17% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::4 332 1.18% 97.36% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::5 227 0.81% 98.17% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::6 200 0.71% 98.88% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::7 76 0.27% 99.15% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::8 237 0.85% 100.00% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::total 28025 # Number of insts commited each cycle 576system.cpu.commit.committedInsts::0 6389 # Number of instructions committed 577system.cpu.commit.committedInsts::1 6390 # Number of instructions committed 578system.cpu.commit.committedInsts::total 12779 # Number of instructions committed 579system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed 580system.cpu.commit.committedOps::1 6390 # Number of ops (including micro ops) committed 581system.cpu.commit.committedOps::total 12779 # Number of ops (including micro ops) committed 582system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 583system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed 584system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed 585system.cpu.commit.refs::0 2048 # Number of memory references committed 586system.cpu.commit.refs::1 2048 # Number of memory references committed 587system.cpu.commit.refs::total 4096 # Number of memory references committed 588system.cpu.commit.loads::0 1183 # Number of loads committed 589system.cpu.commit.loads::1 1183 # Number of loads committed 590system.cpu.commit.loads::total 2366 # Number of loads committed 591system.cpu.commit.membars::0 0 # Number of memory barriers committed 592system.cpu.commit.membars::1 0 # Number of memory barriers committed 593system.cpu.commit.membars::total 0 # Number of memory barriers committed 594system.cpu.commit.branches::0 1050 # Number of branches committed 595system.cpu.commit.branches::1 1050 # Number of branches committed 596system.cpu.commit.branches::total 2100 # Number of branches committed 597system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. 598system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. 599system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. 600system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions. 601system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions. 602system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions. 603system.cpu.commit.function_calls::0 127 # Number of function calls committed. 604system.cpu.commit.function_calls::1 127 # Number of function calls committed. 605system.cpu.commit.function_calls::total 254 # Number of function calls committed. 606system.cpu.commit.bw_lim_events 237 # number cycles where commit BW limit reached 607system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits 608system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits 609system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits 610system.cpu.rob.rob_reads 126869 # The number of ROB reads 611system.cpu.rob.rob_writes 53172 # The number of ROB writes 612system.cpu.timesIdled 388 # Number of times that the entire CPU went into an idle state and unscheduled itself 613system.cpu.idleCycles 20877 # Total number of cycles that the CPU has spent unscheduled due to idling 614system.cpu.committedInsts::0 6372 # Number of Instructions Simulated 615system.cpu.committedInsts::1 6373 # Number of Instructions Simulated 616system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated 617system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated 618system.cpu.committedInsts_total 12745 # Number of Instructions Simulated 619system.cpu.cpi::0 7.681576 # CPI: Cycles Per Instruction 620system.cpu.cpi::1 7.680370 # CPI: Cycles Per Instruction 621system.cpu.cpi_total 3.840486 # CPI: Total CPI of All Threads 622system.cpu.ipc::0 0.130182 # IPC: Instructions Per Cycle 623system.cpu.ipc::1 0.130202 # IPC: Instructions Per Cycle 624system.cpu.ipc_total 0.260384 # IPC: Total IPC of All Threads 625system.cpu.int_regfile_reads 24701 # number of integer regfile reads 626system.cpu.int_regfile_writes 13755 # number of integer regfile writes 627system.cpu.fp_regfile_reads 16 # number of floating regfile reads 628system.cpu.fp_regfile_writes 4 # number of floating regfile writes 629system.cpu.misc_regfile_reads 2 # number of misc regfile reads 630system.cpu.misc_regfile_writes 2 # number of misc regfile writes 631system.cpu.icache.replacements::0 6 # number of replacements 632system.cpu.icache.replacements::1 0 # number of replacements 633system.cpu.icache.replacements::total 6 # number of replacements 634system.cpu.icache.tagsinuse 292.522712 # Cycle average of tags in use 635system.cpu.icache.total_refs 3780 # Total number of references to valid blocks. 636system.cpu.icache.sampled_refs 624 # Sample count of references to valid blocks. 637system.cpu.icache.avg_refs 6.057692 # Average number of references to valid blocks. 638system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 639system.cpu.icache.occ_blocks::cpu.inst 292.522712 # Average occupied blocks per requestor 640system.cpu.icache.occ_percent::cpu.inst 0.142833 # Average percentage of cache occupancy 641system.cpu.icache.occ_percent::total 0.142833 # Average percentage of cache occupancy 642system.cpu.icache.ReadReq_hits::cpu.inst 3780 # number of ReadReq hits 643system.cpu.icache.ReadReq_hits::total 3780 # number of ReadReq hits 644system.cpu.icache.demand_hits::cpu.inst 3780 # number of demand (read+write) hits 645system.cpu.icache.demand_hits::total 3780 # number of demand (read+write) hits 646system.cpu.icache.overall_hits::cpu.inst 3780 # number of overall hits 647system.cpu.icache.overall_hits::total 3780 # number of overall hits 648system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses 649system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses 650system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses 651system.cpu.icache.demand_misses::total 1049 # number of demand (read+write) misses 652system.cpu.icache.overall_misses::cpu.inst 1049 # number of overall misses 653system.cpu.icache.overall_misses::total 1049 # number of overall misses 654system.cpu.icache.ReadReq_miss_latency::cpu.inst 78577996 # number of ReadReq miss cycles 655system.cpu.icache.ReadReq_miss_latency::total 78577996 # number of ReadReq miss cycles 656system.cpu.icache.demand_miss_latency::cpu.inst 78577996 # number of demand (read+write) miss cycles 657system.cpu.icache.demand_miss_latency::total 78577996 # number of demand (read+write) miss cycles 658system.cpu.icache.overall_miss_latency::cpu.inst 78577996 # number of overall miss cycles 659system.cpu.icache.overall_miss_latency::total 78577996 # number of overall miss cycles 660system.cpu.icache.ReadReq_accesses::cpu.inst 4829 # number of ReadReq accesses(hits+misses) 661system.cpu.icache.ReadReq_accesses::total 4829 # number of ReadReq accesses(hits+misses) 662system.cpu.icache.demand_accesses::cpu.inst 4829 # number of demand (read+write) accesses 663system.cpu.icache.demand_accesses::total 4829 # number of demand (read+write) accesses 664system.cpu.icache.overall_accesses::cpu.inst 4829 # number of overall (read+write) accesses 665system.cpu.icache.overall_accesses::total 4829 # number of overall (read+write) accesses 666system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217229 # miss rate for ReadReq accesses 667system.cpu.icache.ReadReq_miss_rate::total 0.217229 # miss rate for ReadReq accesses 668system.cpu.icache.demand_miss_rate::cpu.inst 0.217229 # miss rate for demand accesses 669system.cpu.icache.demand_miss_rate::total 0.217229 # miss rate for demand accesses 670system.cpu.icache.overall_miss_rate::cpu.inst 0.217229 # miss rate for overall accesses 671system.cpu.icache.overall_miss_rate::total 0.217229 # miss rate for overall accesses 672system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74907.527169 # average ReadReq miss latency 673system.cpu.icache.ReadReq_avg_miss_latency::total 74907.527169 # average ReadReq miss latency 674system.cpu.icache.demand_avg_miss_latency::cpu.inst 74907.527169 # average overall miss latency 675system.cpu.icache.demand_avg_miss_latency::total 74907.527169 # average overall miss latency 676system.cpu.icache.overall_avg_miss_latency::cpu.inst 74907.527169 # average overall miss latency 677system.cpu.icache.overall_avg_miss_latency::total 74907.527169 # average overall miss latency 678system.cpu.icache.blocked_cycles::no_mshrs 3158 # number of cycles access was blocked 679system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 680system.cpu.icache.blocked::no_mshrs 66 # number of cycles access was blocked 681system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 682system.cpu.icache.avg_blocked_cycles::no_mshrs 47.848485 # average number of cycles each access was blocked 683system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 684system.cpu.icache.fast_writes 0 # number of fast writes performed 685system.cpu.icache.cache_copies 0 # number of cache copies performed 686system.cpu.icache.ReadReq_mshr_hits::cpu.inst 425 # number of ReadReq MSHR hits 687system.cpu.icache.ReadReq_mshr_hits::total 425 # number of ReadReq MSHR hits 688system.cpu.icache.demand_mshr_hits::cpu.inst 425 # number of demand (read+write) MSHR hits 689system.cpu.icache.demand_mshr_hits::total 425 # number of demand (read+write) MSHR hits 690system.cpu.icache.overall_mshr_hits::cpu.inst 425 # number of overall MSHR hits 691system.cpu.icache.overall_mshr_hits::total 425 # number of overall MSHR hits 692system.cpu.icache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses 693system.cpu.icache.ReadReq_mshr_misses::total 624 # number of ReadReq MSHR misses 694system.cpu.icache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses 695system.cpu.icache.demand_mshr_misses::total 624 # number of demand (read+write) MSHR misses 696system.cpu.icache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses 697system.cpu.icache.overall_mshr_misses::total 624 # number of overall MSHR misses 698system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48453998 # number of ReadReq MSHR miss cycles 699system.cpu.icache.ReadReq_mshr_miss_latency::total 48453998 # number of ReadReq MSHR miss cycles 700system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48453998 # number of demand (read+write) MSHR miss cycles 701system.cpu.icache.demand_mshr_miss_latency::total 48453998 # number of demand (read+write) MSHR miss cycles 702system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48453998 # number of overall MSHR miss cycles 703system.cpu.icache.overall_mshr_miss_latency::total 48453998 # number of overall MSHR miss cycles 704system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.129219 # mshr miss rate for ReadReq accesses 705system.cpu.icache.ReadReq_mshr_miss_rate::total 0.129219 # mshr miss rate for ReadReq accesses 706system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.129219 # mshr miss rate for demand accesses 707system.cpu.icache.demand_mshr_miss_rate::total 0.129219 # mshr miss rate for demand accesses 708system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.129219 # mshr miss rate for overall accesses 709system.cpu.icache.overall_mshr_miss_rate::total 0.129219 # mshr miss rate for overall accesses 710system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77650.637821 # average ReadReq mshr miss latency 711system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77650.637821 # average ReadReq mshr miss latency 712system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77650.637821 # average overall mshr miss latency 713system.cpu.icache.demand_avg_mshr_miss_latency::total 77650.637821 # average overall mshr miss latency 714system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77650.637821 # average overall mshr miss latency 715system.cpu.icache.overall_avg_mshr_miss_latency::total 77650.637821 # average overall mshr miss latency 716system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 717system.cpu.l2cache.replacements::0 0 # number of replacements 718system.cpu.l2cache.replacements::1 0 # number of replacements 719system.cpu.l2cache.replacements::total 0 # number of replacements 720system.cpu.l2cache.tagsinuse 407.828883 # Cycle average of tags in use 721system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 722system.cpu.l2cache.sampled_refs 824 # Sample count of references to valid blocks. 723system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. 724system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 725system.cpu.l2cache.occ_blocks::cpu.inst 293.011617 # Average occupied blocks per requestor 726system.cpu.l2cache.occ_blocks::cpu.data 114.817266 # Average occupied blocks per requestor 727system.cpu.l2cache.occ_percent::cpu.inst 0.008942 # Average percentage of cache occupancy 728system.cpu.l2cache.occ_percent::cpu.data 0.003504 # Average percentage of cache occupancy 729system.cpu.l2cache.occ_percent::total 0.012446 # Average percentage of cache occupancy 730system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 731system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 732system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 733system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 734system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 735system.cpu.l2cache.overall_hits::total 2 # number of overall hits 736system.cpu.l2cache.ReadReq_misses::cpu.inst 622 # number of ReadReq misses 737system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses 738system.cpu.l2cache.ReadReq_misses::total 824 # number of ReadReq misses 739system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses 740system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses 741system.cpu.l2cache.demand_misses::cpu.inst 622 # number of demand (read+write) misses 742system.cpu.l2cache.demand_misses::cpu.data 348 # number of demand (read+write) misses 743system.cpu.l2cache.demand_misses::total 970 # number of demand (read+write) misses 744system.cpu.l2cache.overall_misses::cpu.inst 622 # number of overall misses 745system.cpu.l2cache.overall_misses::cpu.data 348 # number of overall misses 746system.cpu.l2cache.overall_misses::total 970 # number of overall misses 747system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 47808000 # number of ReadReq miss cycles 748system.cpu.l2cache.ReadReq_miss_latency::cpu.data 18056500 # number of ReadReq miss cycles 749system.cpu.l2cache.ReadReq_miss_latency::total 65864500 # number of ReadReq miss cycles 750system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12124000 # number of ReadExReq miss cycles 751system.cpu.l2cache.ReadExReq_miss_latency::total 12124000 # number of ReadExReq miss cycles 752system.cpu.l2cache.demand_miss_latency::cpu.inst 47808000 # number of demand (read+write) miss cycles 753system.cpu.l2cache.demand_miss_latency::cpu.data 30180500 # number of demand (read+write) miss cycles 754system.cpu.l2cache.demand_miss_latency::total 77988500 # number of demand (read+write) miss cycles 755system.cpu.l2cache.overall_miss_latency::cpu.inst 47808000 # number of overall miss cycles 756system.cpu.l2cache.overall_miss_latency::cpu.data 30180500 # number of overall miss cycles 757system.cpu.l2cache.overall_miss_latency::total 77988500 # number of overall miss cycles 758system.cpu.l2cache.ReadReq_accesses::cpu.inst 624 # number of ReadReq accesses(hits+misses) 759system.cpu.l2cache.ReadReq_accesses::cpu.data 202 # number of ReadReq accesses(hits+misses) 760system.cpu.l2cache.ReadReq_accesses::total 826 # number of ReadReq accesses(hits+misses) 761system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) 762system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) 763system.cpu.l2cache.demand_accesses::cpu.inst 624 # number of demand (read+write) accesses 764system.cpu.l2cache.demand_accesses::cpu.data 348 # number of demand (read+write) accesses 765system.cpu.l2cache.demand_accesses::total 972 # number of demand (read+write) accesses 766system.cpu.l2cache.overall_accesses::cpu.inst 624 # number of overall (read+write) accesses 767system.cpu.l2cache.overall_accesses::cpu.data 348 # number of overall (read+write) accesses 768system.cpu.l2cache.overall_accesses::total 972 # number of overall (read+write) accesses 769system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996795 # miss rate for ReadReq accesses 770system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 771system.cpu.l2cache.ReadReq_miss_rate::total 0.997579 # miss rate for ReadReq accesses 772system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 773system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 774system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses 775system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 776system.cpu.l2cache.demand_miss_rate::total 0.997942 # miss rate for demand accesses 777system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses 778system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 779system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses 780system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76861.736334 # average ReadReq miss latency 781system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89388.613861 # average ReadReq miss latency 782system.cpu.l2cache.ReadReq_avg_miss_latency::total 79932.645631 # average ReadReq miss latency 783system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83041.095890 # average ReadExReq miss latency 784system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83041.095890 # average ReadExReq miss latency 785system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76861.736334 # average overall miss latency 786system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86725.574713 # average overall miss latency 787system.cpu.l2cache.demand_avg_miss_latency::total 80400.515464 # average overall miss latency 788system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76861.736334 # average overall miss latency 789system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86725.574713 # average overall miss latency 790system.cpu.l2cache.overall_avg_miss_latency::total 80400.515464 # average overall miss latency 791system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 792system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 793system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 794system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 795system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 796system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 797system.cpu.l2cache.fast_writes 0 # number of fast writes performed 798system.cpu.l2cache.cache_copies 0 # number of cache copies performed 799system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 622 # number of ReadReq MSHR misses 800system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses 801system.cpu.l2cache.ReadReq_mshr_misses::total 824 # number of ReadReq MSHR misses 802system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses 803system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses 804system.cpu.l2cache.demand_mshr_misses::cpu.inst 622 # number of demand (read+write) MSHR misses 805system.cpu.l2cache.demand_mshr_misses::cpu.data 348 # number of demand (read+write) MSHR misses 806system.cpu.l2cache.demand_mshr_misses::total 970 # number of demand (read+write) MSHR misses 807system.cpu.l2cache.overall_mshr_misses::cpu.inst 622 # number of overall MSHR misses 808system.cpu.l2cache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses 809system.cpu.l2cache.overall_mshr_misses::total 970 # number of overall MSHR misses 810system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40142034 # number of ReadReq MSHR miss cycles 811system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15600631 # number of ReadReq MSHR miss cycles 812system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55742665 # number of ReadReq MSHR miss cycles 813system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10339864 # number of ReadExReq MSHR miss cycles 814system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10339864 # number of ReadExReq MSHR miss cycles 815system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40142034 # number of demand (read+write) MSHR miss cycles 816system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25940495 # number of demand (read+write) MSHR miss cycles 817system.cpu.l2cache.demand_mshr_miss_latency::total 66082529 # number of demand (read+write) MSHR miss cycles 818system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40142034 # number of overall MSHR miss cycles 819system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25940495 # number of overall MSHR miss cycles 820system.cpu.l2cache.overall_mshr_miss_latency::total 66082529 # number of overall MSHR miss cycles 821system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses 822system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 823system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997579 # mshr miss rate for ReadReq accesses 824system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 825system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 826system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses 827system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 828system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses 829system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses 830system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 831system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses 832system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64537.032154 # average ReadReq mshr miss latency 833system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77230.846535 # average ReadReq mshr miss latency 834system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67648.865291 # average ReadReq mshr miss latency 835system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70820.986301 # average ReadExReq mshr miss latency 836system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70820.986301 # average ReadExReq mshr miss latency 837system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency 838system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency 839system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency 840system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency 841system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency 842system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency 843system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 844system.cpu.dcache.replacements::0 0 # number of replacements 845system.cpu.dcache.replacements::1 0 # number of replacements 846system.cpu.dcache.replacements::total 0 # number of replacements 847system.cpu.dcache.tagsinuse 202.984846 # Cycle average of tags in use 848system.cpu.dcache.total_refs 4338 # Total number of references to valid blocks. 849system.cpu.dcache.sampled_refs 348 # Sample count of references to valid blocks. 850system.cpu.dcache.avg_refs 12.465517 # Average number of references to valid blocks. 851system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 852system.cpu.dcache.occ_blocks::cpu.data 202.984846 # Average occupied blocks per requestor 853system.cpu.dcache.occ_percent::cpu.data 0.049557 # Average percentage of cache occupancy 854system.cpu.dcache.occ_percent::total 0.049557 # Average percentage of cache occupancy 855system.cpu.dcache.ReadReq_hits::cpu.data 3316 # number of ReadReq hits 856system.cpu.dcache.ReadReq_hits::total 3316 # number of ReadReq hits 857system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits 858system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits 859system.cpu.dcache.demand_hits::cpu.data 4338 # number of demand (read+write) hits 860system.cpu.dcache.demand_hits::total 4338 # number of demand (read+write) hits 861system.cpu.dcache.overall_hits::cpu.data 4338 # number of overall hits 862system.cpu.dcache.overall_hits::total 4338 # number of overall hits 863system.cpu.dcache.ReadReq_misses::cpu.data 320 # number of ReadReq misses 864system.cpu.dcache.ReadReq_misses::total 320 # number of ReadReq misses 865system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses 866system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses 867system.cpu.dcache.demand_misses::cpu.data 1028 # number of demand (read+write) misses 868system.cpu.dcache.demand_misses::total 1028 # number of demand (read+write) misses 869system.cpu.dcache.overall_misses::cpu.data 1028 # number of overall misses 870system.cpu.dcache.overall_misses::total 1028 # number of overall misses 871system.cpu.dcache.ReadReq_miss_latency::cpu.data 26222500 # number of ReadReq miss cycles 872system.cpu.dcache.ReadReq_miss_latency::total 26222500 # number of ReadReq miss cycles 873system.cpu.dcache.WriteReq_miss_latency::cpu.data 53389967 # number of WriteReq miss cycles 874system.cpu.dcache.WriteReq_miss_latency::total 53389967 # number of WriteReq miss cycles 875system.cpu.dcache.demand_miss_latency::cpu.data 79612467 # number of demand (read+write) miss cycles 876system.cpu.dcache.demand_miss_latency::total 79612467 # number of demand (read+write) miss cycles 877system.cpu.dcache.overall_miss_latency::cpu.data 79612467 # number of overall miss cycles 878system.cpu.dcache.overall_miss_latency::total 79612467 # number of overall miss cycles 879system.cpu.dcache.ReadReq_accesses::cpu.data 3636 # number of ReadReq accesses(hits+misses) 880system.cpu.dcache.ReadReq_accesses::total 3636 # number of ReadReq accesses(hits+misses) 881system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) 882system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) 883system.cpu.dcache.demand_accesses::cpu.data 5366 # number of demand (read+write) accesses 884system.cpu.dcache.demand_accesses::total 5366 # number of demand (read+write) accesses 885system.cpu.dcache.overall_accesses::cpu.data 5366 # number of overall (read+write) accesses 886system.cpu.dcache.overall_accesses::total 5366 # number of overall (read+write) accesses 887system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.088009 # miss rate for ReadReq accesses 888system.cpu.dcache.ReadReq_miss_rate::total 0.088009 # miss rate for ReadReq accesses 889system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses 890system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses 891system.cpu.dcache.demand_miss_rate::cpu.data 0.191577 # miss rate for demand accesses 892system.cpu.dcache.demand_miss_rate::total 0.191577 # miss rate for demand accesses 893system.cpu.dcache.overall_miss_rate::cpu.data 0.191577 # miss rate for overall accesses 894system.cpu.dcache.overall_miss_rate::total 0.191577 # miss rate for overall accesses 895system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81945.312500 # average ReadReq miss latency 896system.cpu.dcache.ReadReq_avg_miss_latency::total 81945.312500 # average ReadReq miss latency 897system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75409.557910 # average WriteReq miss latency 898system.cpu.dcache.WriteReq_avg_miss_latency::total 75409.557910 # average WriteReq miss latency 899system.cpu.dcache.demand_avg_miss_latency::cpu.data 77444.034047 # average overall miss latency 900system.cpu.dcache.demand_avg_miss_latency::total 77444.034047 # average overall miss latency 901system.cpu.dcache.overall_avg_miss_latency::cpu.data 77444.034047 # average overall miss latency 902system.cpu.dcache.overall_avg_miss_latency::total 77444.034047 # average overall miss latency 903system.cpu.dcache.blocked_cycles::no_mshrs 4583 # number of cycles access was blocked 904system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 905system.cpu.dcache.blocked::no_mshrs 91 # number of cycles access was blocked 906system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 907system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.362637 # average number of cycles each access was blocked 908system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 909system.cpu.dcache.fast_writes 0 # number of fast writes performed 910system.cpu.dcache.cache_copies 0 # number of cache copies performed 911system.cpu.dcache.ReadReq_mshr_hits::cpu.data 118 # number of ReadReq MSHR hits 912system.cpu.dcache.ReadReq_mshr_hits::total 118 # number of ReadReq MSHR hits 913system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits 914system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits 915system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits 916system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits 917system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits 918system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits 919system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses 920system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses 921system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses 922system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses 923system.cpu.dcache.demand_mshr_misses::cpu.data 348 # number of demand (read+write) MSHR misses 924system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses 925system.cpu.dcache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses 926system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses 927system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18267500 # number of ReadReq MSHR miss cycles 928system.cpu.dcache.ReadReq_mshr_miss_latency::total 18267500 # number of ReadReq MSHR miss cycles 929system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12271498 # number of WriteReq MSHR miss cycles 930system.cpu.dcache.WriteReq_mshr_miss_latency::total 12271498 # number of WriteReq MSHR miss cycles 931system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30538998 # number of demand (read+write) MSHR miss cycles 932system.cpu.dcache.demand_mshr_miss_latency::total 30538998 # number of demand (read+write) MSHR miss cycles 933system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30538998 # number of overall MSHR miss cycles 934system.cpu.dcache.overall_mshr_miss_latency::total 30538998 # number of overall MSHR miss cycles 935system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055556 # mshr miss rate for ReadReq accesses 936system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055556 # mshr miss rate for ReadReq accesses 937system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 938system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 939system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064853 # mshr miss rate for demand accesses 940system.cpu.dcache.demand_mshr_miss_rate::total 0.064853 # mshr miss rate for demand accesses 941system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064853 # mshr miss rate for overall accesses 942system.cpu.dcache.overall_mshr_miss_rate::total 0.064853 # mshr miss rate for overall accesses 943system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90433.168317 # average ReadReq mshr miss latency 944system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90433.168317 # average ReadReq mshr miss latency 945system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84051.356164 # average WriteReq mshr miss latency 946system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84051.356164 # average WriteReq mshr miss latency 947system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87755.741379 # average overall mshr miss latency 948system.cpu.dcache.demand_avg_mshr_miss_latency::total 87755.741379 # average overall mshr miss latency 949system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87755.741379 # average overall mshr miss latency 950system.cpu.dcache.overall_avg_mshr_miss_latency::total 87755.741379 # average overall mshr miss latency 951system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 952 953---------- End Simulation Statistics ---------- 954