stats.txt revision 6127
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 105048 # Simulator instruction rate (inst/s) 4host_mem_usage 203136 # Number of bytes of host memory used 5host_seconds 0.12 # Real time elapsed on the host 6host_tick_rate 116961296 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 12773 # Number of instructions simulated 9sim_seconds 0.000014 # Number of seconds simulated 10sim_ticks 14251500 # Number of ticks simulated 11system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 12system.cpu.BPredUnit.BTBHits 916 # Number of BTB hits 13system.cpu.BPredUnit.BTBLookups 4733 # Number of BTB lookups 14system.cpu.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. 15system.cpu.BPredUnit.condIncorrect 1595 # Number of conditional branches incorrect 16system.cpu.BPredUnit.condPredicted 3153 # Number of conditional branches predicted 17system.cpu.BPredUnit.lookups 5548 # Number of BP lookups 18system.cpu.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target. 19system.cpu.commit.COM:branches::0 1051 # Number of branches committed 20system.cpu.commit.COM:branches::1 1051 # Number of branches committed 21system.cpu.commit.COM:branches::total 2102 # Number of branches committed 22system.cpu.commit.COM:bw_lim_events 122 # number cycles where commit BW limit reached 23system.cpu.commit.COM:bw_limited::0 0 # number of insts not committed due to BW limits 24system.cpu.commit.COM:bw_limited::1 0 # number of insts not committed due to BW limits 25system.cpu.commit.COM:bw_limited::total 0 # number of insts not committed due to BW limits 26system.cpu.commit.COM:committed_per_cycle::samples 22838 # Number of insts commited each cycle 27system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle 28system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle 29system.cpu.commit.COM:committed_per_cycle::0-1 16881 73.92% # Number of insts commited each cycle 30system.cpu.commit.COM:committed_per_cycle::1-2 3016 13.21% # Number of insts commited each cycle 31system.cpu.commit.COM:committed_per_cycle::2-3 1386 6.07% # Number of insts commited each cycle 32system.cpu.commit.COM:committed_per_cycle::3-4 576 2.52% # Number of insts commited each cycle 33system.cpu.commit.COM:committed_per_cycle::4-5 326 1.43% # Number of insts commited each cycle 34system.cpu.commit.COM:committed_per_cycle::5-6 268 1.17% # Number of insts commited each cycle 35system.cpu.commit.COM:committed_per_cycle::6-7 170 0.74% # Number of insts commited each cycle 36system.cpu.commit.COM:committed_per_cycle::7-8 93 0.41% # Number of insts commited each cycle 37system.cpu.commit.COM:committed_per_cycle::8 122 0.53% # Number of insts commited each cycle 38system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle 39system.cpu.commit.COM:committed_per_cycle::total 22838 # Number of insts commited each cycle 40system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle 41system.cpu.commit.COM:committed_per_cycle::mean 0.560776 # Number of insts commited each cycle 42system.cpu.commit.COM:committed_per_cycle::stdev 1.272228 # Number of insts commited each cycle 43system.cpu.commit.COM:count::0 6403 # Number of instructions committed 44system.cpu.commit.COM:count::1 6404 # Number of instructions committed 45system.cpu.commit.COM:count::total 12807 # Number of instructions committed 46system.cpu.commit.COM:loads::0 1185 # Number of loads committed 47system.cpu.commit.COM:loads::1 1185 # Number of loads committed 48system.cpu.commit.COM:loads::total 2370 # Number of loads committed 49system.cpu.commit.COM:membars::0 0 # Number of memory barriers committed 50system.cpu.commit.COM:membars::1 0 # Number of memory barriers committed 51system.cpu.commit.COM:membars::total 0 # Number of memory barriers committed 52system.cpu.commit.COM:refs::0 2050 # Number of memory references committed 53system.cpu.commit.COM:refs::1 2050 # Number of memory references committed 54system.cpu.commit.COM:refs::total 4100 # Number of memory references committed 55system.cpu.commit.COM:swp_count::0 0 # Number of s/w prefetches committed 56system.cpu.commit.COM:swp_count::1 0 # Number of s/w prefetches committed 57system.cpu.commit.COM:swp_count::total 0 # Number of s/w prefetches committed 58system.cpu.commit.branchMispredicts 1166 # The number of times a branch was mispredicted 59system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions 60system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards 61system.cpu.commit.commitSquashedInsts 10895 # The number of squashed insts skipped by commit 62system.cpu.committedInsts::0 6386 # Number of Instructions Simulated 63system.cpu.committedInsts::1 6387 # Number of Instructions Simulated 64system.cpu.committedInsts_total 12773 # Number of Instructions Simulated 65system.cpu.cpi::0 4.463514 # CPI: Cycles Per Instruction 66system.cpu.cpi::1 4.462815 # CPI: Cycles Per Instruction 67system.cpu.cpi_total 2.231582 # CPI: Total CPI of All Threads 68system.cpu.dcache.ReadReq_accesses::0 3925 # number of ReadReq accesses(hits+misses) 69system.cpu.dcache.ReadReq_accesses::total 3925 # number of ReadReq accesses(hits+misses) 70system.cpu.dcache.ReadReq_avg_miss_latency::0 35473.913043 # average ReadReq miss latency 71system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36849.514563 # average ReadReq mshr miss latency 72system.cpu.dcache.ReadReq_hits::0 3580 # number of ReadReq hits 73system.cpu.dcache.ReadReq_hits::total 3580 # number of ReadReq hits 74system.cpu.dcache.ReadReq_miss_latency::0 12238500 # number of ReadReq miss cycles 75system.cpu.dcache.ReadReq_miss_latency::total 12238500 # number of ReadReq miss cycles 76system.cpu.dcache.ReadReq_miss_rate::0 0.087898 # miss rate for ReadReq accesses 77system.cpu.dcache.ReadReq_misses::0 345 # number of ReadReq misses 78system.cpu.dcache.ReadReq_misses::total 345 # number of ReadReq misses 79system.cpu.dcache.ReadReq_mshr_hits::0 139 # number of ReadReq MSHR hits 80system.cpu.dcache.ReadReq_mshr_hits::total 139 # number of ReadReq MSHR hits 81system.cpu.dcache.ReadReq_mshr_miss_latency::0 7591000 # number of ReadReq MSHR miss cycles 82system.cpu.dcache.ReadReq_mshr_miss_latency::total 7591000 # number of ReadReq MSHR miss cycles 83system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.052484 # mshr miss rate for ReadReq accesses 84system.cpu.dcache.ReadReq_mshr_misses::0 206 # number of ReadReq MSHR misses 85system.cpu.dcache.ReadReq_mshr_misses::total 206 # number of ReadReq MSHR misses 86system.cpu.dcache.WriteReq_accesses::0 1730 # number of WriteReq accesses(hits+misses) 87system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) 88system.cpu.dcache.WriteReq_avg_miss_latency::0 33703.947368 # average WriteReq miss latency 89system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36103.448276 # average WriteReq mshr miss latency 90system.cpu.dcache.WriteReq_hits::0 970 # number of WriteReq hits 91system.cpu.dcache.WriteReq_hits::total 970 # number of WriteReq hits 92system.cpu.dcache.WriteReq_miss_latency::0 25615000 # number of WriteReq miss cycles 93system.cpu.dcache.WriteReq_miss_latency::total 25615000 # number of WriteReq miss cycles 94system.cpu.dcache.WriteReq_miss_rate::0 0.439306 # miss rate for WriteReq accesses 95system.cpu.dcache.WriteReq_misses::0 760 # number of WriteReq misses 96system.cpu.dcache.WriteReq_misses::total 760 # number of WriteReq misses 97system.cpu.dcache.WriteReq_mshr_hits::0 586 # number of WriteReq MSHR hits 98system.cpu.dcache.WriteReq_mshr_hits::total 586 # number of WriteReq MSHR hits 99system.cpu.dcache.WriteReq_mshr_miss_latency::0 6282000 # number of WriteReq MSHR miss cycles 100system.cpu.dcache.WriteReq_mshr_miss_latency::total 6282000 # number of WriteReq MSHR miss cycles 101system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.100578 # mshr miss rate for WriteReq accesses 102system.cpu.dcache.WriteReq_mshr_misses::0 174 # number of WriteReq MSHR misses 103system.cpu.dcache.WriteReq_mshr_misses::total 174 # number of WriteReq MSHR misses 104system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 105system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 106system.cpu.dcache.avg_refs 13.102273 # Average number of references to valid blocks. 107system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 108system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 109system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 110system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 111system.cpu.dcache.cache_copies 0 # number of cache copies performed 112system.cpu.dcache.demand_accesses::0 5655 # number of demand (read+write) accesses 113system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 114system.cpu.dcache.demand_accesses::total 5655 # number of demand (read+write) accesses 115system.cpu.dcache.demand_avg_miss_latency::0 34256.561086 # average overall miss latency 116system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency 117system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency 118system.cpu.dcache.demand_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency 119system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 120system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 121system.cpu.dcache.demand_hits::0 4550 # number of demand (read+write) hits 122system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 123system.cpu.dcache.demand_hits::total 4550 # number of demand (read+write) hits 124system.cpu.dcache.demand_miss_latency::0 37853500 # number of demand (read+write) miss cycles 125system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles 126system.cpu.dcache.demand_miss_latency::total 37853500 # number of demand (read+write) miss cycles 127system.cpu.dcache.demand_miss_rate::0 0.195402 # miss rate for demand accesses 128system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 129system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 130system.cpu.dcache.demand_misses::0 1105 # number of demand (read+write) misses 131system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 132system.cpu.dcache.demand_misses::total 1105 # number of demand (read+write) misses 133system.cpu.dcache.demand_mshr_hits::0 725 # number of demand (read+write) MSHR hits 134system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits 135system.cpu.dcache.demand_mshr_hits::total 725 # number of demand (read+write) MSHR hits 136system.cpu.dcache.demand_mshr_miss_latency::0 13873000 # number of demand (read+write) MSHR miss cycles 137system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles 138system.cpu.dcache.demand_mshr_miss_latency::total 13873000 # number of demand (read+write) MSHR miss cycles 139system.cpu.dcache.demand_mshr_miss_rate::0 0.067197 # mshr miss rate for demand accesses 140system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 141system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 142system.cpu.dcache.demand_mshr_misses::0 380 # number of demand (read+write) MSHR misses 143system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses 144system.cpu.dcache.demand_mshr_misses::total 380 # number of demand (read+write) MSHR misses 145system.cpu.dcache.fast_writes 0 # number of fast writes performed 146system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated 147system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated 148system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated 149system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 150system.cpu.dcache.overall_accesses::0 5655 # number of overall (read+write) accesses 151system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 152system.cpu.dcache.overall_accesses::total 5655 # number of overall (read+write) accesses 153system.cpu.dcache.overall_avg_miss_latency::0 34256.561086 # average overall miss latency 154system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency 155system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency 156system.cpu.dcache.overall_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency 157system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 158system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 159system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency 160system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency 161system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency 162system.cpu.dcache.overall_hits::0 4550 # number of overall hits 163system.cpu.dcache.overall_hits::1 0 # number of overall hits 164system.cpu.dcache.overall_hits::total 4550 # number of overall hits 165system.cpu.dcache.overall_miss_latency::0 37853500 # number of overall miss cycles 166system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles 167system.cpu.dcache.overall_miss_latency::total 37853500 # number of overall miss cycles 168system.cpu.dcache.overall_miss_rate::0 0.195402 # miss rate for overall accesses 169system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 170system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 171system.cpu.dcache.overall_misses::0 1105 # number of overall misses 172system.cpu.dcache.overall_misses::1 0 # number of overall misses 173system.cpu.dcache.overall_misses::total 1105 # number of overall misses 174system.cpu.dcache.overall_mshr_hits::0 725 # number of overall MSHR hits 175system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits 176system.cpu.dcache.overall_mshr_hits::total 725 # number of overall MSHR hits 177system.cpu.dcache.overall_mshr_miss_latency::0 13873000 # number of overall MSHR miss cycles 178system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles 179system.cpu.dcache.overall_mshr_miss_latency::total 13873000 # number of overall MSHR miss cycles 180system.cpu.dcache.overall_mshr_miss_rate::0 0.067197 # mshr miss rate for overall accesses 181system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 182system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 183system.cpu.dcache.overall_mshr_misses::0 380 # number of overall MSHR misses 184system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses 185system.cpu.dcache.overall_mshr_misses::total 380 # number of overall MSHR misses 186system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles 187system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles 188system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles 189system.cpu.dcache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses 190system.cpu.dcache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses 191system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses 192system.cpu.dcache.replacements::0 0 # number of replacements 193system.cpu.dcache.replacements::1 0 # number of replacements 194system.cpu.dcache.replacements::total 0 # number of replacements 195system.cpu.dcache.sampled_refs 352 # Sample count of references to valid blocks. 196system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions 197system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions 198system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions 199system.cpu.dcache.tagsinuse 223.700041 # Cycle average of tags in use 200system.cpu.dcache.total_refs 4612 # Total number of references to valid blocks. 201system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 202system.cpu.dcache.writebacks::0 0 # number of writebacks 203system.cpu.dcache.writebacks::1 0 # number of writebacks 204system.cpu.dcache.writebacks::total 0 # number of writebacks 205system.cpu.decode.DECODE:BlockedCycles 5063 # Number of cycles decode is blocked 206system.cpu.decode.DECODE:BranchMispred 441 # Number of times decode detected a branch misprediction 207system.cpu.decode.DECODE:BranchResolved 602 # Number of times decode resolved a branch 208system.cpu.decode.DECODE:DecodedInsts 27492 # Number of instructions handled by decode 209system.cpu.decode.DECODE:IdleCycles 33392 # Number of cycles decode is idle 210system.cpu.decode.DECODE:RunCycles 4878 # Number of cycles decode is running 211system.cpu.decode.DECODE:SquashCycles 2128 # Number of cycles decode is squashing 212system.cpu.decode.DECODE:SquashedInsts 668 # Number of squashed instructions handled by decode 213system.cpu.decode.DECODE:UnblockCycles 186 # Number of cycles decode is unblocking 214system.cpu.dtb.data_accesses 6300 # DTB accesses 215system.cpu.dtb.data_acv 0 # DTB access violations 216system.cpu.dtb.data_hits 6155 # DTB hits 217system.cpu.dtb.data_misses 145 # DTB misses 218system.cpu.dtb.fetch_accesses 0 # ITB accesses 219system.cpu.dtb.fetch_acv 0 # ITB acv 220system.cpu.dtb.fetch_hits 0 # ITB hits 221system.cpu.dtb.fetch_misses 0 # ITB misses 222system.cpu.dtb.read_accesses 4144 # DTB read accesses 223system.cpu.dtb.read_acv 0 # DTB read access violations 224system.cpu.dtb.read_hits 4056 # DTB read hits 225system.cpu.dtb.read_misses 88 # DTB read misses 226system.cpu.dtb.write_accesses 2156 # DTB write accesses 227system.cpu.dtb.write_acv 0 # DTB write access violations 228system.cpu.dtb.write_hits 2099 # DTB write hits 229system.cpu.dtb.write_misses 57 # DTB write misses 230system.cpu.fetch.Branches 5548 # Number of branches that fetch encountered 231system.cpu.fetch.CacheLines 4113 # Number of cache lines fetched 232system.cpu.fetch.Cycles 9444 # Number of cycles fetch has run and was not squashing or blocked 233system.cpu.fetch.IcacheSquashes 613 # Number of outstanding Icache misses that were squashed 234system.cpu.fetch.Insts 30949 # Number of instructions fetch has processed 235system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing 236system.cpu.fetch.branchRate 0.194639 # Number of branch fetches per cycle 237system.cpu.fetch.icacheStallCycles 4113 # Number of cycles fetch is stalled on an Icache miss 238system.cpu.fetch.predictedBranches 1597 # Number of branches that fetch has predicted taken 239system.cpu.fetch.rate 1.085777 # Number of inst fetches per cycle 240system.cpu.fetch.rateDist::samples 22904 # Number of instructions fetched each cycle (Total) 241system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 242system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) 243system.cpu.fetch.rateDist::0-1 17622 76.94% # Number of instructions fetched each cycle (Total) 244system.cpu.fetch.rateDist::1-2 416 1.82% # Number of instructions fetched each cycle (Total) 245system.cpu.fetch.rateDist::2-3 353 1.54% # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.rateDist::3-4 477 2.08% # Number of instructions fetched each cycle (Total) 247system.cpu.fetch.rateDist::4-5 425 1.86% # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::5-6 349 1.52% # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::6-7 442 1.93% # Number of instructions fetched each cycle (Total) 250system.cpu.fetch.rateDist::7-8 261 1.14% # Number of instructions fetched each cycle (Total) 251system.cpu.fetch.rateDist::8 2559 11.17% # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::total 22904 # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::mean 1.351249 # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::stdev 2.742840 # Number of instructions fetched each cycle (Total) 257system.cpu.icache.ReadReq_accesses::0 4113 # number of ReadReq accesses(hits+misses) 258system.cpu.icache.ReadReq_accesses::total 4113 # number of ReadReq accesses(hits+misses) 259system.cpu.icache.ReadReq_avg_miss_latency::0 35793.697979 # average ReadReq miss latency 260system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35516.155089 # average ReadReq mshr miss latency 261system.cpu.icache.ReadReq_hits::0 3272 # number of ReadReq hits 262system.cpu.icache.ReadReq_hits::total 3272 # number of ReadReq hits 263system.cpu.icache.ReadReq_miss_latency::0 30102500 # number of ReadReq miss cycles 264system.cpu.icache.ReadReq_miss_latency::total 30102500 # number of ReadReq miss cycles 265system.cpu.icache.ReadReq_miss_rate::0 0.204474 # miss rate for ReadReq accesses 266system.cpu.icache.ReadReq_misses::0 841 # number of ReadReq misses 267system.cpu.icache.ReadReq_misses::total 841 # number of ReadReq misses 268system.cpu.icache.ReadReq_mshr_hits::0 222 # number of ReadReq MSHR hits 269system.cpu.icache.ReadReq_mshr_hits::total 222 # number of ReadReq MSHR hits 270system.cpu.icache.ReadReq_mshr_miss_latency::0 21984500 # number of ReadReq MSHR miss cycles 271system.cpu.icache.ReadReq_mshr_miss_latency::total 21984500 # number of ReadReq MSHR miss cycles 272system.cpu.icache.ReadReq_mshr_miss_rate::0 0.150498 # mshr miss rate for ReadReq accesses 273system.cpu.icache.ReadReq_mshr_misses::0 619 # number of ReadReq MSHR misses 274system.cpu.icache.ReadReq_mshr_misses::total 619 # number of ReadReq MSHR misses 275system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 276system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 277system.cpu.icache.avg_refs 5.285945 # Average number of references to valid blocks. 278system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 279system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 280system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 281system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 282system.cpu.icache.cache_copies 0 # number of cache copies performed 283system.cpu.icache.demand_accesses::0 4113 # number of demand (read+write) accesses 284system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 285system.cpu.icache.demand_accesses::total 4113 # number of demand (read+write) accesses 286system.cpu.icache.demand_avg_miss_latency::0 35793.697979 # average overall miss latency 287system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency 288system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency 289system.cpu.icache.demand_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency 290system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 291system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 292system.cpu.icache.demand_hits::0 3272 # number of demand (read+write) hits 293system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 294system.cpu.icache.demand_hits::total 3272 # number of demand (read+write) hits 295system.cpu.icache.demand_miss_latency::0 30102500 # number of demand (read+write) miss cycles 296system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles 297system.cpu.icache.demand_miss_latency::total 30102500 # number of demand (read+write) miss cycles 298system.cpu.icache.demand_miss_rate::0 0.204474 # miss rate for demand accesses 299system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 300system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 301system.cpu.icache.demand_misses::0 841 # number of demand (read+write) misses 302system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 303system.cpu.icache.demand_misses::total 841 # number of demand (read+write) misses 304system.cpu.icache.demand_mshr_hits::0 222 # number of demand (read+write) MSHR hits 305system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits 306system.cpu.icache.demand_mshr_hits::total 222 # number of demand (read+write) MSHR hits 307system.cpu.icache.demand_mshr_miss_latency::0 21984500 # number of demand (read+write) MSHR miss cycles 308system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles 309system.cpu.icache.demand_mshr_miss_latency::total 21984500 # number of demand (read+write) MSHR miss cycles 310system.cpu.icache.demand_mshr_miss_rate::0 0.150498 # mshr miss rate for demand accesses 311system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 312system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 313system.cpu.icache.demand_mshr_misses::0 619 # number of demand (read+write) MSHR misses 314system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses 315system.cpu.icache.demand_mshr_misses::total 619 # number of demand (read+write) MSHR misses 316system.cpu.icache.fast_writes 0 # number of fast writes performed 317system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated 318system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated 319system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated 320system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 321system.cpu.icache.overall_accesses::0 4113 # number of overall (read+write) accesses 322system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 323system.cpu.icache.overall_accesses::total 4113 # number of overall (read+write) accesses 324system.cpu.icache.overall_avg_miss_latency::0 35793.697979 # average overall miss latency 325system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency 326system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency 327system.cpu.icache.overall_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency 328system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 329system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 330system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency 331system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency 332system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency 333system.cpu.icache.overall_hits::0 3272 # number of overall hits 334system.cpu.icache.overall_hits::1 0 # number of overall hits 335system.cpu.icache.overall_hits::total 3272 # number of overall hits 336system.cpu.icache.overall_miss_latency::0 30102500 # number of overall miss cycles 337system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles 338system.cpu.icache.overall_miss_latency::total 30102500 # number of overall miss cycles 339system.cpu.icache.overall_miss_rate::0 0.204474 # miss rate for overall accesses 340system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 341system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 342system.cpu.icache.overall_misses::0 841 # number of overall misses 343system.cpu.icache.overall_misses::1 0 # number of overall misses 344system.cpu.icache.overall_misses::total 841 # number of overall misses 345system.cpu.icache.overall_mshr_hits::0 222 # number of overall MSHR hits 346system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits 347system.cpu.icache.overall_mshr_hits::total 222 # number of overall MSHR hits 348system.cpu.icache.overall_mshr_miss_latency::0 21984500 # number of overall MSHR miss cycles 349system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles 350system.cpu.icache.overall_mshr_miss_latency::total 21984500 # number of overall MSHR miss cycles 351system.cpu.icache.overall_mshr_miss_rate::0 0.150498 # mshr miss rate for overall accesses 352system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 353system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 354system.cpu.icache.overall_mshr_misses::0 619 # number of overall MSHR misses 355system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses 356system.cpu.icache.overall_mshr_misses::total 619 # number of overall MSHR misses 357system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles 358system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles 359system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles 360system.cpu.icache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses 361system.cpu.icache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses 362system.cpu.icache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses 363system.cpu.icache.replacements::0 6 # number of replacements 364system.cpu.icache.replacements::1 0 # number of replacements 365system.cpu.icache.replacements::total 6 # number of replacements 366system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. 367system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions 368system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions 369system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions 370system.cpu.icache.tagsinuse 321.284131 # Cycle average of tags in use 371system.cpu.icache.total_refs 3272 # Total number of references to valid blocks. 372system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 373system.cpu.icache.writebacks::0 0 # number of writebacks 374system.cpu.icache.writebacks::1 0 # number of writebacks 375system.cpu.icache.writebacks::total 0 # number of writebacks 376system.cpu.idleCycles 5600 # Total number of cycles that the CPU has spent unscheduled due to idling 377system.cpu.iew.EXEC:branches::0 1573 # Number of branches executed 378system.cpu.iew.EXEC:branches::1 1587 # Number of branches executed 379system.cpu.iew.EXEC:branches::total 3160 # Number of branches executed 380system.cpu.iew.EXEC:nop::0 70 # number of nop insts executed 381system.cpu.iew.EXEC:nop::1 65 # number of nop insts executed 382system.cpu.iew.EXEC:nop::total 135 # number of nop insts executed 383system.cpu.iew.EXEC:rate 0.673940 # Inst execution rate 384system.cpu.iew.EXEC:refs::0 3132 # number of memory reference insts executed 385system.cpu.iew.EXEC:refs::1 3189 # number of memory reference insts executed 386system.cpu.iew.EXEC:refs::total 6321 # number of memory reference insts executed 387system.cpu.iew.EXEC:stores::0 1090 # Number of stores executed 388system.cpu.iew.EXEC:stores::1 1085 # Number of stores executed 389system.cpu.iew.EXEC:stores::total 2175 # Number of stores executed 390system.cpu.iew.EXEC:swp::0 0 # number of swp insts executed 391system.cpu.iew.EXEC:swp::1 0 # number of swp insts executed 392system.cpu.iew.EXEC:swp::total 0 # number of swp insts executed 393system.cpu.iew.WB:consumers::0 5984 # num instructions consuming a value 394system.cpu.iew.WB:consumers::1 5917 # num instructions consuming a value 395system.cpu.iew.WB:consumers::total 11901 # num instructions consuming a value 396system.cpu.iew.WB:count::0 9221 # cumulative count of insts written-back 397system.cpu.iew.WB:count::1 9205 # cumulative count of insts written-back 398system.cpu.iew.WB:count::total 18426 # cumulative count of insts written-back 399system.cpu.iew.WB:fanout::0 0.776404 # average fanout of values written-back 400system.cpu.iew.WB:fanout::1 0.776407 # average fanout of values written-back 401system.cpu.iew.WB:fanout::total 1.552811 # average fanout of values written-back 402system.cpu.iew.WB:penalized::0 0 # number of instrctions required to write to 'other' IQ 403system.cpu.iew.WB:penalized::1 0 # number of instrctions required to write to 'other' IQ 404system.cpu.iew.WB:penalized::total 0 # number of instrctions required to write to 'other' IQ 405system.cpu.iew.WB:penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ 406system.cpu.iew.WB:penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ 407system.cpu.iew.WB:penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ 408system.cpu.iew.WB:producers::0 4646 # num instructions producing a value 409system.cpu.iew.WB:producers::1 4594 # num instructions producing a value 410system.cpu.iew.WB:producers::total 9240 # num instructions producing a value 411system.cpu.iew.WB:rate::0 0.323498 # insts written-back per cycle 412system.cpu.iew.WB:rate::1 0.322937 # insts written-back per cycle 413system.cpu.iew.WB:rate::total 0.646436 # insts written-back per cycle 414system.cpu.iew.WB:sent::0 9324 # cumulative count of insts sent to commit 415system.cpu.iew.WB:sent::1 9340 # cumulative count of insts sent to commit 416system.cpu.iew.WB:sent::total 18664 # cumulative count of insts sent to commit 417system.cpu.iew.branchMispredicts 1342 # Number of branch mispredicts detected at execute 418system.cpu.iew.iewBlockCycles 1080 # Number of cycles IEW is blocking 419system.cpu.iew.iewDispLoadInsts 4951 # Number of dispatched load instructions 420system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions 421system.cpu.iew.iewDispSquashedInsts 727 # Number of squashed instructions skipped by dispatch 422system.cpu.iew.iewDispStoreInsts 2585 # Number of dispatched store instructions 423system.cpu.iew.iewDispatchedInsts 23775 # Number of instructions dispatched to IQ 424system.cpu.iew.iewExecLoadInsts::0 2042 # Number of load instructions executed 425system.cpu.iew.iewExecLoadInsts::1 2104 # Number of load instructions executed 426system.cpu.iew.iewExecLoadInsts::total 4146 # Number of load instructions executed 427system.cpu.iew.iewExecSquashedInsts 1180 # Number of squashed instructions skipped in execute 428system.cpu.iew.iewExecutedInsts 19210 # Number of executed instructions 429system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall 430system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 431system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 432system.cpu.iew.iewSquashCycles 2128 # Number of cycles IEW is squashing 433system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking 434system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 435system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 436system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores 437system.cpu.iew.lsq.thread.0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed 438system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 439system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 440system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations 441system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled 442system.cpu.iew.lsq.thread.0.squashedLoads 1246 # Number of loads squashed 443system.cpu.iew.lsq.thread.0.squashedStores 417 # Number of stores squashed 444system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 445system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 446system.cpu.iew.lsq.thread.1.forwLoads 72 # Number of loads that had data forwarded from stores 447system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed 448system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address 449system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 450system.cpu.iew.lsq.thread.1.memOrderViolation 68 # Number of memory ordering violations 451system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled 452system.cpu.iew.lsq.thread.1.squashedLoads 1335 # Number of loads squashed 453system.cpu.iew.lsq.thread.1.squashedStores 438 # Number of stores squashed 454system.cpu.iew.memOrderViolationEvents 136 # Number of memory order violations 455system.cpu.iew.predictedNotTakenIncorrect 1080 # Number of branches that were predicted not taken incorrectly 456system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly 457system.cpu.ipc::0 0.224039 # IPC: Instructions Per Cycle 458system.cpu.ipc::1 0.224074 # IPC: Instructions Per Cycle 459system.cpu.ipc_total 0.448113 # IPC: Total IPC of All Threads 460system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% # Type of FU issued 461system.cpu.iq.ISSUE:FU_type_0::IntAlu 6830 67.10% # Type of FU issued 462system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% # Type of FU issued 463system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued 464system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% # Type of FU issued 465system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued 466system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued 467system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued 468system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued 469system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued 470system.cpu.iq.ISSUE:FU_type_0::MemRead 2173 21.35% # Type of FU issued 471system.cpu.iq.ISSUE:FU_type_0::MemWrite 1171 11.50% # Type of FU issued 472system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued 473system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued 474system.cpu.iq.ISSUE:FU_type_0::total 10179 # Type of FU issued 475system.cpu.iq.ISSUE:FU_type_1::No_OpClass 2 0.02% # Type of FU issued 476system.cpu.iq.ISSUE:FU_type_1::IntAlu 6842 67.01% # Type of FU issued 477system.cpu.iq.ISSUE:FU_type_1::IntMult 1 0.01% # Type of FU issued 478system.cpu.iq.ISSUE:FU_type_1::IntDiv 0 0.00% # Type of FU issued 479system.cpu.iq.ISSUE:FU_type_1::FloatAdd 2 0.02% # Type of FU issued 480system.cpu.iq.ISSUE:FU_type_1::FloatCmp 0 0.00% # Type of FU issued 481system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% # Type of FU issued 482system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% # Type of FU issued 483system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% # Type of FU issued 484system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% # Type of FU issued 485system.cpu.iq.ISSUE:FU_type_1::MemRead 2230 21.84% # Type of FU issued 486system.cpu.iq.ISSUE:FU_type_1::MemWrite 1134 11.11% # Type of FU issued 487system.cpu.iq.ISSUE:FU_type_1::IprAccess 0 0.00% # Type of FU issued 488system.cpu.iq.ISSUE:FU_type_1::InstPrefetch 0 0.00% # Type of FU issued 489system.cpu.iq.ISSUE:FU_type_1::total 10211 # Type of FU issued 490system.cpu.iq.ISSUE:FU_type::No_OpClass 4 0.02% # Type of FU issued 491system.cpu.iq.ISSUE:FU_type::IntAlu 13672 67.05% # Type of FU issued 492system.cpu.iq.ISSUE:FU_type::IntMult 2 0.01% # Type of FU issued 493system.cpu.iq.ISSUE:FU_type::IntDiv 0 0.00% # Type of FU issued 494system.cpu.iq.ISSUE:FU_type::FloatAdd 4 0.02% # Type of FU issued 495system.cpu.iq.ISSUE:FU_type::FloatCmp 0 0.00% # Type of FU issued 496system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% # Type of FU issued 497system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% # Type of FU issued 498system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% # Type of FU issued 499system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% # Type of FU issued 500system.cpu.iq.ISSUE:FU_type::MemRead 4403 21.59% # Type of FU issued 501system.cpu.iq.ISSUE:FU_type::MemWrite 2305 11.30% # Type of FU issued 502system.cpu.iq.ISSUE:FU_type::IprAccess 0 0.00% # Type of FU issued 503system.cpu.iq.ISSUE:FU_type::InstPrefetch 0 0.00% # Type of FU issued 504system.cpu.iq.ISSUE:FU_type::total 20390 # Type of FU issued 505system.cpu.iq.ISSUE:fu_busy_cnt::0 87 # FU busy when requested 506system.cpu.iq.ISSUE:fu_busy_cnt::1 85 # FU busy when requested 507system.cpu.iq.ISSUE:fu_busy_cnt::total 172 # FU busy when requested 508system.cpu.iq.ISSUE:fu_busy_rate::0 0.004267 # FU busy rate (busy events/executed inst) 509system.cpu.iq.ISSUE:fu_busy_rate::1 0.004169 # FU busy rate (busy events/executed inst) 510system.cpu.iq.ISSUE:fu_busy_rate::total 0.008436 # FU busy rate (busy events/executed inst) 511system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available 512system.cpu.iq.ISSUE:fu_full::IntAlu 13 7.56% # attempts to use FU when none available 513system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available 514system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available 515system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available 516system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available 517system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available 518system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available 519system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available 520system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available 521system.cpu.iq.ISSUE:fu_full::MemRead 96 55.81% # attempts to use FU when none available 522system.cpu.iq.ISSUE:fu_full::MemWrite 63 36.63% # attempts to use FU when none available 523system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available 524system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available 525system.cpu.iq.ISSUE:issued_per_cycle::samples 22904 # Number of insts issued each cycle 526system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle 527system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle 528system.cpu.iq.ISSUE:issued_per_cycle::0-1 14156 61.81% # Number of insts issued each cycle 529system.cpu.iq.ISSUE:issued_per_cycle::1-2 3289 14.36% # Number of insts issued each cycle 530system.cpu.iq.ISSUE:issued_per_cycle::2-3 2351 10.26% # Number of insts issued each cycle 531system.cpu.iq.ISSUE:issued_per_cycle::3-4 1373 5.99% # Number of insts issued each cycle 532system.cpu.iq.ISSUE:issued_per_cycle::4-5 854 3.73% # Number of insts issued each cycle 533system.cpu.iq.ISSUE:issued_per_cycle::5-6 535 2.34% # Number of insts issued each cycle 534system.cpu.iq.ISSUE:issued_per_cycle::6-7 261 1.14% # Number of insts issued each cycle 535system.cpu.iq.ISSUE:issued_per_cycle::7-8 57 0.25% # Number of insts issued each cycle 536system.cpu.iq.ISSUE:issued_per_cycle::8 28 0.12% # Number of insts issued each cycle 537system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle 538system.cpu.iq.ISSUE:issued_per_cycle::total 22904 # Number of insts issued each cycle 539system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle 540system.cpu.iq.ISSUE:issued_per_cycle::mean 0.890238 # Number of insts issued each cycle 541system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.446450 # Number of insts issued each cycle 542system.cpu.iq.ISSUE:rate 0.715338 # Inst issue rate 543system.cpu.iq.iqInstsAdded 23596 # Number of instructions added to the IQ (excludes non-spec) 544system.cpu.iq.iqInstsIssued 20390 # Number of instructions issued 545system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ 546system.cpu.iq.iqSquashedInstsExamined 9662 # Number of squashed instructions iterated over during squash; mainly for profiling 547system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued 548system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed 549system.cpu.iq.iqSquashedOperandsExamined 5422 # Number of squashed operands that are examined and possibly removed from graph 550system.cpu.itb.data_accesses 0 # DTB accesses 551system.cpu.itb.data_acv 0 # DTB access violations 552system.cpu.itb.data_hits 0 # DTB hits 553system.cpu.itb.data_misses 0 # DTB misses 554system.cpu.itb.fetch_accesses 4162 # ITB accesses 555system.cpu.itb.fetch_acv 0 # ITB acv 556system.cpu.itb.fetch_hits 4113 # ITB hits 557system.cpu.itb.fetch_misses 49 # ITB misses 558system.cpu.itb.read_accesses 0 # DTB read accesses 559system.cpu.itb.read_acv 0 # DTB read access violations 560system.cpu.itb.read_hits 0 # DTB read hits 561system.cpu.itb.read_misses 0 # DTB read misses 562system.cpu.itb.write_accesses 0 # DTB write accesses 563system.cpu.itb.write_acv 0 # DTB write access violations 564system.cpu.itb.write_hits 0 # DTB write hits 565system.cpu.itb.write_misses 0 # DTB write misses 566system.cpu.l2cache.ReadExReq_accesses::0 146 # number of ReadExReq accesses(hits+misses) 567system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) 568system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34643.835616 # average ReadExReq miss latency 569system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31589.041096 # average ReadExReq mshr miss latency 570system.cpu.l2cache.ReadExReq_miss_latency::0 5058000 # number of ReadExReq miss cycles 571system.cpu.l2cache.ReadExReq_miss_latency::total 5058000 # number of ReadExReq miss cycles 572system.cpu.l2cache.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses 573system.cpu.l2cache.ReadExReq_misses::0 146 # number of ReadExReq misses 574system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses 575system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4612000 # number of ReadExReq MSHR miss cycles 576system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4612000 # number of ReadExReq MSHR miss cycles 577system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses 578system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses 579system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses 580system.cpu.l2cache.ReadReq_accesses::0 825 # number of ReadReq accesses(hits+misses) 581system.cpu.l2cache.ReadReq_accesses::total 825 # number of ReadReq accesses(hits+misses) 582system.cpu.l2cache.ReadReq_avg_miss_latency::0 34555.285541 # average ReadReq miss latency 583system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31414.337789 # average ReadReq mshr miss latency 584system.cpu.l2cache.ReadReq_hits::0 2 # number of ReadReq hits 585system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 586system.cpu.l2cache.ReadReq_miss_latency::0 28439000 # number of ReadReq miss cycles 587system.cpu.l2cache.ReadReq_miss_latency::total 28439000 # number of ReadReq miss cycles 588system.cpu.l2cache.ReadReq_miss_rate::0 0.997576 # miss rate for ReadReq accesses 589system.cpu.l2cache.ReadReq_misses::0 823 # number of ReadReq misses 590system.cpu.l2cache.ReadReq_misses::total 823 # number of ReadReq misses 591system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25854000 # number of ReadReq MSHR miss cycles 592system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25854000 # number of ReadReq MSHR miss cycles 593system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997576 # mshr miss rate for ReadReq accesses 594system.cpu.l2cache.ReadReq_mshr_misses::0 823 # number of ReadReq MSHR misses 595system.cpu.l2cache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses 596system.cpu.l2cache.UpgradeReq_accesses::0 28 # number of UpgradeReq accesses(hits+misses) 597system.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses) 598system.cpu.l2cache.UpgradeReq_avg_miss_latency::0 34482.142857 # average UpgradeReq miss latency 599system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::0 31357.142857 # average UpgradeReq mshr miss latency 600system.cpu.l2cache.UpgradeReq_miss_latency::0 965500 # number of UpgradeReq miss cycles 601system.cpu.l2cache.UpgradeReq_miss_latency::total 965500 # number of UpgradeReq miss cycles 602system.cpu.l2cache.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses 603system.cpu.l2cache.UpgradeReq_misses::0 28 # number of UpgradeReq misses 604system.cpu.l2cache.UpgradeReq_misses::total 28 # number of UpgradeReq misses 605system.cpu.l2cache.UpgradeReq_mshr_miss_latency::0 878000 # number of UpgradeReq MSHR miss cycles 606system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 878000 # number of UpgradeReq MSHR miss cycles 607system.cpu.l2cache.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses 608system.cpu.l2cache.UpgradeReq_mshr_misses::0 28 # number of UpgradeReq MSHR misses 609system.cpu.l2cache.UpgradeReq_mshr_misses::total 28 # number of UpgradeReq MSHR misses 610system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6750 # average number of cycles each access was blocked 611system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 612system.cpu.l2cache.avg_refs 0.002516 # Average number of references to valid blocks. 613system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked 614system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 615system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked 616system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 617system.cpu.l2cache.cache_copies 0 # number of cache copies performed 618system.cpu.l2cache.demand_accesses::0 971 # number of demand (read+write) accesses 619system.cpu.l2cache.demand_accesses::1 0 # number of demand (read+write) accesses 620system.cpu.l2cache.demand_accesses::total 971 # number of demand (read+write) accesses 621system.cpu.l2cache.demand_avg_miss_latency::0 34568.627451 # average overall miss latency 622system.cpu.l2cache.demand_avg_miss_latency::1 no_value # average overall miss latency 623system.cpu.l2cache.demand_avg_miss_latency::total no_value # average overall miss latency 624system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency 625system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 626system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 627system.cpu.l2cache.demand_hits::0 2 # number of demand (read+write) hits 628system.cpu.l2cache.demand_hits::1 0 # number of demand (read+write) hits 629system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 630system.cpu.l2cache.demand_miss_latency::0 33497000 # number of demand (read+write) miss cycles 631system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles 632system.cpu.l2cache.demand_miss_latency::total 33497000 # number of demand (read+write) miss cycles 633system.cpu.l2cache.demand_miss_rate::0 0.997940 # miss rate for demand accesses 634system.cpu.l2cache.demand_miss_rate::1 no_value # miss rate for demand accesses 635system.cpu.l2cache.demand_miss_rate::total no_value # miss rate for demand accesses 636system.cpu.l2cache.demand_misses::0 969 # number of demand (read+write) misses 637system.cpu.l2cache.demand_misses::1 0 # number of demand (read+write) misses 638system.cpu.l2cache.demand_misses::total 969 # number of demand (read+write) misses 639system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits 640system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits 641system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits 642system.cpu.l2cache.demand_mshr_miss_latency::0 30466000 # number of demand (read+write) MSHR miss cycles 643system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles 644system.cpu.l2cache.demand_mshr_miss_latency::total 30466000 # number of demand (read+write) MSHR miss cycles 645system.cpu.l2cache.demand_mshr_miss_rate::0 0.997940 # mshr miss rate for demand accesses 646system.cpu.l2cache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 647system.cpu.l2cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 648system.cpu.l2cache.demand_mshr_misses::0 969 # number of demand (read+write) MSHR misses 649system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses 650system.cpu.l2cache.demand_mshr_misses::total 969 # number of demand (read+write) MSHR misses 651system.cpu.l2cache.fast_writes 0 # number of fast writes performed 652system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated 653system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated 654system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated 655system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 656system.cpu.l2cache.overall_accesses::0 971 # number of overall (read+write) accesses 657system.cpu.l2cache.overall_accesses::1 0 # number of overall (read+write) accesses 658system.cpu.l2cache.overall_accesses::total 971 # number of overall (read+write) accesses 659system.cpu.l2cache.overall_avg_miss_latency::0 34568.627451 # average overall miss latency 660system.cpu.l2cache.overall_avg_miss_latency::1 no_value # average overall miss latency 661system.cpu.l2cache.overall_avg_miss_latency::total no_value # average overall miss latency 662system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency 663system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency 664system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency 665system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency 666system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency 667system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency 668system.cpu.l2cache.overall_hits::0 2 # number of overall hits 669system.cpu.l2cache.overall_hits::1 0 # number of overall hits 670system.cpu.l2cache.overall_hits::total 2 # number of overall hits 671system.cpu.l2cache.overall_miss_latency::0 33497000 # number of overall miss cycles 672system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles 673system.cpu.l2cache.overall_miss_latency::total 33497000 # number of overall miss cycles 674system.cpu.l2cache.overall_miss_rate::0 0.997940 # miss rate for overall accesses 675system.cpu.l2cache.overall_miss_rate::1 no_value # miss rate for overall accesses 676system.cpu.l2cache.overall_miss_rate::total no_value # miss rate for overall accesses 677system.cpu.l2cache.overall_misses::0 969 # number of overall misses 678system.cpu.l2cache.overall_misses::1 0 # number of overall misses 679system.cpu.l2cache.overall_misses::total 969 # number of overall misses 680system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits 681system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits 682system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits 683system.cpu.l2cache.overall_mshr_miss_latency::0 30466000 # number of overall MSHR miss cycles 684system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles 685system.cpu.l2cache.overall_mshr_miss_latency::total 30466000 # number of overall MSHR miss cycles 686system.cpu.l2cache.overall_mshr_miss_rate::0 0.997940 # mshr miss rate for overall accesses 687system.cpu.l2cache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 688system.cpu.l2cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 689system.cpu.l2cache.overall_mshr_misses::0 969 # number of overall MSHR misses 690system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses 691system.cpu.l2cache.overall_mshr_misses::total 969 # number of overall MSHR misses 692system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles 693system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles 694system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles 695system.cpu.l2cache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses 696system.cpu.l2cache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses 697system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses 698system.cpu.l2cache.replacements::0 0 # number of replacements 699system.cpu.l2cache.replacements::1 0 # number of replacements 700system.cpu.l2cache.replacements::total 0 # number of replacements 701system.cpu.l2cache.sampled_refs 795 # Sample count of references to valid blocks. 702system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions 703system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions 704system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions 705system.cpu.l2cache.tagsinuse 435.713880 # Cycle average of tags in use 706system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 707system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 708system.cpu.l2cache.writebacks::0 0 # number of writebacks 709system.cpu.l2cache.writebacks::1 0 # number of writebacks 710system.cpu.l2cache.writebacks::total 0 # number of writebacks 711system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. 712system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. 713system.cpu.memDep0.insertedLoads 2431 # Number of loads inserted to the mem dependence unit. 714system.cpu.memDep0.insertedStores 1282 # Number of stores inserted to the mem dependence unit. 715system.cpu.memDep1.conflictingLoads 58 # Number of conflicting loads. 716system.cpu.memDep1.conflictingStores 32 # Number of conflicting stores. 717system.cpu.memDep1.insertedLoads 2520 # Number of loads inserted to the mem dependence unit. 718system.cpu.memDep1.insertedStores 1303 # Number of stores inserted to the mem dependence unit. 719system.cpu.numCycles 28504 # number of cpu cycles simulated 720system.cpu.rename.RENAME:BlockCycles 2835 # Number of cycles rename is blocking 721system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed 722system.cpu.rename.RENAME:IdleCycles 33866 # Number of cycles rename is idle 723system.cpu.rename.RENAME:LSQFullEvents 1399 # Number of times rename has blocked due to LSQ full 724system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full 725system.cpu.rename.RENAME:RenameLookups 32685 # Number of register rename lookups that rename has made 726system.cpu.rename.RENAME:RenamedInsts 26128 # Number of instructions processed by rename 727system.cpu.rename.RENAME:RenamedOperands 19538 # Number of destination operands rename has renamed 728system.cpu.rename.RENAME:RunCycles 4546 # Number of cycles rename is running 729system.cpu.rename.RENAME:SquashCycles 2128 # Number of cycles rename is squashing 730system.cpu.rename.RENAME:UnblockCycles 1422 # Number of cycles rename is unblocking 731system.cpu.rename.RENAME:UndoneMaps 10372 # Number of HB maps that are undone due to squashing 732system.cpu.rename.RENAME:serializeStallCycles 850 # count of cycles rename stalled for serializing inst 733system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed 734system.cpu.rename.RENAME:skidInsts 3399 # count of insts added to the skid buffer 735system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed 736system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself 737system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls 738system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls 739 740---------- End Simulation Statistics ---------- 741