stats.txt revision 3147
1 2---------- Begin Simulation Statistics ---------- 3global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 4global.BPredUnit.BTBHits 638 # Number of BTB hits 5global.BPredUnit.BTBLookups 3591 # Number of BTB lookups 6global.BPredUnit.RASInCorrect 96 # Number of incorrect RAS predictions. 7global.BPredUnit.condIncorrect 1078 # Number of conditional branches incorrect 8global.BPredUnit.condPredicted 2445 # Number of conditional branches predicted 9global.BPredUnit.lookups 4165 # Number of BP lookups 10global.BPredUnit.usedRAS 550 # Number of times the RAS was used to get a target. 11host_inst_rate 26570 # Simulator instruction rate (inst/s) 12host_mem_usage 161280 # Number of bytes of host memory used 13host_seconds 0.42 # Real time elapsed on the host 14host_tick_rate 19898 # Simulator tick rate (ticks/s) 15memdepunit.memDep.conflictingLoads 41 # Number of conflicting loads. 16memdepunit.memDep.conflictingLoads 39 # Number of conflicting loads. 17memdepunit.memDep.conflictingStores 194 # Number of conflicting stores. 18memdepunit.memDep.conflictingStores 198 # Number of conflicting stores. 19memdepunit.memDep.insertedLoads 1873 # Number of loads inserted to the mem dependence unit. 20memdepunit.memDep.insertedLoads 1836 # Number of loads inserted to the mem dependence unit. 21memdepunit.memDep.insertedStores 1110 # Number of stores inserted to the mem dependence unit. 22memdepunit.memDep.insertedStores 1108 # Number of stores inserted to the mem dependence unit. 23sim_freq 1000000000000 # Frequency of simulated ticks 24sim_insts 11247 # Number of instructions simulated 25sim_seconds 0.000000 # Number of seconds simulated 26sim_ticks 8429 # Number of ticks simulated 27system.cpu.commit.COM:branches 1724 # Number of branches committed 28system.cpu.commit.COM:branches_0 862 # Number of branches committed 29system.cpu.commit.COM:branches_1 862 # Number of branches committed 30system.cpu.commit.COM:bw_lim_events 125 # number cycles where commit BW limit reached 31system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits 32system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits 33system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits 34system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle 35system.cpu.commit.COM:committed_per_cycle.samples 8381 36system.cpu.commit.COM:committed_per_cycle.min_value 0 37 0 3942 4703.50% 38 1 1903 2270.61% 39 2 930 1109.65% 40 3 517 616.87% 41 4 373 445.05% 42 5 236 281.59% 43 6 190 226.70% 44 7 165 196.87% 45 8 125 149.15% 46system.cpu.commit.COM:committed_per_cycle.max_value 8 47system.cpu.commit.COM:committed_per_cycle.end_dist 48 49system.cpu.commit.COM:count 11281 # Number of instructions committed 50system.cpu.commit.COM:count_0 5640 # Number of instructions committed 51system.cpu.commit.COM:count_1 5641 # Number of instructions committed 52system.cpu.commit.COM:loads 1958 # Number of loads committed 53system.cpu.commit.COM:loads_0 979 # Number of loads committed 54system.cpu.commit.COM:loads_1 979 # Number of loads committed 55system.cpu.commit.COM:membars 0 # Number of memory barriers committed 56system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed 57system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed 58system.cpu.commit.COM:refs 3582 # Number of memory references committed 59system.cpu.commit.COM:refs_0 1791 # Number of memory references committed 60system.cpu.commit.COM:refs_1 1791 # Number of memory references committed 61system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed 62system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed 63system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed 64system.cpu.commit.branchMispredicts 829 # The number of times a branch was mispredicted 65system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions 66system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards 67system.cpu.commit.commitSquashedInsts 7542 # The number of squashed insts skipped by commit 68system.cpu.committedInsts_0 5623 # Number of Instructions Simulated 69system.cpu.committedInsts_1 5624 # Number of Instructions Simulated 70system.cpu.committedInsts_total 11247 # Number of Instructions Simulated 71system.cpu.cpi_0 1.499022 # CPI: Cycles Per Instruction 72system.cpu.cpi_1 1.498755 # CPI: Cycles Per Instruction 73system.cpu.cpi_total 0.749444 # CPI: Total CPI of All Threads 74system.cpu.dcache.ReadReq_accesses 2921 # number of ReadReq accesses(hits+misses) 75system.cpu.dcache.ReadReq_accesses_0 1470 # number of ReadReq accesses(hits+misses) 76system.cpu.dcache.ReadReq_accesses_1 1451 # number of ReadReq accesses(hits+misses) 77system.cpu.dcache.ReadReq_avg_miss_latency 3.100000 # average ReadReq miss latency 78system.cpu.dcache.ReadReq_avg_miss_latency_0 3.162393 # average ReadReq miss latency 79system.cpu.dcache.ReadReq_avg_miss_latency_1 3.035398 # average ReadReq miss latency 80system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.251282 # average ReadReq mshr miss latency 81system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 2.323232 # average ReadReq mshr miss latency 82system.cpu.dcache.ReadReq_avg_mshr_miss_latency_1 2.177083 # average ReadReq mshr miss latency 83system.cpu.dcache.ReadReq_hits 2691 # number of ReadReq hits 84system.cpu.dcache.ReadReq_hits_0 1353 # number of ReadReq hits 85system.cpu.dcache.ReadReq_hits_1 1338 # number of ReadReq hits 86system.cpu.dcache.ReadReq_miss_latency 713 # number of ReadReq miss cycles 87system.cpu.dcache.ReadReq_miss_latency_0 370 # number of ReadReq miss cycles 88system.cpu.dcache.ReadReq_miss_latency_1 343 # number of ReadReq miss cycles 89system.cpu.dcache.ReadReq_miss_rate 0.078740 # miss rate for ReadReq accesses 90system.cpu.dcache.ReadReq_miss_rate_0 0.079592 # miss rate for ReadReq accesses 91system.cpu.dcache.ReadReq_miss_rate_1 0.077877 # miss rate for ReadReq accesses 92system.cpu.dcache.ReadReq_misses 230 # number of ReadReq misses 93system.cpu.dcache.ReadReq_misses_0 117 # number of ReadReq misses 94system.cpu.dcache.ReadReq_misses_1 113 # number of ReadReq misses 95system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits 96system.cpu.dcache.ReadReq_mshr_hits_0 18 # number of ReadReq MSHR hits 97system.cpu.dcache.ReadReq_mshr_hits_1 17 # number of ReadReq MSHR hits 98system.cpu.dcache.ReadReq_mshr_miss_latency 439 # number of ReadReq MSHR miss cycles 99system.cpu.dcache.ReadReq_mshr_miss_latency_0 230 # number of ReadReq MSHR miss cycles 100system.cpu.dcache.ReadReq_mshr_miss_latency_1 209 # number of ReadReq MSHR miss cycles 101system.cpu.dcache.ReadReq_mshr_miss_rate 0.066758 # mshr miss rate for ReadReq accesses 102system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.067347 # mshr miss rate for ReadReq accesses 103system.cpu.dcache.ReadReq_mshr_miss_rate_1 0.066161 # mshr miss rate for ReadReq accesses 104system.cpu.dcache.ReadReq_mshr_misses 195 # number of ReadReq MSHR misses 105system.cpu.dcache.ReadReq_mshr_misses_0 99 # number of ReadReq MSHR misses 106system.cpu.dcache.ReadReq_mshr_misses_1 96 # number of ReadReq MSHR misses 107system.cpu.dcache.WriteReq_accesses 1642 # number of WriteReq accesses(hits+misses) 108system.cpu.dcache.WriteReq_accesses_0 830 # number of WriteReq accesses(hits+misses) 109system.cpu.dcache.WriteReq_accesses_1 812 # number of WriteReq accesses(hits+misses) 110system.cpu.dcache.WriteReq_avg_miss_latency 2.649842 # average WriteReq miss latency 111system.cpu.dcache.WriteReq_avg_miss_latency_0 2.533333 # average WriteReq miss latency 112system.cpu.dcache.WriteReq_avg_miss_latency_1 2.776316 # average WriteReq miss latency 113system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.076389 # average WriteReq mshr miss latency 114system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 2.069444 # average WriteReq mshr miss latency 115system.cpu.dcache.WriteReq_avg_mshr_miss_latency_1 2.083333 # average WriteReq mshr miss latency 116system.cpu.dcache.WriteReq_hits 1325 # number of WriteReq hits 117system.cpu.dcache.WriteReq_hits_0 665 # number of WriteReq hits 118system.cpu.dcache.WriteReq_hits_1 660 # number of WriteReq hits 119system.cpu.dcache.WriteReq_miss_latency 840 # number of WriteReq miss cycles 120system.cpu.dcache.WriteReq_miss_latency_0 418 # number of WriteReq miss cycles 121system.cpu.dcache.WriteReq_miss_latency_1 422 # number of WriteReq miss cycles 122system.cpu.dcache.WriteReq_miss_rate 0.193057 # miss rate for WriteReq accesses 123system.cpu.dcache.WriteReq_miss_rate_0 0.198795 # miss rate for WriteReq accesses 124system.cpu.dcache.WriteReq_miss_rate_1 0.187192 # miss rate for WriteReq accesses 125system.cpu.dcache.WriteReq_misses 317 # number of WriteReq misses 126system.cpu.dcache.WriteReq_misses_0 165 # number of WriteReq misses 127system.cpu.dcache.WriteReq_misses_1 152 # number of WriteReq misses 128system.cpu.dcache.WriteReq_mshr_hits 159 # number of WriteReq MSHR hits 129system.cpu.dcache.WriteReq_mshr_hits_0 79 # number of WriteReq MSHR hits 130system.cpu.dcache.WriteReq_mshr_hits_1 80 # number of WriteReq MSHR hits 131system.cpu.dcache.WriteReq_mshr_miss_latency 299 # number of WriteReq MSHR miss cycles 132system.cpu.dcache.WriteReq_mshr_miss_latency_0 149 # number of WriteReq MSHR miss cycles 133system.cpu.dcache.WriteReq_mshr_miss_latency_1 150 # number of WriteReq MSHR miss cycles 134system.cpu.dcache.WriteReq_mshr_miss_rate 0.087698 # mshr miss rate for WriteReq accesses 135system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.086747 # mshr miss rate for WriteReq accesses 136system.cpu.dcache.WriteReq_mshr_miss_rate_1 0.088670 # mshr miss rate for WriteReq accesses 137system.cpu.dcache.WriteReq_mshr_misses 144 # number of WriteReq MSHR misses 138system.cpu.dcache.WriteReq_mshr_misses_0 72 # number of WriteReq MSHR misses 139system.cpu.dcache.WriteReq_mshr_misses_1 72 # number of WriteReq MSHR misses 140system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 141system.cpu.dcache.avg_blocked_cycles_no_targets 1 # average number of cycles each access was blocked 142system.cpu.dcache.avg_refs 11.376771 # Average number of references to valid blocks. 143system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked 144system.cpu.dcache.blocked_no_targets 7 # number of cycles access was blocked 145system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 146system.cpu.dcache.blocked_cycles_no_targets 7 # number of cycles access was blocked 147system.cpu.dcache.cache_copies 0 # number of cache copies performed 148system.cpu.dcache.demand_accesses 4563 # number of demand (read+write) accesses 149system.cpu.dcache.demand_accesses_0 2300 # number of demand (read+write) accesses 150system.cpu.dcache.demand_accesses_1 2263 # number of demand (read+write) accesses 151system.cpu.dcache.demand_avg_miss_latency 2.839122 # average overall miss latency 152system.cpu.dcache.demand_avg_miss_latency_0 2.794326 # average overall miss latency 153system.cpu.dcache.demand_avg_miss_latency_1 2.886792 # average overall miss latency 154system.cpu.dcache.demand_avg_mshr_miss_latency 2.176991 # average overall mshr miss latency 155system.cpu.dcache.demand_avg_mshr_miss_latency_0 2.216374 # average overall mshr miss latency 156system.cpu.dcache.demand_avg_mshr_miss_latency_1 2.136905 # average overall mshr miss latency 157system.cpu.dcache.demand_hits 4016 # number of demand (read+write) hits 158system.cpu.dcache.demand_hits_0 2018 # number of demand (read+write) hits 159system.cpu.dcache.demand_hits_1 1998 # number of demand (read+write) hits 160system.cpu.dcache.demand_miss_latency 1553 # number of demand (read+write) miss cycles 161system.cpu.dcache.demand_miss_latency_0 788 # number of demand (read+write) miss cycles 162system.cpu.dcache.demand_miss_latency_1 765 # number of demand (read+write) miss cycles 163system.cpu.dcache.demand_miss_rate 0.119877 # miss rate for demand accesses 164system.cpu.dcache.demand_miss_rate_0 0.122609 # miss rate for demand accesses 165system.cpu.dcache.demand_miss_rate_1 0.117101 # miss rate for demand accesses 166system.cpu.dcache.demand_misses 547 # number of demand (read+write) misses 167system.cpu.dcache.demand_misses_0 282 # number of demand (read+write) misses 168system.cpu.dcache.demand_misses_1 265 # number of demand (read+write) misses 169system.cpu.dcache.demand_mshr_hits 194 # number of demand (read+write) MSHR hits 170system.cpu.dcache.demand_mshr_hits_0 97 # number of demand (read+write) MSHR hits 171system.cpu.dcache.demand_mshr_hits_1 97 # number of demand (read+write) MSHR hits 172system.cpu.dcache.demand_mshr_miss_latency 738 # number of demand (read+write) MSHR miss cycles 173system.cpu.dcache.demand_mshr_miss_latency_0 379 # number of demand (read+write) MSHR miss cycles 174system.cpu.dcache.demand_mshr_miss_latency_1 359 # number of demand (read+write) MSHR miss cycles 175system.cpu.dcache.demand_mshr_miss_rate 0.074293 # mshr miss rate for demand accesses 176system.cpu.dcache.demand_mshr_miss_rate_0 0.074348 # mshr miss rate for demand accesses 177system.cpu.dcache.demand_mshr_miss_rate_1 0.074238 # mshr miss rate for demand accesses 178system.cpu.dcache.demand_mshr_misses 339 # number of demand (read+write) MSHR misses 179system.cpu.dcache.demand_mshr_misses_0 171 # number of demand (read+write) MSHR misses 180system.cpu.dcache.demand_mshr_misses_1 168 # number of demand (read+write) MSHR misses 181system.cpu.dcache.fast_writes 0 # number of fast writes performed 182system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 183system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated 184system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated 185system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 186system.cpu.dcache.overall_accesses 4563 # number of overall (read+write) accesses 187system.cpu.dcache.overall_accesses_0 2300 # number of overall (read+write) accesses 188system.cpu.dcache.overall_accesses_1 2263 # number of overall (read+write) accesses 189system.cpu.dcache.overall_avg_miss_latency 2.839122 # average overall miss latency 190system.cpu.dcache.overall_avg_miss_latency_0 2.794326 # average overall miss latency 191system.cpu.dcache.overall_avg_miss_latency_1 2.886792 # average overall miss latency 192system.cpu.dcache.overall_avg_mshr_miss_latency 2.176991 # average overall mshr miss latency 193system.cpu.dcache.overall_avg_mshr_miss_latency_0 2.216374 # average overall mshr miss latency 194system.cpu.dcache.overall_avg_mshr_miss_latency_1 2.136905 # average overall mshr miss latency 195system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 196system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency 197system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency 198system.cpu.dcache.overall_hits 4016 # number of overall hits 199system.cpu.dcache.overall_hits_0 2018 # number of overall hits 200system.cpu.dcache.overall_hits_1 1998 # number of overall hits 201system.cpu.dcache.overall_miss_latency 1553 # number of overall miss cycles 202system.cpu.dcache.overall_miss_latency_0 788 # number of overall miss cycles 203system.cpu.dcache.overall_miss_latency_1 765 # number of overall miss cycles 204system.cpu.dcache.overall_miss_rate 0.119877 # miss rate for overall accesses 205system.cpu.dcache.overall_miss_rate_0 0.122609 # miss rate for overall accesses 206system.cpu.dcache.overall_miss_rate_1 0.117101 # miss rate for overall accesses 207system.cpu.dcache.overall_misses 547 # number of overall misses 208system.cpu.dcache.overall_misses_0 282 # number of overall misses 209system.cpu.dcache.overall_misses_1 265 # number of overall misses 210system.cpu.dcache.overall_mshr_hits 194 # number of overall MSHR hits 211system.cpu.dcache.overall_mshr_hits_0 97 # number of overall MSHR hits 212system.cpu.dcache.overall_mshr_hits_1 97 # number of overall MSHR hits 213system.cpu.dcache.overall_mshr_miss_latency 738 # number of overall MSHR miss cycles 214system.cpu.dcache.overall_mshr_miss_latency_0 379 # number of overall MSHR miss cycles 215system.cpu.dcache.overall_mshr_miss_latency_1 359 # number of overall MSHR miss cycles 216system.cpu.dcache.overall_mshr_miss_rate 0.074293 # mshr miss rate for overall accesses 217system.cpu.dcache.overall_mshr_miss_rate_0 0.074348 # mshr miss rate for overall accesses 218system.cpu.dcache.overall_mshr_miss_rate_1 0.074238 # mshr miss rate for overall accesses 219system.cpu.dcache.overall_mshr_misses 339 # number of overall MSHR misses 220system.cpu.dcache.overall_mshr_misses_0 171 # number of overall MSHR misses 221system.cpu.dcache.overall_mshr_misses_1 168 # number of overall MSHR misses 222system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 223system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles 224system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles 225system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 226system.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses 227system.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses 228system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 229system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 230system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 231system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 232system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 233system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 234system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 235system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 236system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 237system.cpu.dcache.replacements 0 # number of replacements 238system.cpu.dcache.replacements_0 0 # number of replacements 239system.cpu.dcache.replacements_1 0 # number of replacements 240system.cpu.dcache.sampled_refs 353 # Sample count of references to valid blocks. 241system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 242system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions 243system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions 244system.cpu.dcache.tagsinuse 236.409371 # Cycle average of tags in use 245system.cpu.dcache.total_refs 4016 # Total number of references to valid blocks. 246system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 247system.cpu.dcache.writebacks 0 # number of writebacks 248system.cpu.dcache.writebacks_0 0 # number of writebacks 249system.cpu.dcache.writebacks_1 0 # number of writebacks 250system.cpu.decode.DECODE:BlockedCycles 1676 # Number of cycles decode is blocked 251system.cpu.decode.DECODE:BranchMispred 270 # Number of times decode detected a branch misprediction 252system.cpu.decode.DECODE:BranchResolved 367 # Number of times decode resolved a branch 253system.cpu.decode.DECODE:DecodedInsts 22636 # Number of instructions handled by decode 254system.cpu.decode.DECODE:IdleCycles 9654 # Number of cycles decode is idle 255system.cpu.decode.DECODE:RunCycles 3745 # Number of cycles decode is running 256system.cpu.decode.DECODE:SquashCycles 1395 # Number of cycles decode is squashing 257system.cpu.decode.DECODE:SquashedInsts 246 # Number of squashed instructions handled by decode 258system.cpu.decode.DECODE:UnblockCycles 110 # Number of cycles decode is unblocking 259system.cpu.fetch.Branches 4165 # Number of branches that fetch encountered 260system.cpu.fetch.CacheLines 2863 # Number of cache lines fetched 261system.cpu.fetch.Cycles 6949 # Number of cycles fetch has run and was not squashing or blocked 262system.cpu.fetch.IcacheSquashes 197 # Number of outstanding Icache misses that were squashed 263system.cpu.fetch.Insts 25207 # Number of instructions fetch has processed 264system.cpu.fetch.SquashCycles 1140 # Number of cycles fetch has spent squashing 265system.cpu.fetch.branchRate 0.494069 # Number of branch fetches per cycle 266system.cpu.fetch.icacheStallCycles 2863 # Number of cycles fetch is stalled on an Icache miss 267system.cpu.fetch.predictedBranches 1188 # Number of branches that fetch has predicted taken 268system.cpu.fetch.rate 2.990154 # Number of inst fetches per cycle 269system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist.samples 8430 271system.cpu.fetch.rateDist.min_value 0 272 0 4345 5154.21% 273 1 273 323.84% 274 2 232 275.21% 275 3 245 290.63% 276 4 309 366.55% 277 5 277 328.59% 278 6 293 347.57% 279 7 292 346.38% 280 8 2164 2567.02% 281system.cpu.fetch.rateDist.max_value 8 282system.cpu.fetch.rateDist.end_dist 283 284system.cpu.icache.ReadReq_accesses 2863 # number of ReadReq accesses(hits+misses) 285system.cpu.icache.ReadReq_accesses_0 1463 # number of ReadReq accesses(hits+misses) 286system.cpu.icache.ReadReq_accesses_1 1400 # number of ReadReq accesses(hits+misses) 287system.cpu.icache.ReadReq_avg_miss_latency 2.982343 # average ReadReq miss latency 288system.cpu.icache.ReadReq_avg_miss_latency_0 2.974441 # average ReadReq miss latency 289system.cpu.icache.ReadReq_avg_miss_latency_1 2.990323 # average ReadReq miss latency 290system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.995153 # average ReadReq mshr miss latency 291system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 1.993548 # average ReadReq mshr miss latency 292system.cpu.icache.ReadReq_avg_mshr_miss_latency_1 1.996764 # average ReadReq mshr miss latency 293system.cpu.icache.ReadReq_hits 2240 # number of ReadReq hits 294system.cpu.icache.ReadReq_hits_0 1150 # number of ReadReq hits 295system.cpu.icache.ReadReq_hits_1 1090 # number of ReadReq hits 296system.cpu.icache.ReadReq_miss_latency 1858 # number of ReadReq miss cycles 297system.cpu.icache.ReadReq_miss_latency_0 931 # number of ReadReq miss cycles 298system.cpu.icache.ReadReq_miss_latency_1 927 # number of ReadReq miss cycles 299system.cpu.icache.ReadReq_miss_rate 0.217604 # miss rate for ReadReq accesses 300system.cpu.icache.ReadReq_miss_rate_0 0.213944 # miss rate for ReadReq accesses 301system.cpu.icache.ReadReq_miss_rate_1 0.221429 # miss rate for ReadReq accesses 302system.cpu.icache.ReadReq_misses 623 # number of ReadReq misses 303system.cpu.icache.ReadReq_misses_0 313 # number of ReadReq misses 304system.cpu.icache.ReadReq_misses_1 310 # number of ReadReq misses 305system.cpu.icache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits 306system.cpu.icache.ReadReq_mshr_hits_0 3 # number of ReadReq MSHR hits 307system.cpu.icache.ReadReq_mshr_hits_1 1 # number of ReadReq MSHR hits 308system.cpu.icache.ReadReq_mshr_miss_latency 1235 # number of ReadReq MSHR miss cycles 309system.cpu.icache.ReadReq_mshr_miss_latency_0 618 # number of ReadReq MSHR miss cycles 310system.cpu.icache.ReadReq_mshr_miss_latency_1 617 # number of ReadReq MSHR miss cycles 311system.cpu.icache.ReadReq_mshr_miss_rate 0.216207 # mshr miss rate for ReadReq accesses 312system.cpu.icache.ReadReq_mshr_miss_rate_0 0.211893 # mshr miss rate for ReadReq accesses 313system.cpu.icache.ReadReq_mshr_miss_rate_1 0.220714 # mshr miss rate for ReadReq accesses 314system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses 315system.cpu.icache.ReadReq_mshr_misses_0 310 # number of ReadReq MSHR misses 316system.cpu.icache.ReadReq_mshr_misses_1 309 # number of ReadReq MSHR misses 317system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 318system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 319system.cpu.icache.avg_refs 3.618740 # Average number of references to valid blocks. 320system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked 321system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked 322system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 323system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked 324system.cpu.icache.cache_copies 0 # number of cache copies performed 325system.cpu.icache.demand_accesses 2863 # number of demand (read+write) accesses 326system.cpu.icache.demand_accesses_0 1463 # number of demand (read+write) accesses 327system.cpu.icache.demand_accesses_1 1400 # number of demand (read+write) accesses 328system.cpu.icache.demand_avg_miss_latency 2.982343 # average overall miss latency 329system.cpu.icache.demand_avg_miss_latency_0 2.974441 # average overall miss latency 330system.cpu.icache.demand_avg_miss_latency_1 2.990323 # average overall miss latency 331system.cpu.icache.demand_avg_mshr_miss_latency 1.995153 # average overall mshr miss latency 332system.cpu.icache.demand_avg_mshr_miss_latency_0 1.993548 # average overall mshr miss latency 333system.cpu.icache.demand_avg_mshr_miss_latency_1 1.996764 # average overall mshr miss latency 334system.cpu.icache.demand_hits 2240 # number of demand (read+write) hits 335system.cpu.icache.demand_hits_0 1150 # number of demand (read+write) hits 336system.cpu.icache.demand_hits_1 1090 # number of demand (read+write) hits 337system.cpu.icache.demand_miss_latency 1858 # number of demand (read+write) miss cycles 338system.cpu.icache.demand_miss_latency_0 931 # number of demand (read+write) miss cycles 339system.cpu.icache.demand_miss_latency_1 927 # number of demand (read+write) miss cycles 340system.cpu.icache.demand_miss_rate 0.217604 # miss rate for demand accesses 341system.cpu.icache.demand_miss_rate_0 0.213944 # miss rate for demand accesses 342system.cpu.icache.demand_miss_rate_1 0.221429 # miss rate for demand accesses 343system.cpu.icache.demand_misses 623 # number of demand (read+write) misses 344system.cpu.icache.demand_misses_0 313 # number of demand (read+write) misses 345system.cpu.icache.demand_misses_1 310 # number of demand (read+write) misses 346system.cpu.icache.demand_mshr_hits 4 # number of demand (read+write) MSHR hits 347system.cpu.icache.demand_mshr_hits_0 3 # number of demand (read+write) MSHR hits 348system.cpu.icache.demand_mshr_hits_1 1 # number of demand (read+write) MSHR hits 349system.cpu.icache.demand_mshr_miss_latency 1235 # number of demand (read+write) MSHR miss cycles 350system.cpu.icache.demand_mshr_miss_latency_0 618 # number of demand (read+write) MSHR miss cycles 351system.cpu.icache.demand_mshr_miss_latency_1 617 # number of demand (read+write) MSHR miss cycles 352system.cpu.icache.demand_mshr_miss_rate 0.216207 # mshr miss rate for demand accesses 353system.cpu.icache.demand_mshr_miss_rate_0 0.211893 # mshr miss rate for demand accesses 354system.cpu.icache.demand_mshr_miss_rate_1 0.220714 # mshr miss rate for demand accesses 355system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses 356system.cpu.icache.demand_mshr_misses_0 310 # number of demand (read+write) MSHR misses 357system.cpu.icache.demand_mshr_misses_1 309 # number of demand (read+write) MSHR misses 358system.cpu.icache.fast_writes 0 # number of fast writes performed 359system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 360system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated 361system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated 362system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 363system.cpu.icache.overall_accesses 2863 # number of overall (read+write) accesses 364system.cpu.icache.overall_accesses_0 1463 # number of overall (read+write) accesses 365system.cpu.icache.overall_accesses_1 1400 # number of overall (read+write) accesses 366system.cpu.icache.overall_avg_miss_latency 2.982343 # average overall miss latency 367system.cpu.icache.overall_avg_miss_latency_0 2.974441 # average overall miss latency 368system.cpu.icache.overall_avg_miss_latency_1 2.990323 # average overall miss latency 369system.cpu.icache.overall_avg_mshr_miss_latency 1.995153 # average overall mshr miss latency 370system.cpu.icache.overall_avg_mshr_miss_latency_0 1.993548 # average overall mshr miss latency 371system.cpu.icache.overall_avg_mshr_miss_latency_1 1.996764 # average overall mshr miss latency 372system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 373system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency 374system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency 375system.cpu.icache.overall_hits 2240 # number of overall hits 376system.cpu.icache.overall_hits_0 1150 # number of overall hits 377system.cpu.icache.overall_hits_1 1090 # number of overall hits 378system.cpu.icache.overall_miss_latency 1858 # number of overall miss cycles 379system.cpu.icache.overall_miss_latency_0 931 # number of overall miss cycles 380system.cpu.icache.overall_miss_latency_1 927 # number of overall miss cycles 381system.cpu.icache.overall_miss_rate 0.217604 # miss rate for overall accesses 382system.cpu.icache.overall_miss_rate_0 0.213944 # miss rate for overall accesses 383system.cpu.icache.overall_miss_rate_1 0.221429 # miss rate for overall accesses 384system.cpu.icache.overall_misses 623 # number of overall misses 385system.cpu.icache.overall_misses_0 313 # number of overall misses 386system.cpu.icache.overall_misses_1 310 # number of overall misses 387system.cpu.icache.overall_mshr_hits 4 # number of overall MSHR hits 388system.cpu.icache.overall_mshr_hits_0 3 # number of overall MSHR hits 389system.cpu.icache.overall_mshr_hits_1 1 # number of overall MSHR hits 390system.cpu.icache.overall_mshr_miss_latency 1235 # number of overall MSHR miss cycles 391system.cpu.icache.overall_mshr_miss_latency_0 618 # number of overall MSHR miss cycles 392system.cpu.icache.overall_mshr_miss_latency_1 617 # number of overall MSHR miss cycles 393system.cpu.icache.overall_mshr_miss_rate 0.216207 # mshr miss rate for overall accesses 394system.cpu.icache.overall_mshr_miss_rate_0 0.211893 # mshr miss rate for overall accesses 395system.cpu.icache.overall_mshr_miss_rate_1 0.220714 # mshr miss rate for overall accesses 396system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses 397system.cpu.icache.overall_mshr_misses_0 310 # number of overall MSHR misses 398system.cpu.icache.overall_mshr_misses_1 309 # number of overall MSHR misses 399system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 400system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles 401system.cpu.icache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles 402system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 403system.cpu.icache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses 404system.cpu.icache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses 405system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 406system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 407system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 408system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 409system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 410system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 411system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 412system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 413system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 414system.cpu.icache.replacements 9 # number of replacements 415system.cpu.icache.replacements_0 9 # number of replacements 416system.cpu.icache.replacements_1 0 # number of replacements 417system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. 418system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 419system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions 420system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions 421system.cpu.icache.tagsinuse 332.781969 # Cycle average of tags in use 422system.cpu.icache.total_refs 2240 # Total number of references to valid blocks. 423system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 424system.cpu.icache.writebacks 0 # number of writebacks 425system.cpu.icache.writebacks_0 0 # number of writebacks 426system.cpu.icache.writebacks_1 0 # number of writebacks 427system.cpu.iew.EXEC:branches 2317 # Number of branches executed 428system.cpu.iew.EXEC:branches_0 1161 # Number of branches executed 429system.cpu.iew.EXEC:branches_1 1156 # Number of branches executed 430system.cpu.iew.EXEC:nop 65 # number of nop insts executed 431system.cpu.iew.EXEC:nop_0 31 # number of nop insts executed 432system.cpu.iew.EXEC:nop_1 34 # number of nop insts executed 433system.cpu.iew.EXEC:rate 1.816845 # Inst execution rate 434system.cpu.iew.EXEC:refs 4932 # number of memory reference insts executed 435system.cpu.iew.EXEC:refs_0 2476 # number of memory reference insts executed 436system.cpu.iew.EXEC:refs_1 2456 # number of memory reference insts executed 437system.cpu.iew.EXEC:stores 1873 # Number of stores executed 438system.cpu.iew.EXEC:stores_0 938 # Number of stores executed 439system.cpu.iew.EXEC:stores_1 935 # Number of stores executed 440system.cpu.iew.EXEC:swp 0 # number of swp insts executed 441system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed 442system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed 443system.cpu.iew.WB:consumers 9998 # num instructions consuming a value 444system.cpu.iew.WB:consumers_0 5018 # num instructions consuming a value 445system.cpu.iew.WB:consumers_1 4980 # num instructions consuming a value 446system.cpu.iew.WB:count 14809 # cumulative count of insts written-back 447system.cpu.iew.WB:count_0 7426 # cumulative count of insts written-back 448system.cpu.iew.WB:count_1 7383 # cumulative count of insts written-back 449system.cpu.iew.WB:fanout 0.777255 # average fanout of values written-back 450system.cpu.iew.WB:fanout_0 0.776206 # average fanout of values written-back 451system.cpu.iew.WB:fanout_1 0.778313 # average fanout of values written-back 452system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ 453system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ 454system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ 455system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 456system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ 457system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ 458system.cpu.iew.WB:producers 7771 # num instructions producing a value 459system.cpu.iew.WB:producers_0 3895 # num instructions producing a value 460system.cpu.iew.WB:producers_1 3876 # num instructions producing a value 461system.cpu.iew.WB:rate 1.756702 # insts written-back per cycle 462system.cpu.iew.WB:rate_0 0.880902 # insts written-back per cycle 463system.cpu.iew.WB:rate_1 0.875801 # insts written-back per cycle 464system.cpu.iew.WB:sent 14942 # cumulative count of insts sent to commit 465system.cpu.iew.WB:sent_0 7492 # cumulative count of insts sent to commit 466system.cpu.iew.WB:sent_1 7450 # cumulative count of insts sent to commit 467system.cpu.iew.branchMispredicts 921 # Number of branch mispredicts detected at execute 468system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking 469system.cpu.iew.iewDispLoadInsts 3709 # Number of dispatched load instructions 470system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions 471system.cpu.iew.iewDispSquashedInsts 562 # Number of squashed instructions skipped by dispatch 472system.cpu.iew.iewDispStoreInsts 2218 # Number of dispatched store instructions 473system.cpu.iew.iewDispatchedInsts 18824 # Number of instructions dispatched to IQ 474system.cpu.iew.iewExecLoadInsts 3059 # Number of load instructions executed 475system.cpu.iew.iewExecLoadInsts_0 1538 # Number of load instructions executed 476system.cpu.iew.iewExecLoadInsts_1 1521 # Number of load instructions executed 477system.cpu.iew.iewExecSquashedInsts 941 # Number of squashed instructions skipped in execute 478system.cpu.iew.iewExecutedInsts 15316 # Number of executed instructions 479system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 480system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 481system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 482system.cpu.iew.iewSquashCycles 1395 # Number of cycles IEW is squashing 483system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking 484system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding 485system.cpu.iew.lsq.thread.0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked 486system.cpu.iew.lsq.thread.0.forwLoads 45 # Number of loads that had data forwarded from stores 487system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 488system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 489system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 490system.cpu.iew.lsq.thread.0.memOrderViolation 32 # Number of memory ordering violations 491system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled 492system.cpu.iew.lsq.thread.0.squashedLoads 894 # Number of loads squashed 493system.cpu.iew.lsq.thread.0.squashedStores 298 # Number of stores squashed 494system.cpu.iew.lsq.thread.1.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding 495system.cpu.iew.lsq.thread.1.cacheBlocked 6 # Number of times an access to memory failed due to the cache being blocked 496system.cpu.iew.lsq.thread.1.forwLoads 44 # Number of loads that had data forwarded from stores 497system.cpu.iew.lsq.thread.1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 498system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address 499system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 500system.cpu.iew.lsq.thread.1.memOrderViolation 35 # Number of memory ordering violations 501system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled 502system.cpu.iew.lsq.thread.1.squashedLoads 857 # Number of loads squashed 503system.cpu.iew.lsq.thread.1.squashedStores 296 # Number of stores squashed 504system.cpu.iew.memOrderViolationEvents 67 # Number of memory order violations 505system.cpu.iew.predictedNotTakenIncorrect 763 # Number of branches that were predicted not taken incorrectly 506system.cpu.iew.predictedTakenIncorrect 158 # Number of branches that were predicted taken incorrectly 507system.cpu.ipc_0 0.667102 # IPC: Instructions Per Cycle 508system.cpu.ipc_1 0.667220 # IPC: Instructions Per Cycle 509system.cpu.ipc_total 1.334322 # IPC: Total IPC of All Threads 510system.cpu.iq.ISSUE:FU_type_0 8176 # Type of FU issued 511system.cpu.iq.ISSUE:FU_type_0.start_dist 512 (null) 2 0.02% # Type of FU issued 513 IntAlu 5526 67.59% # Type of FU issued 514 IntMult 1 0.01% # Type of FU issued 515 IntDiv 0 0.00% # Type of FU issued 516 FloatAdd 2 0.02% # Type of FU issued 517 FloatCmp 0 0.00% # Type of FU issued 518 FloatCvt 0 0.00% # Type of FU issued 519 FloatMult 0 0.00% # Type of FU issued 520 FloatDiv 0 0.00% # Type of FU issued 521 FloatSqrt 0 0.00% # Type of FU issued 522 MemRead 1667 20.39% # Type of FU issued 523 MemWrite 978 11.96% # Type of FU issued 524 IprAccess 0 0.00% # Type of FU issued 525 InstPrefetch 0 0.00% # Type of FU issued 526system.cpu.iq.ISSUE:FU_type_0.end_dist 527system.cpu.iq.ISSUE:FU_type_1 8081 # Type of FU issued 528system.cpu.iq.ISSUE:FU_type_1.start_dist 529 (null) 2 0.02% # Type of FU issued 530 IntAlu 5475 67.75% # Type of FU issued 531 IntMult 1 0.01% # Type of FU issued 532 IntDiv 0 0.00% # Type of FU issued 533 FloatAdd 2 0.02% # Type of FU issued 534 FloatCmp 0 0.00% # Type of FU issued 535 FloatCvt 0 0.00% # Type of FU issued 536 FloatMult 0 0.00% # Type of FU issued 537 FloatDiv 0 0.00% # Type of FU issued 538 FloatSqrt 0 0.00% # Type of FU issued 539 MemRead 1638 20.27% # Type of FU issued 540 MemWrite 963 11.92% # Type of FU issued 541 IprAccess 0 0.00% # Type of FU issued 542 InstPrefetch 0 0.00% # Type of FU issued 543system.cpu.iq.ISSUE:FU_type_1.end_dist 544system.cpu.iq.ISSUE:FU_type 16257 # Type of FU issued 545system.cpu.iq.ISSUE:FU_type.start_dist 546 (null) 4 0.02% # Type of FU issued 547 IntAlu 11001 67.67% # Type of FU issued 548 IntMult 2 0.01% # Type of FU issued 549 IntDiv 0 0.00% # Type of FU issued 550 FloatAdd 4 0.02% # Type of FU issued 551 FloatCmp 0 0.00% # Type of FU issued 552 FloatCvt 0 0.00% # Type of FU issued 553 FloatMult 0 0.00% # Type of FU issued 554 FloatDiv 0 0.00% # Type of FU issued 555 FloatSqrt 0 0.00% # Type of FU issued 556 MemRead 3305 20.33% # Type of FU issued 557 MemWrite 1941 11.94% # Type of FU issued 558 IprAccess 0 0.00% # Type of FU issued 559 InstPrefetch 0 0.00% # Type of FU issued 560system.cpu.iq.ISSUE:FU_type.end_dist 561system.cpu.iq.ISSUE:fu_busy_cnt 185 # FU busy when requested 562system.cpu.iq.ISSUE:fu_busy_cnt_0 102 # FU busy when requested 563system.cpu.iq.ISSUE:fu_busy_cnt_1 83 # FU busy when requested 564system.cpu.iq.ISSUE:fu_busy_rate 0.011380 # FU busy rate (busy events/executed inst) 565system.cpu.iq.ISSUE:fu_busy_rate_0 0.006274 # FU busy rate (busy events/executed inst) 566system.cpu.iq.ISSUE:fu_busy_rate_1 0.005105 # FU busy rate (busy events/executed inst) 567system.cpu.iq.ISSUE:fu_full.start_dist 568 (null) 0 0.00% # attempts to use FU when none available 569 IntAlu 10 5.41% # attempts to use FU when none available 570 IntMult 0 0.00% # attempts to use FU when none available 571 IntDiv 0 0.00% # attempts to use FU when none available 572 FloatAdd 0 0.00% # attempts to use FU when none available 573 FloatCmp 0 0.00% # attempts to use FU when none available 574 FloatCvt 0 0.00% # attempts to use FU when none available 575 FloatMult 0 0.00% # attempts to use FU when none available 576 FloatDiv 0 0.00% # attempts to use FU when none available 577 FloatSqrt 0 0.00% # attempts to use FU when none available 578 MemRead 105 56.76% # attempts to use FU when none available 579 MemWrite 70 37.84% # attempts to use FU when none available 580 IprAccess 0 0.00% # attempts to use FU when none available 581 InstPrefetch 0 0.00% # attempts to use FU when none available 582system.cpu.iq.ISSUE:fu_full.end_dist 583system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle 584system.cpu.iq.ISSUE:issued_per_cycle.samples 8430 585system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 586 0 2671 3168.45% 587 1 1437 1704.63% 588 2 1466 1739.03% 589 3 1108 1314.35% 590 4 752 892.05% 591 5 584 692.76% 592 6 285 338.08% 593 7 90 106.76% 594 8 37 43.89% 595system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 596system.cpu.iq.ISSUE:issued_per_cycle.end_dist 597 598system.cpu.iq.ISSUE:rate 1.928470 # Inst issue rate 599system.cpu.iq.iqInstsAdded 18719 # Number of instructions added to the IQ (excludes non-spec) 600system.cpu.iq.iqInstsIssued 16257 # Number of instructions issued 601system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ 602system.cpu.iq.iqSquashedInstsExamined 6696 # Number of squashed instructions iterated over during squash; mainly for profiling 603system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued 604system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed 605system.cpu.iq.iqSquashedOperandsExamined 4128 # Number of squashed operands that are examined and possibly removed from graph 606system.cpu.l2cache.ReadReq_accesses 972 # number of ReadReq accesses(hits+misses) 607system.cpu.l2cache.ReadReq_accesses_0 495 # number of ReadReq accesses(hits+misses) 608system.cpu.l2cache.ReadReq_accesses_1 477 # number of ReadReq accesses(hits+misses) 609system.cpu.l2cache.ReadReq_avg_miss_latency 2.035160 # average ReadReq miss latency 610system.cpu.l2cache.ReadReq_avg_miss_latency_0 2.020325 # average ReadReq miss latency 611system.cpu.l2cache.ReadReq_avg_miss_latency_1 2.050526 # average ReadReq miss latency 612system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency 613system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 1 # average ReadReq mshr miss latency 614system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_1 1 # average ReadReq mshr miss latency 615system.cpu.l2cache.ReadReq_hits 5 # number of ReadReq hits 616system.cpu.l2cache.ReadReq_hits_0 3 # number of ReadReq hits 617system.cpu.l2cache.ReadReq_hits_1 2 # number of ReadReq hits 618system.cpu.l2cache.ReadReq_miss_latency 1968 # number of ReadReq miss cycles 619system.cpu.l2cache.ReadReq_miss_latency_0 994 # number of ReadReq miss cycles 620system.cpu.l2cache.ReadReq_miss_latency_1 974 # number of ReadReq miss cycles 621system.cpu.l2cache.ReadReq_miss_rate 0.994856 # miss rate for ReadReq accesses 622system.cpu.l2cache.ReadReq_miss_rate_0 0.993939 # miss rate for ReadReq accesses 623system.cpu.l2cache.ReadReq_miss_rate_1 0.995807 # miss rate for ReadReq accesses 624system.cpu.l2cache.ReadReq_misses 967 # number of ReadReq misses 625system.cpu.l2cache.ReadReq_misses_0 492 # number of ReadReq misses 626system.cpu.l2cache.ReadReq_misses_1 475 # number of ReadReq misses 627system.cpu.l2cache.ReadReq_mshr_miss_latency 953 # number of ReadReq MSHR miss cycles 628system.cpu.l2cache.ReadReq_mshr_miss_latency_0 478 # number of ReadReq MSHR miss cycles 629system.cpu.l2cache.ReadReq_mshr_miss_latency_1 475 # number of ReadReq MSHR miss cycles 630system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980453 # mshr miss rate for ReadReq accesses 631system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.965657 # mshr miss rate for ReadReq accesses 632system.cpu.l2cache.ReadReq_mshr_miss_rate_1 0.995807 # mshr miss rate for ReadReq accesses 633system.cpu.l2cache.ReadReq_mshr_misses 953 # number of ReadReq MSHR misses 634system.cpu.l2cache.ReadReq_mshr_misses_0 478 # number of ReadReq MSHR misses 635system.cpu.l2cache.ReadReq_mshr_misses_1 475 # number of ReadReq MSHR misses 636system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 637system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 638system.cpu.l2cache.avg_refs 0.005171 # Average number of references to valid blocks. 639system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked 640system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked 641system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 642system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked 643system.cpu.l2cache.cache_copies 0 # number of cache copies performed 644system.cpu.l2cache.demand_accesses 972 # number of demand (read+write) accesses 645system.cpu.l2cache.demand_accesses_0 495 # number of demand (read+write) accesses 646system.cpu.l2cache.demand_accesses_1 477 # number of demand (read+write) accesses 647system.cpu.l2cache.demand_avg_miss_latency 2.035160 # average overall miss latency 648system.cpu.l2cache.demand_avg_miss_latency_0 2.020325 # average overall miss latency 649system.cpu.l2cache.demand_avg_miss_latency_1 2.050526 # average overall miss latency 650system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency 651system.cpu.l2cache.demand_avg_mshr_miss_latency_0 1 # average overall mshr miss latency 652system.cpu.l2cache.demand_avg_mshr_miss_latency_1 1 # average overall mshr miss latency 653system.cpu.l2cache.demand_hits 5 # number of demand (read+write) hits 654system.cpu.l2cache.demand_hits_0 3 # number of demand (read+write) hits 655system.cpu.l2cache.demand_hits_1 2 # number of demand (read+write) hits 656system.cpu.l2cache.demand_miss_latency 1968 # number of demand (read+write) miss cycles 657system.cpu.l2cache.demand_miss_latency_0 994 # number of demand (read+write) miss cycles 658system.cpu.l2cache.demand_miss_latency_1 974 # number of demand (read+write) miss cycles 659system.cpu.l2cache.demand_miss_rate 0.994856 # miss rate for demand accesses 660system.cpu.l2cache.demand_miss_rate_0 0.993939 # miss rate for demand accesses 661system.cpu.l2cache.demand_miss_rate_1 0.995807 # miss rate for demand accesses 662system.cpu.l2cache.demand_misses 967 # number of demand (read+write) misses 663system.cpu.l2cache.demand_misses_0 492 # number of demand (read+write) misses 664system.cpu.l2cache.demand_misses_1 475 # number of demand (read+write) misses 665system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 666system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits 667system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits 668system.cpu.l2cache.demand_mshr_miss_latency 953 # number of demand (read+write) MSHR miss cycles 669system.cpu.l2cache.demand_mshr_miss_latency_0 478 # number of demand (read+write) MSHR miss cycles 670system.cpu.l2cache.demand_mshr_miss_latency_1 475 # number of demand (read+write) MSHR miss cycles 671system.cpu.l2cache.demand_mshr_miss_rate 0.980453 # mshr miss rate for demand accesses 672system.cpu.l2cache.demand_mshr_miss_rate_0 0.965657 # mshr miss rate for demand accesses 673system.cpu.l2cache.demand_mshr_miss_rate_1 0.995807 # mshr miss rate for demand accesses 674system.cpu.l2cache.demand_mshr_misses 953 # number of demand (read+write) MSHR misses 675system.cpu.l2cache.demand_mshr_misses_0 478 # number of demand (read+write) MSHR misses 676system.cpu.l2cache.demand_mshr_misses_1 475 # number of demand (read+write) MSHR misses 677system.cpu.l2cache.fast_writes 0 # number of fast writes performed 678system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 679system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated 680system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated 681system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 682system.cpu.l2cache.overall_accesses 972 # number of overall (read+write) accesses 683system.cpu.l2cache.overall_accesses_0 495 # number of overall (read+write) accesses 684system.cpu.l2cache.overall_accesses_1 477 # number of overall (read+write) accesses 685system.cpu.l2cache.overall_avg_miss_latency 2.035160 # average overall miss latency 686system.cpu.l2cache.overall_avg_miss_latency_0 2.020325 # average overall miss latency 687system.cpu.l2cache.overall_avg_miss_latency_1 2.050526 # average overall miss latency 688system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency 689system.cpu.l2cache.overall_avg_mshr_miss_latency_0 1 # average overall mshr miss latency 690system.cpu.l2cache.overall_avg_mshr_miss_latency_1 1 # average overall mshr miss latency 691system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 692system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency 693system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency 694system.cpu.l2cache.overall_hits 5 # number of overall hits 695system.cpu.l2cache.overall_hits_0 3 # number of overall hits 696system.cpu.l2cache.overall_hits_1 2 # number of overall hits 697system.cpu.l2cache.overall_miss_latency 1968 # number of overall miss cycles 698system.cpu.l2cache.overall_miss_latency_0 994 # number of overall miss cycles 699system.cpu.l2cache.overall_miss_latency_1 974 # number of overall miss cycles 700system.cpu.l2cache.overall_miss_rate 0.994856 # miss rate for overall accesses 701system.cpu.l2cache.overall_miss_rate_0 0.993939 # miss rate for overall accesses 702system.cpu.l2cache.overall_miss_rate_1 0.995807 # miss rate for overall accesses 703system.cpu.l2cache.overall_misses 967 # number of overall misses 704system.cpu.l2cache.overall_misses_0 492 # number of overall misses 705system.cpu.l2cache.overall_misses_1 475 # number of overall misses 706system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 707system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits 708system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits 709system.cpu.l2cache.overall_mshr_miss_latency 953 # number of overall MSHR miss cycles 710system.cpu.l2cache.overall_mshr_miss_latency_0 478 # number of overall MSHR miss cycles 711system.cpu.l2cache.overall_mshr_miss_latency_1 475 # number of overall MSHR miss cycles 712system.cpu.l2cache.overall_mshr_miss_rate 0.980453 # mshr miss rate for overall accesses 713system.cpu.l2cache.overall_mshr_miss_rate_0 0.965657 # mshr miss rate for overall accesses 714system.cpu.l2cache.overall_mshr_miss_rate_1 0.995807 # mshr miss rate for overall accesses 715system.cpu.l2cache.overall_mshr_misses 953 # number of overall MSHR misses 716system.cpu.l2cache.overall_mshr_misses_0 478 # number of overall MSHR misses 717system.cpu.l2cache.overall_mshr_misses_1 475 # number of overall MSHR misses 718system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 719system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles 720system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles 721system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 722system.cpu.l2cache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses 723system.cpu.l2cache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses 724system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 725system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 726system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 727system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 728system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 729system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 730system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 731system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 732system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 733system.cpu.l2cache.replacements 0 # number of replacements 734system.cpu.l2cache.replacements_0 0 # number of replacements 735system.cpu.l2cache.replacements_1 0 # number of replacements 736system.cpu.l2cache.sampled_refs 967 # Sample count of references to valid blocks. 737system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 738system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions 739system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions 740system.cpu.l2cache.tagsinuse 569.253381 # Cycle average of tags in use 741system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. 742system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 743system.cpu.l2cache.writebacks 0 # number of writebacks 744system.cpu.l2cache.writebacks_0 0 # number of writebacks 745system.cpu.l2cache.writebacks_1 0 # number of writebacks 746system.cpu.numCycles 8430 # number of cpu cycles simulated 747system.cpu.rename.RENAME:BlockCycles 345 # Number of cycles rename is blocking 748system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed 749system.cpu.rename.RENAME:IdleCycles 9956 # Number of cycles rename is idle 750system.cpu.rename.RENAME:LSQFullEvents 693 # Number of times rename has blocked due to LSQ full 751system.cpu.rename.RENAME:RenameLookups 26837 # Number of register rename lookups that rename has made 752system.cpu.rename.RENAME:RenamedInsts 21059 # Number of instructions processed by rename 753system.cpu.rename.RENAME:RenamedOperands 15731 # Number of destination operands rename has renamed 754system.cpu.rename.RENAME:RunCycles 3562 # Number of cycles rename is running 755system.cpu.rename.RENAME:SquashCycles 1395 # Number of cycles rename is squashing 756system.cpu.rename.RENAME:UnblockCycles 766 # Number of cycles rename is unblocking 757system.cpu.rename.RENAME:UndoneMaps 7629 # Number of HB maps that are undone due to squashing 758system.cpu.rename.RENAME:serializeStallCycles 556 # count of cycles rename stalled for serializing inst 759system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed 760system.cpu.rename.RENAME:skidInsts 1898 # count of insts added to the skid buffer 761system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed 762system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls 763system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls 764 765---------- End Simulation Statistics ---------- 766