stats.txt revision 11201
13142SN/A 23142SN/A---------- Begin Simulation Statistics ---------- 310726SN/Asim_seconds 0.000025 # Number of seconds simulated 411103SN/Asim_ticks 24832500 # Number of ticks simulated 511103SN/Afinal_tick 24832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 63142SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711201Sandreas.hansson@arm.comhost_inst_rate 76523 # Simulator instruction rate (inst/s) 811201Sandreas.hansson@arm.comhost_op_rate 76517 # Simulator op (including micro ops) rate (op/s) 911201Sandreas.hansson@arm.comhost_tick_rate 149086837 # Simulator tick rate (ticks/s) 1011201Sandreas.hansson@arm.comhost_mem_usage 297164 # Number of bytes of host memory used 1111201Sandreas.hansson@arm.comhost_seconds 0.17 # Real time elapsed on the host 1210352SN/Asim_insts 12744 # Number of instructions simulated 1310352SN/Asim_ops 12744 # Number of ops (including micro ops) simulated 1410036SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611103SN/Asystem.physmem.bytes_read::cpu.inst 40448 # Number of bytes read from this memory 1711103SN/Asystem.physmem.bytes_read::cpu.data 22016 # Number of bytes read from this memory 1811103SN/Asystem.physmem.bytes_read::total 62464 # Number of bytes read from this memory 1911103SN/Asystem.physmem.bytes_inst_read::cpu.inst 40448 # Number of instructions bytes read from this memory 2011103SN/Asystem.physmem.bytes_inst_read::total 40448 # Number of instructions bytes read from this memory 2111103SN/Asystem.physmem.num_reads::cpu.inst 632 # Number of read requests responded to by this memory 2211103SN/Asystem.physmem.num_reads::cpu.data 344 # Number of read requests responded to by this memory 2311103SN/Asystem.physmem.num_reads::total 976 # Number of read requests responded to by this memory 2411103SN/Asystem.physmem.bw_read::cpu.inst 1628833182 # Total read bandwidth from this memory (bytes/s) 2511103SN/Asystem.physmem.bw_read::cpu.data 886580087 # Total read bandwidth from this memory (bytes/s) 2611103SN/Asystem.physmem.bw_read::total 2515413269 # Total read bandwidth from this memory (bytes/s) 2711103SN/Asystem.physmem.bw_inst_read::cpu.inst 1628833182 # Instruction read bandwidth from this memory (bytes/s) 2811103SN/Asystem.physmem.bw_inst_read::total 1628833182 # Instruction read bandwidth from this memory (bytes/s) 2911103SN/Asystem.physmem.bw_total::cpu.inst 1628833182 # Total bandwidth to/from this memory (bytes/s) 3011103SN/Asystem.physmem.bw_total::cpu.data 886580087 # Total bandwidth to/from this memory (bytes/s) 3111103SN/Asystem.physmem.bw_total::total 2515413269 # Total bandwidth to/from this memory (bytes/s) 3211103SN/Asystem.physmem.readReqs 976 # Number of read requests accepted 339978SN/Asystem.physmem.writeReqs 0 # Number of write requests accepted 3411103SN/Asystem.physmem.readBursts 976 # Number of DRAM read bursts, including those serviced by the write queue 359978SN/Asystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3611103SN/Asystem.physmem.bytesReadDRAM 62464 # Total number of bytes read from DRAM 379978SN/Asystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978SN/Asystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 3911103SN/Asystem.physmem.bytesReadSys 62464 # Total read bytes from the system interface side 409978SN/Asystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978SN/Asystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978SN/Asystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978SN/Asystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4411103SN/Asystem.physmem.perBankRdBursts::0 84 # Per bank write bursts 4511103SN/Asystem.physmem.perBankRdBursts::1 152 # Per bank write bursts 4611103SN/Asystem.physmem.perBankRdBursts::2 78 # Per bank write bursts 4710726SN/Asystem.physmem.perBankRdBursts::3 59 # Per bank write bursts 4810628SN/Asystem.physmem.perBankRdBursts::4 88 # Per bank write bursts 4911103SN/Asystem.physmem.perBankRdBursts::5 48 # Per bank write bursts 5010726SN/Asystem.physmem.perBankRdBursts::6 33 # Per bank write bursts 5110726SN/Asystem.physmem.perBankRdBursts::7 50 # Per bank write bursts 5210726SN/Asystem.physmem.perBankRdBursts::8 42 # Per bank write bursts 5310726SN/Asystem.physmem.perBankRdBursts::9 39 # Per bank write bursts 5411103SN/Asystem.physmem.perBankRdBursts::10 29 # Per bank write bursts 5510352SN/Asystem.physmem.perBankRdBursts::11 34 # Per bank write bursts 569978SN/Asystem.physmem.perBankRdBursts::12 15 # Per bank write bursts 5710726SN/Asystem.physmem.perBankRdBursts::13 120 # Per bank write bursts 5811103SN/Asystem.physmem.perBankRdBursts::14 68 # Per bank write bursts 5910352SN/Asystem.physmem.perBankRdBursts::15 37 # Per bank write bursts 609978SN/Asystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978SN/Asystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978SN/Asystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978SN/Asystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978SN/Asystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978SN/Asystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978SN/Asystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978SN/Asystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978SN/Asystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978SN/Asystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978SN/Asystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978SN/Asystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978SN/Asystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978SN/Asystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978SN/Asystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978SN/Asystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978SN/Asystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978SN/Asystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7811103SN/Asystem.physmem.totGap 24688000 # Total gap between requests 799978SN/Asystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978SN/Asystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978SN/Asystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978SN/Asystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978SN/Asystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978SN/Asystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8511103SN/Asystem.physmem.readPktSize::6 976 # Read request sizes (log2) 869978SN/Asystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978SN/Asystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978SN/Asystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978SN/Asystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978SN/Asystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978SN/Asystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978SN/Asystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9311103SN/Asystem.physmem.rdQLenPdf::0 340 # What read queue length does an incoming req see 9411103SN/Asystem.physmem.rdQLenPdf::1 321 # What read queue length does an incoming req see 9511103SN/Asystem.physmem.rdQLenPdf::2 209 # What read queue length does an incoming req see 9611103SN/Asystem.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see 9711103SN/Asystem.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see 9811103SN/Asystem.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see 9910892SN/Asystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1009322SN/Asystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019322SN/Asystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029322SN/Asystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312SN/Asystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312SN/Asystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312SN/Asystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312SN/Asystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312SN/Asystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312SN/Asystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312SN/Asystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312SN/Asystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312SN/Asystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312SN/Asystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312SN/Asystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312SN/Asystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312SN/Asystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312SN/Asystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312SN/Asystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312SN/Asystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312SN/Asystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312SN/Asystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312SN/Asystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312SN/Asystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312SN/Asystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312SN/Asystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312SN/Asystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312SN/Asystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312SN/Asystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312SN/Asystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312SN/Asystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312SN/Asystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312SN/Asystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312SN/Asystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312SN/Asystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312SN/Asystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312SN/Asystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312SN/Asystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312SN/Asystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312SN/Asystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312SN/Asystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312SN/Asystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312SN/Asystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312SN/Asystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312SN/Asystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312SN/Asystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312SN/Asystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312SN/Asystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312SN/Asystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312SN/Asystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148SN/Asystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148SN/Asystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148SN/Asystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148SN/Asystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148SN/Asystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148SN/Asystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148SN/Asystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148SN/Asystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148SN/Asystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148SN/Asystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148SN/Asystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148SN/Asystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148SN/Asystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148SN/Asystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148SN/Asystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148SN/Asystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148SN/Asystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148SN/Asystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148SN/Asystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148SN/Asystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148SN/Asystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148SN/Asystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148SN/Asystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148SN/Asystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148SN/Asystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148SN/Asystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148SN/Asystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148SN/Asystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148SN/Asystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148SN/Asystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148SN/Asystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148SN/Asystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18911103SN/Asystem.physmem.bytesPerActivate::samples 217 # Bytes accessed per row activation 19011103SN/Asystem.physmem.bytesPerActivate::mean 280.184332 # Bytes accessed per row activation 19111103SN/Asystem.physmem.bytesPerActivate::gmean 175.894103 # Bytes accessed per row activation 19211103SN/Asystem.physmem.bytesPerActivate::stdev 284.655938 # Bytes accessed per row activation 19311103SN/Asystem.physmem.bytesPerActivate::0-127 78 35.94% 35.94% # Bytes accessed per row activation 19411103SN/Asystem.physmem.bytesPerActivate::128-255 61 28.11% 64.06% # Bytes accessed per row activation 19511103SN/Asystem.physmem.bytesPerActivate::256-383 19 8.76% 72.81% # Bytes accessed per row activation 19611103SN/Asystem.physmem.bytesPerActivate::384-511 11 5.07% 77.88% # Bytes accessed per row activation 19711103SN/Asystem.physmem.bytesPerActivate::512-639 14 6.45% 84.33% # Bytes accessed per row activation 19811103SN/Asystem.physmem.bytesPerActivate::640-767 13 5.99% 90.32% # Bytes accessed per row activation 19911103SN/Asystem.physmem.bytesPerActivate::768-895 4 1.84% 92.17% # Bytes accessed per row activation 20011103SN/Asystem.physmem.bytesPerActivate::896-1023 6 2.76% 94.93% # Bytes accessed per row activation 20111103SN/Asystem.physmem.bytesPerActivate::1024-1151 11 5.07% 100.00% # Bytes accessed per row activation 20211103SN/Asystem.physmem.bytesPerActivate::total 217 # Bytes accessed per row activation 20311103SN/Asystem.physmem.totQLat 12728500 # Total ticks spent queuing 20411103SN/Asystem.physmem.totMemAccLat 31028500 # Total ticks spent from burst creation until serviced by the DRAM 20511103SN/Asystem.physmem.totBusLat 4880000 # Total ticks spent in databus transfers 20611103SN/Asystem.physmem.avgQLat 13041.50 # Average queueing delay per DRAM burst 2079978SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20811103SN/Asystem.physmem.avgMemAccLat 31791.50 # Average memory access latency per DRAM burst 20911103SN/Asystem.physmem.avgRdBW 2515.41 # Average DRAM read bandwidth in MiByte/s 2109978SN/Asystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21111103SN/Asystem.physmem.avgRdBWSys 2515.41 # Average system read bandwidth in MiByte/s 2129978SN/Asystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2139978SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21411103SN/Asystem.physmem.busUtil 19.65 # Data bus utilization in percentage 21511103SN/Asystem.physmem.busUtilRead 19.65 # Data bus utilization in percentage for reads 2169978SN/Asystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21711103SN/Asystem.physmem.avgRdQLen 2.42 # Average read queue length when enqueuing 2189978SN/Asystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21911103SN/Asystem.physmem.readRowHits 749 # Number of row buffer hits during reads 2209312SN/Asystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22111103SN/Asystem.physmem.readRowHitRate 76.74 # Row buffer hit rate for reads 2229312SN/Asystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22311103SN/Asystem.physmem.avgGap 25295.08 # Average gap between requests 22411103SN/Asystem.physmem.pageHitRate 76.74 # Row buffer hit rate, read and write combined 22511103SN/Asystem.physmem_0.actEnergy 892080 # Energy for activate commands per rank (pJ) 22611103SN/Asystem.physmem_0.preEnergy 486750 # Energy for precharge commands per rank (pJ) 22711103SN/Asystem.physmem_0.readEnergy 4516200 # Energy for read commands per rank (pJ) 22810628SN/Asystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22910628SN/Asystem.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 23011103SN/Asystem.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ) 23111103SN/Asystem.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ) 23211103SN/Asystem.physmem_0.totalEnergy 23568270 # Total energy per rank (pJ) 23311103SN/Asystem.physmem_0.averagePower 997.862715 # Core power per rank (mW) 23410892SN/Asystem.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states 23510628SN/Asystem.physmem_0.memoryStateTime::REF 780000 # Time in different power states 23610628SN/Asystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23710726SN/Asystem.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states 23810628SN/Asystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23911103SN/Asystem.physmem_1.actEnergy 718200 # Energy for activate commands per rank (pJ) 24011103SN/Asystem.physmem_1.preEnergy 391875 # Energy for precharge commands per rank (pJ) 24111103SN/Asystem.physmem_1.readEnergy 2847000 # Energy for read commands per rank (pJ) 24210628SN/Asystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24310628SN/Asystem.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 24411103SN/Asystem.physmem_1.actBackEnergy 15524235 # Energy for active background per rank (pJ) 24511103SN/Asystem.physmem_1.preBackEnergy 557250 # Energy for precharge background per rank (pJ) 24611103SN/Asystem.physmem_1.totalEnergy 21564240 # Total energy per rank (pJ) 24711103SN/Asystem.physmem_1.averagePower 912.772063 # Core power per rank (mW) 24811103SN/Asystem.physmem_1.memoryStateTime::IDLE 830500 # Time in different power states 24910628SN/Asystem.physmem_1.memoryStateTime::REF 780000 # Time in different power states 25010628SN/Asystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25111103SN/Asystem.physmem_1.memoryStateTime::ACT 22027750 # Time in different power states 25210628SN/Asystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25311103SN/Asystem.cpu.branchPred.lookups 6978 # Number of BP lookups 25411103SN/Asystem.cpu.branchPred.condPredicted 3979 # Number of conditional branches predicted 25511103SN/Asystem.cpu.branchPred.condIncorrect 1366 # Number of conditional branches incorrect 25611103SN/Asystem.cpu.branchPred.BTBLookups 5343 # Number of BTB lookups 25711103SN/Asystem.cpu.branchPred.BTBHits 988 # Number of BTB hits 25810628SN/Asystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 25911103SN/Asystem.cpu.branchPred.BTBHitPct 18.491484 # BTB Hit Percentage 26011103SN/Asystem.cpu.branchPred.usedRAS 1115 # Number of times the RAS was used to get a target. 26111103SN/Asystem.cpu.branchPred.RASInCorrect 79 # Number of incorrect RAS predictions. 26210036SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 2638464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 2648464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 2658464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 2668464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 26711103SN/Asystem.cpu.dtb.read_hits 4756 # DTB read hits 26811103SN/Asystem.cpu.dtb.read_misses 94 # DTB read misses 2698464SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 27011103SN/Asystem.cpu.dtb.read_accesses 4850 # DTB read accesses 27111103SN/Asystem.cpu.dtb.write_hits 2093 # DTB write hits 27211103SN/Asystem.cpu.dtb.write_misses 69 # DTB write misses 2738464SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 27411103SN/Asystem.cpu.dtb.write_accesses 2162 # DTB write accesses 27511103SN/Asystem.cpu.dtb.data_hits 6849 # DTB hits 27611103SN/Asystem.cpu.dtb.data_misses 163 # DTB misses 2778464SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 27811103SN/Asystem.cpu.dtb.data_accesses 7012 # DTB accesses 27911103SN/Asystem.cpu.itb.fetch_hits 5404 # ITB hits 28011103SN/Asystem.cpu.itb.fetch_misses 57 # ITB misses 2818464SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 28211103SN/Asystem.cpu.itb.fetch_accesses 5461 # ITB accesses 2838464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2848464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2858464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 2868464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2878464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2888464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2898464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 2908464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2918464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 2928464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 2938464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 2948464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 2958464SN/Asystem.cpu.workload0.num_syscalls 17 # Number of system calls 2968464SN/Asystem.cpu.workload1.num_syscalls 17 # Number of system calls 29711103SN/Asystem.cpu.numCycles 49666 # number of cpu cycles simulated 2988464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2998464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 30011103SN/Asystem.cpu.fetch.icacheStallCycles 1235 # Number of cycles fetch is stalled on an Icache miss 30111138SN/Asystem.cpu.fetch.Insts 39551 # Number of instructions fetch has processed 30211103SN/Asystem.cpu.fetch.Branches 6978 # Number of branches that fetch encountered 30311103SN/Asystem.cpu.fetch.predictedBranches 2103 # Number of branches that fetch has predicted taken 30411138SN/Asystem.cpu.fetch.Cycles 10833 # Number of cycles fetch has run and was not squashing or blocked 30511103SN/Asystem.cpu.fetch.SquashCycles 1446 # Number of cycles fetch has spent squashing 30611103SN/Asystem.cpu.fetch.MiscStallCycles 389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 30711103SN/Asystem.cpu.fetch.CacheLines 5404 # Number of cache lines fetched 30811103SN/Asystem.cpu.fetch.IcacheSquashes 838 # Number of outstanding Icache misses that were squashed 30911103SN/Asystem.cpu.fetch.rateDist::samples 27534 # Number of instructions fetched each cycle (Total) 31011138SN/Asystem.cpu.fetch.rateDist::mean 1.436442 # Number of instructions fetched each cycle (Total) 31111138SN/Asystem.cpu.fetch.rateDist::stdev 2.801385 # Number of instructions fetched each cycle (Total) 3128464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 31311138SN/Asystem.cpu.fetch.rateDist::0 20751 75.37% 75.37% # Number of instructions fetched each cycle (Total) 31411138SN/Asystem.cpu.fetch.rateDist::1 584 2.12% 77.49% # Number of instructions fetched each cycle (Total) 31511103SN/Asystem.cpu.fetch.rateDist::2 426 1.55% 79.03% # Number of instructions fetched each cycle (Total) 31611103SN/Asystem.cpu.fetch.rateDist::3 584 2.12% 81.15% # Number of instructions fetched each cycle (Total) 31711138SN/Asystem.cpu.fetch.rateDist::4 571 2.07% 83.23% # Number of instructions fetched each cycle (Total) 31811103SN/Asystem.cpu.fetch.rateDist::5 441 1.60% 84.83% # Number of instructions fetched each cycle (Total) 31911103SN/Asystem.cpu.fetch.rateDist::6 491 1.78% 86.61% # Number of instructions fetched each cycle (Total) 32011138SN/Asystem.cpu.fetch.rateDist::7 560 2.03% 88.65% # Number of instructions fetched each cycle (Total) 32111138SN/Asystem.cpu.fetch.rateDist::8 3126 11.35% 100.00% # Number of instructions fetched each cycle (Total) 3228464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3238464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3248464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 32511103SN/Asystem.cpu.fetch.rateDist::total 27534 # Number of instructions fetched each cycle (Total) 32611103SN/Asystem.cpu.fetch.branchRate 0.140499 # Number of branch fetches per cycle 32711138SN/Asystem.cpu.fetch.rate 0.796340 # Number of inst fetches per cycle 32811138SN/Asystem.cpu.decode.IdleCycles 37297 # Number of cycles decode is idle 32911103SN/Asystem.cpu.decode.BlockedCycles 10659 # Number of cycles decode is blocked 33011103SN/Asystem.cpu.decode.RunCycles 5112 # Number of cycles decode is running 33111138SN/Asystem.cpu.decode.UnblockCycles 614 # Number of cycles decode is unblocking 33211103SN/Asystem.cpu.decode.SquashCycles 1127 # Number of cycles decode is squashing 33311103SN/Asystem.cpu.decode.BranchResolved 528 # Number of times decode resolved a branch 33411103SN/Asystem.cpu.decode.BranchMispred 328 # Number of times decode detected a branch misprediction 33511138SN/Asystem.cpu.decode.DecodedInsts 32206 # Number of instructions handled by decode 33611103SN/Asystem.cpu.decode.SquashedInsts 725 # Number of squashed instructions handled by decode 33711103SN/Asystem.cpu.rename.SquashCycles 1127 # Number of cycles rename is squashing 33811138SN/Asystem.cpu.rename.IdleCycles 37872 # Number of cycles rename is idle 33911103SN/Asystem.cpu.rename.BlockCycles 4968 # Number of cycles rename is blocking 34011103SN/Asystem.cpu.rename.serializeStallCycles 1226 # count of cycles rename stalled for serializing inst 34111138SN/Asystem.cpu.rename.RunCycles 5150 # Number of cycles rename is running 34211103SN/Asystem.cpu.rename.UnblockCycles 4466 # Number of cycles rename is unblocking 34311138SN/Asystem.cpu.rename.RenamedInsts 30281 # Number of instructions processed by rename 34411103SN/Asystem.cpu.rename.ROBFullEvents 78 # Number of times rename has blocked due to ROB full 34511103SN/Asystem.cpu.rename.IQFullEvents 324 # Number of times rename has blocked due to IQ full 34611103SN/Asystem.cpu.rename.LQFullEvents 847 # Number of times rename has blocked due to LQ full 34711103SN/Asystem.cpu.rename.SQFullEvents 3132 # Number of times rename has blocked due to SQ full 34811138SN/Asystem.cpu.rename.RenamedOperands 22821 # Number of destination operands rename has renamed 34911138SN/Asystem.cpu.rename.RenameLookups 37713 # Number of register rename lookups that rename has made 35011138SN/Asystem.cpu.rename.int_rename_lookups 37695 # Number of integer rename lookups 3519924SN/Asystem.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 3529150SN/Asystem.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed 35311138SN/Asystem.cpu.rename.UndoneMaps 13681 # Number of HB maps that are undone due to squashing 35411103SN/Asystem.cpu.rename.serializingInsts 60 # count of serializing insts renamed 35511103SN/Asystem.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed 35611103SN/Asystem.cpu.rename.skidInsts 2263 # count of insts added to the skid buffer 35711103SN/Asystem.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. 35811103SN/Asystem.cpu.memDep0.insertedStores 1407 # Number of stores inserted to the mem dependence unit. 35911103SN/Asystem.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. 36011103SN/Asystem.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. 36111103SN/Asystem.cpu.memDep1.insertedLoads 2862 # Number of loads inserted to the mem dependence unit. 36211103SN/Asystem.cpu.memDep1.insertedStores 1462 # Number of stores inserted to the mem dependence unit. 36311103SN/Asystem.cpu.memDep1.conflictingLoads 2 # Number of conflicting loads. 36410352SN/Asystem.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. 36511103SN/Asystem.cpu.iq.iqInstsAdded 27015 # Number of instructions added to the IQ (excludes non-spec) 36611103SN/Asystem.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ 36711103SN/Asystem.cpu.iq.iqInstsIssued 22338 # Number of instructions issued 36811103SN/Asystem.cpu.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued 36911103SN/Asystem.cpu.iq.iqSquashedInstsExamined 14320 # Number of squashed instructions iterated over during squash; mainly for profiling 37011103SN/Asystem.cpu.iq.iqSquashedOperandsExamined 8141 # Number of squashed operands that are examined and possibly removed from graph 37111103SN/Asystem.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed 37211103SN/Asystem.cpu.iq.issued_per_cycle::samples 27534 # Number of insts issued each cycle 37311103SN/Asystem.cpu.iq.issued_per_cycle::mean 0.811288 # Number of insts issued each cycle 37411103SN/Asystem.cpu.iq.issued_per_cycle::stdev 1.520707 # Number of insts issued each cycle 3758464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 37611103SN/Asystem.cpu.iq.issued_per_cycle::0 19179 69.66% 69.66% # Number of insts issued each cycle 37711103SN/Asystem.cpu.iq.issued_per_cycle::1 2638 9.58% 79.24% # Number of insts issued each cycle 37811103SN/Asystem.cpu.iq.issued_per_cycle::2 1919 6.97% 86.21% # Number of insts issued each cycle 37911103SN/Asystem.cpu.iq.issued_per_cycle::3 1327 4.82% 91.03% # Number of insts issued each cycle 38011103SN/Asystem.cpu.iq.issued_per_cycle::4 1227 4.46% 95.48% # Number of insts issued each cycle 38111103SN/Asystem.cpu.iq.issued_per_cycle::5 711 2.58% 98.06% # Number of insts issued each cycle 38211103SN/Asystem.cpu.iq.issued_per_cycle::6 354 1.29% 99.35% # Number of insts issued each cycle 38311103SN/Asystem.cpu.iq.issued_per_cycle::7 138 0.50% 99.85% # Number of insts issued each cycle 38411103SN/Asystem.cpu.iq.issued_per_cycle::8 41 0.15% 100.00% # Number of insts issued each cycle 3858464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3868464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3878464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 38811103SN/Asystem.cpu.iq.issued_per_cycle::total 27534 # Number of insts issued each cycle 3898464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 39011103SN/Asystem.cpu.iq.fu_full::IntAlu 32 9.64% 9.64% # attempts to use FU when none available 39111103SN/Asystem.cpu.iq.fu_full::IntMult 0 0.00% 9.64% # attempts to use FU when none available 39211103SN/Asystem.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available 39311103SN/Asystem.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available 39411103SN/Asystem.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available 39511103SN/Asystem.cpu.iq.fu_full::FloatCvt 0 0.00% 9.64% # attempts to use FU when none available 39611103SN/Asystem.cpu.iq.fu_full::FloatMult 0 0.00% 9.64% # attempts to use FU when none available 39711103SN/Asystem.cpu.iq.fu_full::FloatDiv 0 0.00% 9.64% # attempts to use FU when none available 39811103SN/Asystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.64% # attempts to use FU when none available 39911103SN/Asystem.cpu.iq.fu_full::SimdAdd 0 0.00% 9.64% # attempts to use FU when none available 40011103SN/Asystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.64% # attempts to use FU when none available 40111103SN/Asystem.cpu.iq.fu_full::SimdAlu 0 0.00% 9.64% # attempts to use FU when none available 40211103SN/Asystem.cpu.iq.fu_full::SimdCmp 0 0.00% 9.64% # attempts to use FU when none available 40311103SN/Asystem.cpu.iq.fu_full::SimdCvt 0 0.00% 9.64% # attempts to use FU when none available 40411103SN/Asystem.cpu.iq.fu_full::SimdMisc 0 0.00% 9.64% # attempts to use FU when none available 40511103SN/Asystem.cpu.iq.fu_full::SimdMult 0 0.00% 9.64% # attempts to use FU when none available 40611103SN/Asystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.64% # attempts to use FU when none available 40711103SN/Asystem.cpu.iq.fu_full::SimdShift 0 0.00% 9.64% # attempts to use FU when none available 40811103SN/Asystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.64% # attempts to use FU when none available 40911103SN/Asystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.64% # attempts to use FU when none available 41011103SN/Asystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.64% # attempts to use FU when none available 41111103SN/Asystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.64% # attempts to use FU when none available 41211103SN/Asystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.64% # attempts to use FU when none available 41311103SN/Asystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.64% # attempts to use FU when none available 41411103SN/Asystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.64% # attempts to use FU when none available 41511103SN/Asystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # attempts to use FU when none available 41611103SN/Asystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available 41711103SN/Asystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available 41811103SN/Asystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available 41911103SN/Asystem.cpu.iq.fu_full::MemRead 217 65.36% 75.00% # attempts to use FU when none available 42011103SN/Asystem.cpu.iq.fu_full::MemWrite 83 25.00% 100.00% # attempts to use FU when none available 4218464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4228464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4238464SN/Asystem.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 42411103SN/Asystem.cpu.iq.FU_type_0::IntAlu 7321 66.01% 66.03% # Type of FU issued 42511103SN/Asystem.cpu.iq.FU_type_0::IntMult 1 0.01% 66.04% # Type of FU issued 42611103SN/Asystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.04% # Type of FU issued 42711103SN/Asystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.06% # Type of FU issued 42811103SN/Asystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued 42911103SN/Asystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued 43011103SN/Asystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued 43111103SN/Asystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued 43211103SN/Asystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued 43311103SN/Asystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued 43411103SN/Asystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued 43511103SN/Asystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued 43611103SN/Asystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued 43711103SN/Asystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued 43811103SN/Asystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued 43911103SN/Asystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued 44011103SN/Asystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued 44111103SN/Asystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued 44211103SN/Asystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued 44311103SN/Asystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued 44411103SN/Asystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued 44511103SN/Asystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued 44611103SN/Asystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued 44711103SN/Asystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued 44811103SN/Asystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.06% # Type of FU issued 44911103SN/Asystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.06% # Type of FU issued 45011103SN/Asystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.06% # Type of FU issued 45111103SN/Asystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.06% # Type of FU issued 45211103SN/Asystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.06% # Type of FU issued 45311103SN/Asystem.cpu.iq.FU_type_0::MemRead 2641 23.81% 89.87% # Type of FU issued 45411103SN/Asystem.cpu.iq.FU_type_0::MemWrite 1123 10.13% 100.00% # Type of FU issued 4558464SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4568464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 45711103SN/Asystem.cpu.iq.FU_type_0::total 11090 # Type of FU issued 4588464SN/Asystem.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued 45911103SN/Asystem.cpu.iq.FU_type_1::IntAlu 7446 66.20% 66.22% # Type of FU issued 46011103SN/Asystem.cpu.iq.FU_type_1::IntMult 1 0.01% 66.23% # Type of FU issued 46111103SN/Asystem.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.23% # Type of FU issued 46211103SN/Asystem.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.24% # Type of FU issued 46311103SN/Asystem.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.24% # Type of FU issued 46411103SN/Asystem.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.24% # Type of FU issued 46511103SN/Asystem.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.24% # Type of FU issued 46611103SN/Asystem.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.24% # Type of FU issued 46711103SN/Asystem.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.24% # Type of FU issued 46811103SN/Asystem.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.24% # Type of FU issued 46911103SN/Asystem.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.24% # Type of FU issued 47011103SN/Asystem.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.24% # Type of FU issued 47111103SN/Asystem.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.24% # Type of FU issued 47211103SN/Asystem.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.24% # Type of FU issued 47311103SN/Asystem.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.24% # Type of FU issued 47411103SN/Asystem.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.24% # Type of FU issued 47511103SN/Asystem.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.24% # Type of FU issued 47611103SN/Asystem.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.24% # Type of FU issued 47711103SN/Asystem.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.24% # Type of FU issued 47811103SN/Asystem.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.24% # Type of FU issued 47911103SN/Asystem.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.24% # Type of FU issued 48011103SN/Asystem.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.24% # Type of FU issued 48111103SN/Asystem.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.24% # Type of FU issued 48211103SN/Asystem.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.24% # Type of FU issued 48311103SN/Asystem.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.24% # Type of FU issued 48411103SN/Asystem.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.24% # Type of FU issued 48511103SN/Asystem.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.24% # Type of FU issued 48611103SN/Asystem.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.24% # Type of FU issued 48711103SN/Asystem.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.24% # Type of FU issued 48811103SN/Asystem.cpu.iq.FU_type_1::MemRead 2645 23.52% 89.76% # Type of FU issued 48911103SN/Asystem.cpu.iq.FU_type_1::MemWrite 1152 10.24% 100.00% # Type of FU issued 4908464SN/Asystem.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 4918464SN/Asystem.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued 49211103SN/Asystem.cpu.iq.FU_type_1::total 11248 # Type of FU issued 49311103SN/Asystem.cpu.iq.FU_type::total 22338 0.00% 0.00% # Type of FU issued 49411103SN/Asystem.cpu.iq.rate 0.449764 # Inst issue rate 49511103SN/Asystem.cpu.iq.fu_busy_cnt::0 166 # FU busy when requested 49611103SN/Asystem.cpu.iq.fu_busy_cnt::1 166 # FU busy when requested 49711103SN/Asystem.cpu.iq.fu_busy_cnt::total 332 # FU busy when requested 49811103SN/Asystem.cpu.iq.fu_busy_rate::0 0.007431 # FU busy rate (busy events/executed inst) 49911103SN/Asystem.cpu.iq.fu_busy_rate::1 0.007431 # FU busy rate (busy events/executed inst) 50011103SN/Asystem.cpu.iq.fu_busy_rate::total 0.014863 # FU busy rate (busy events/executed inst) 50111103SN/Asystem.cpu.iq.int_inst_queue_reads 72630 # Number of integer instruction queue reads 50211103SN/Asystem.cpu.iq.int_inst_queue_writes 41400 # Number of integer instruction queue writes 50311103SN/Asystem.cpu.iq.int_inst_queue_wakeup_accesses 19613 # Number of integer instruction queue wakeup accesses 5049729SN/Asystem.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads 5058464SN/Asystem.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 5068464SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses 50711103SN/Asystem.cpu.iq.int_alu_accesses 22644 # Number of integer alu accesses 5089729SN/Asystem.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses 50911103SN/Asystem.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores 5108464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 51111103SN/Asystem.cpu.iew.lsq.thread0.squashedLoads 1651 # Number of loads squashed 51211103SN/Asystem.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 51311103SN/Asystem.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations 51411103SN/Asystem.cpu.iew.lsq.thread0.squashedStores 542 # Number of stores squashed 5158464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5168464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 5179322SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 51811103SN/Asystem.cpu.iew.lsq.thread0.cacheBlocked 309 # Number of times an access to memory failed due to the cache being blocked 51911103SN/Asystem.cpu.iew.lsq.thread1.forwLoads 73 # Number of loads that had data forwarded from stores 5208464SN/Asystem.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address 52111103SN/Asystem.cpu.iew.lsq.thread1.squashedLoads 1679 # Number of loads squashed 52211103SN/Asystem.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 52311103SN/Asystem.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations 52411103SN/Asystem.cpu.iew.lsq.thread1.squashedStores 597 # Number of stores squashed 5258464SN/Asystem.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5268464SN/Asystem.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 5278464SN/Asystem.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled 52811103SN/Asystem.cpu.iew.lsq.thread1.cacheBlocked 327 # Number of times an access to memory failed due to the cache being blocked 5298464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 53011103SN/Asystem.cpu.iew.iewSquashCycles 1127 # Number of cycles IEW is squashing 53111103SN/Asystem.cpu.iew.iewBlockCycles 2708 # Number of cycles IEW is blocking 53211103SN/Asystem.cpu.iew.iewUnblockCycles 614 # Number of cycles IEW is unblocking 53311103SN/Asystem.cpu.iew.iewDispatchedInsts 27211 # Number of instructions dispatched to IQ 53411103SN/Asystem.cpu.iew.iewDispSquashedInsts 237 # Number of squashed instructions skipped by dispatch 53511103SN/Asystem.cpu.iew.iewDispLoadInsts 5696 # Number of dispatched load instructions 53611103SN/Asystem.cpu.iew.iewDispStoreInsts 2869 # Number of dispatched store instructions 53711103SN/Asystem.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions 53811103SN/Asystem.cpu.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall 53911103SN/Asystem.cpu.iew.iewLSQFullEvents 589 # Number of times the LSQ has become full, causing a stall 54011103SN/Asystem.cpu.iew.memOrderViolationEvents 37 # Number of memory order violations 54111103SN/Asystem.cpu.iew.predictedTakenIncorrect 160 # Number of branches that were predicted taken incorrectly 54211103SN/Asystem.cpu.iew.predictedNotTakenIncorrect 1089 # Number of branches that were predicted not taken incorrectly 54311103SN/Asystem.cpu.iew.branchMispredicts 1249 # Number of branch mispredicts detected at execute 54411103SN/Asystem.cpu.iew.iewExecutedInsts 21052 # Number of executed instructions 54511103SN/Asystem.cpu.iew.iewExecLoadInsts::0 2447 # Number of load instructions executed 54611103SN/Asystem.cpu.iew.iewExecLoadInsts::1 2411 # Number of load instructions executed 54711103SN/Asystem.cpu.iew.iewExecLoadInsts::total 4858 # Number of load instructions executed 54811103SN/Asystem.cpu.iew.iewExecSquashedInsts 1286 # Number of squashed instructions skipped in execute 5498464SN/Asystem.cpu.iew.exec_swp::0 0 # number of swp insts executed 5508464SN/Asystem.cpu.iew.exec_swp::1 0 # number of swp insts executed 5518464SN/Asystem.cpu.iew.exec_swp::total 0 # number of swp insts executed 55210892SN/Asystem.cpu.iew.exec_nop::0 74 # number of nop insts executed 55311103SN/Asystem.cpu.iew.exec_nop::1 72 # number of nop insts executed 55411103SN/Asystem.cpu.iew.exec_nop::total 146 # number of nop insts executed 55511103SN/Asystem.cpu.iew.exec_refs::0 3514 # number of memory reference insts executed 55611103SN/Asystem.cpu.iew.exec_refs::1 3522 # number of memory reference insts executed 55711103SN/Asystem.cpu.iew.exec_refs::total 7036 # number of memory reference insts executed 55811103SN/Asystem.cpu.iew.exec_branches::0 1644 # Number of branches executed 55911103SN/Asystem.cpu.iew.exec_branches::1 1639 # Number of branches executed 56011103SN/Asystem.cpu.iew.exec_branches::total 3283 # Number of branches executed 56111103SN/Asystem.cpu.iew.exec_stores::0 1067 # Number of stores executed 56211103SN/Asystem.cpu.iew.exec_stores::1 1111 # Number of stores executed 56311103SN/Asystem.cpu.iew.exec_stores::total 2178 # Number of stores executed 56411103SN/Asystem.cpu.iew.exec_rate 0.423871 # Inst execution rate 56511103SN/Asystem.cpu.iew.wb_sent::0 9939 # cumulative count of insts sent to commit 56611103SN/Asystem.cpu.iew.wb_sent::1 10068 # cumulative count of insts sent to commit 56711103SN/Asystem.cpu.iew.wb_sent::total 20007 # cumulative count of insts sent to commit 56811103SN/Asystem.cpu.iew.wb_count::0 9740 # cumulative count of insts written-back 56911103SN/Asystem.cpu.iew.wb_count::1 9893 # cumulative count of insts written-back 57011103SN/Asystem.cpu.iew.wb_count::total 19633 # cumulative count of insts written-back 57111103SN/Asystem.cpu.iew.wb_producers::0 5189 # num instructions producing a value 57211103SN/Asystem.cpu.iew.wb_producers::1 5256 # num instructions producing a value 57311103SN/Asystem.cpu.iew.wb_producers::total 10445 # num instructions producing a value 57411103SN/Asystem.cpu.iew.wb_consumers::0 6868 # num instructions consuming a value 57511103SN/Asystem.cpu.iew.wb_consumers::1 6926 # num instructions consuming a value 57611103SN/Asystem.cpu.iew.wb_consumers::total 13794 # num instructions consuming a value 5778464SN/Asystem.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ 5788464SN/Asystem.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ 5798464SN/Asystem.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ 58011103SN/Asystem.cpu.iew.wb_rate::0 0.196110 # insts written-back per cycle 58111103SN/Asystem.cpu.iew.wb_rate::1 0.199191 # insts written-back per cycle 58211103SN/Asystem.cpu.iew.wb_rate::total 0.395301 # insts written-back per cycle 58311103SN/Asystem.cpu.iew.wb_fanout::0 0.755533 # average fanout of values written-back 58411103SN/Asystem.cpu.iew.wb_fanout::1 0.758880 # average fanout of values written-back 58511103SN/Asystem.cpu.iew.wb_fanout::total 0.757213 # average fanout of values written-back 5868464SN/Asystem.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ 5878464SN/Asystem.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ 5888464SN/Asystem.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ 58911103SN/Asystem.cpu.commit.commitSquashedInsts 14447 # The number of squashed insts skipped by commit 5903142SN/Asystem.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards 59111103SN/Asystem.cpu.commit.branchMispredicts 1048 # The number of times a branch was mispredicted 59211103SN/Asystem.cpu.commit.committed_per_cycle::samples 27467 # Number of insts commited each cycle 59311103SN/Asystem.cpu.commit.committed_per_cycle::mean 0.465213 # Number of insts commited each cycle 59411103SN/Asystem.cpu.commit.committed_per_cycle::stdev 1.343088 # Number of insts commited each cycle 5958241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 59611103SN/Asystem.cpu.commit.committed_per_cycle::0 22438 81.69% 81.69% # Number of insts commited each cycle 59711103SN/Asystem.cpu.commit.committed_per_cycle::1 2371 8.63% 90.32% # Number of insts commited each cycle 59811103SN/Asystem.cpu.commit.committed_per_cycle::2 1089 3.96% 94.29% # Number of insts commited each cycle 59911103SN/Asystem.cpu.commit.committed_per_cycle::3 414 1.51% 95.79% # Number of insts commited each cycle 60011103SN/Asystem.cpu.commit.committed_per_cycle::4 277 1.01% 96.80% # Number of insts commited each cycle 60111103SN/Asystem.cpu.commit.committed_per_cycle::5 199 0.72% 97.53% # Number of insts commited each cycle 60211103SN/Asystem.cpu.commit.committed_per_cycle::6 197 0.72% 98.25% # Number of insts commited each cycle 60311103SN/Asystem.cpu.commit.committed_per_cycle::7 154 0.56% 98.81% # Number of insts commited each cycle 60411103SN/Asystem.cpu.commit.committed_per_cycle::8 328 1.19% 100.00% # Number of insts commited each cycle 6058241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6068241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6078241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 60811103SN/Asystem.cpu.commit.committed_per_cycle::total 27467 # Number of insts commited each cycle 60910220SN/Asystem.cpu.commit.committedInsts::0 6389 # Number of instructions committed 61010352SN/Asystem.cpu.commit.committedInsts::1 6389 # Number of instructions committed 61110352SN/Asystem.cpu.commit.committedInsts::total 12778 # Number of instructions committed 61210220SN/Asystem.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed 61310352SN/Asystem.cpu.commit.committedOps::1 6389 # Number of ops (including micro ops) committed 61410352SN/Asystem.cpu.commit.committedOps::total 12778 # Number of ops (including micro ops) committed 6158464SN/Asystem.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 6168464SN/Asystem.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed 6178464SN/Asystem.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed 6189150SN/Asystem.cpu.commit.refs::0 2048 # Number of memory references committed 6199150SN/Asystem.cpu.commit.refs::1 2048 # Number of memory references committed 6209150SN/Asystem.cpu.commit.refs::total 4096 # Number of memory references committed 6219150SN/Asystem.cpu.commit.loads::0 1183 # Number of loads committed 6229150SN/Asystem.cpu.commit.loads::1 1183 # Number of loads committed 6239150SN/Asystem.cpu.commit.loads::total 2366 # Number of loads committed 6248241SN/Asystem.cpu.commit.membars::0 0 # Number of memory barriers committed 6258241SN/Asystem.cpu.commit.membars::1 0 # Number of memory barriers committed 6268241SN/Asystem.cpu.commit.membars::total 0 # Number of memory barriers committed 6279150SN/Asystem.cpu.commit.branches::0 1050 # Number of branches committed 6289150SN/Asystem.cpu.commit.branches::1 1050 # Number of branches committed 6299150SN/Asystem.cpu.commit.branches::total 2100 # Number of branches committed 6308464SN/Asystem.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. 6318464SN/Asystem.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. 6328464SN/Asystem.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. 6339150SN/Asystem.cpu.commit.int_insts::0 6307 # Number of committed integer instructions. 6349150SN/Asystem.cpu.commit.int_insts::1 6307 # Number of committed integer instructions. 6359150SN/Asystem.cpu.commit.int_insts::total 12614 # Number of committed integer instructions. 6368464SN/Asystem.cpu.commit.function_calls::0 127 # Number of function calls committed. 6378464SN/Asystem.cpu.commit.function_calls::1 127 # Number of function calls committed. 6388464SN/Asystem.cpu.commit.function_calls::total 254 # Number of function calls committed. 63910220SN/Asystem.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 64010220SN/Asystem.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction 64110220SN/Asystem.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction 64210220SN/Asystem.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction 64310220SN/Asystem.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction 64410220SN/Asystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction 64510220SN/Asystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction 64610220SN/Asystem.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction 64710220SN/Asystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction 64810220SN/Asystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction 64910220SN/Asystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction 65010220SN/Asystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction 65110220SN/Asystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction 65210220SN/Asystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction 65310220SN/Asystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction 65410220SN/Asystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction 65510220SN/Asystem.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction 65610220SN/Asystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction 65710220SN/Asystem.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction 65810220SN/Asystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction 65910220SN/Asystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction 66010220SN/Asystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction 66110220SN/Asystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction 66210220SN/Asystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction 66310220SN/Asystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction 66410220SN/Asystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction 66510220SN/Asystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction 66610220SN/Asystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 66710220SN/Asystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 66810220SN/Asystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 66910220SN/Asystem.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction 67010220SN/Asystem.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction 67110220SN/Asystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 67210220SN/Asystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 67310220SN/Asystem.cpu.commit.op_class_0::total 6389 # Class of committed instruction 67410220SN/Asystem.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction 67510352SN/Asystem.cpu.commit.op_class_1::IntAlu 4319 67.60% 67.90% # Class of committed instruction 67610352SN/Asystem.cpu.commit.op_class_1::IntMult 1 0.02% 67.91% # Class of committed instruction 67710352SN/Asystem.cpu.commit.op_class_1::IntDiv 0 0.00% 67.91% # Class of committed instruction 67810352SN/Asystem.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.94% # Class of committed instruction 67910352SN/Asystem.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.94% # Class of committed instruction 68010352SN/Asystem.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.94% # Class of committed instruction 68110352SN/Asystem.cpu.commit.op_class_1::FloatMult 0 0.00% 67.94% # Class of committed instruction 68210352SN/Asystem.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.94% # Class of committed instruction 68310352SN/Asystem.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.94% # Class of committed instruction 68410352SN/Asystem.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.94% # Class of committed instruction 68510352SN/Asystem.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction 68610352SN/Asystem.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.94% # Class of committed instruction 68710352SN/Asystem.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.94% # Class of committed instruction 68810352SN/Asystem.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.94% # Class of committed instruction 68910352SN/Asystem.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.94% # Class of committed instruction 69010352SN/Asystem.cpu.commit.op_class_1::SimdMult 0 0.00% 67.94% # Class of committed instruction 69110352SN/Asystem.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction 69210352SN/Asystem.cpu.commit.op_class_1::SimdShift 0 0.00% 67.94% # Class of committed instruction 69310352SN/Asystem.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction 69410352SN/Asystem.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.94% # Class of committed instruction 69510352SN/Asystem.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction 69610352SN/Asystem.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction 69710352SN/Asystem.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction 69810352SN/Asystem.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction 69910352SN/Asystem.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction 70010352SN/Asystem.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction 70110352SN/Asystem.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 70210352SN/Asystem.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 70310352SN/Asystem.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 70410352SN/Asystem.cpu.commit.op_class_1::MemRead 1183 18.52% 86.46% # Class of committed instruction 70510220SN/Asystem.cpu.commit.op_class_1::MemWrite 865 13.54% 100.00% # Class of committed instruction 70610220SN/Asystem.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction 70710220SN/Asystem.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 70810352SN/Asystem.cpu.commit.op_class_1::total 6389 # Class of committed instruction 70910352SN/Asystem.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction 71011103SN/Asystem.cpu.commit.bw_lim_events 328 # number cycles where commit BW limit reached 71111103SN/Asystem.cpu.rob.rob_reads 129836 # The number of ROB reads 71211103SN/Asystem.cpu.rob.rob_writes 57114 # The number of ROB writes 71311103SN/Asystem.cpu.timesIdled 383 # Number of times that the entire CPU went into an idle state and unscheduled itself 71411103SN/Asystem.cpu.idleCycles 22132 # Total number of cycles that the CPU has spent unscheduled due to idling 71510220SN/Asystem.cpu.committedInsts::0 6372 # Number of Instructions Simulated 71610352SN/Asystem.cpu.committedInsts::1 6372 # Number of Instructions Simulated 71710352SN/Asystem.cpu.committedInsts::total 12744 # Number of Instructions Simulated 71810220SN/Asystem.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated 71910352SN/Asystem.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated 72010352SN/Asystem.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated 72111103SN/Asystem.cpu.cpi::0 7.794413 # CPI: Cycles Per Instruction 72211103SN/Asystem.cpu.cpi::1 7.794413 # CPI: Cycles Per Instruction 72311103SN/Asystem.cpu.cpi_total 3.897207 # CPI: Total CPI of All Threads 72411103SN/Asystem.cpu.ipc::0 0.128297 # IPC: Instructions Per Cycle 72511103SN/Asystem.cpu.ipc::1 0.128297 # IPC: Instructions Per Cycle 72611103SN/Asystem.cpu.ipc_total 0.256594 # IPC: Total IPC of All Threads 72711103SN/Asystem.cpu.int_regfile_reads 26491 # number of integer regfile reads 72811103SN/Asystem.cpu.int_regfile_writes 14992 # number of integer regfile writes 7298464SN/Asystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 7308464SN/Asystem.cpu.fp_regfile_writes 4 # number of floating regfile writes 7318464SN/Asystem.cpu.misc_regfile_reads 2 # number of misc regfile reads 7328464SN/Asystem.cpu.misc_regfile_writes 2 # number of misc regfile writes 73310628SN/Asystem.cpu.dcache.tags.replacements::0 0 # number of replacements 73410628SN/Asystem.cpu.dcache.tags.replacements::1 0 # number of replacements 73510628SN/Asystem.cpu.dcache.tags.replacements::total 0 # number of replacements 73611103SN/Asystem.cpu.dcache.tags.tagsinuse 212.222617 # Cycle average of tags in use 73711103SN/Asystem.cpu.dcache.tags.total_refs 4769 # Total number of references to valid blocks. 73811103SN/Asystem.cpu.dcache.tags.sampled_refs 344 # Sample count of references to valid blocks. 73911103SN/Asystem.cpu.dcache.tags.avg_refs 13.863372 # Average number of references to valid blocks. 74010628SN/Asystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 74111103SN/Asystem.cpu.dcache.tags.occ_blocks::cpu.data 212.222617 # Average occupied blocks per requestor 74211103SN/Asystem.cpu.dcache.tags.occ_percent::cpu.data 0.051812 # Average percentage of cache occupancy 74311103SN/Asystem.cpu.dcache.tags.occ_percent::total 0.051812 # Average percentage of cache occupancy 74411103SN/Asystem.cpu.dcache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id 74511103SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id 74611103SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 74711103SN/Asystem.cpu.dcache.tags.occ_task_id_percent::1024 0.083984 # Percentage of cache occupancy per task id 74811103SN/Asystem.cpu.dcache.tags.tag_accesses 11936 # Number of tag accesses 74911103SN/Asystem.cpu.dcache.tags.data_accesses 11936 # Number of data accesses 75011103SN/Asystem.cpu.dcache.ReadReq_hits::cpu.data 3748 # number of ReadReq hits 75111103SN/Asystem.cpu.dcache.ReadReq_hits::total 3748 # number of ReadReq hits 75211103SN/Asystem.cpu.dcache.WriteReq_hits::cpu.data 1021 # number of WriteReq hits 75311103SN/Asystem.cpu.dcache.WriteReq_hits::total 1021 # number of WriteReq hits 75411103SN/Asystem.cpu.dcache.demand_hits::cpu.data 4769 # number of demand (read+write) hits 75511103SN/Asystem.cpu.dcache.demand_hits::total 4769 # number of demand (read+write) hits 75611103SN/Asystem.cpu.dcache.overall_hits::cpu.data 4769 # number of overall hits 75711103SN/Asystem.cpu.dcache.overall_hits::total 4769 # number of overall hits 75811103SN/Asystem.cpu.dcache.ReadReq_misses::cpu.data 318 # number of ReadReq misses 75911103SN/Asystem.cpu.dcache.ReadReq_misses::total 318 # number of ReadReq misses 76011103SN/Asystem.cpu.dcache.WriteReq_misses::cpu.data 709 # number of WriteReq misses 76111103SN/Asystem.cpu.dcache.WriteReq_misses::total 709 # number of WriteReq misses 76211103SN/Asystem.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses 76311103SN/Asystem.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses 76411103SN/Asystem.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses 76511103SN/Asystem.cpu.dcache.overall_misses::total 1027 # number of overall misses 76611103SN/Asystem.cpu.dcache.ReadReq_miss_latency::cpu.data 24395500 # number of ReadReq miss cycles 76711103SN/Asystem.cpu.dcache.ReadReq_miss_latency::total 24395500 # number of ReadReq miss cycles 76811103SN/Asystem.cpu.dcache.WriteReq_miss_latency::cpu.data 50809414 # number of WriteReq miss cycles 76911103SN/Asystem.cpu.dcache.WriteReq_miss_latency::total 50809414 # number of WriteReq miss cycles 77011103SN/Asystem.cpu.dcache.demand_miss_latency::cpu.data 75204914 # number of demand (read+write) miss cycles 77111103SN/Asystem.cpu.dcache.demand_miss_latency::total 75204914 # number of demand (read+write) miss cycles 77211103SN/Asystem.cpu.dcache.overall_miss_latency::cpu.data 75204914 # number of overall miss cycles 77311103SN/Asystem.cpu.dcache.overall_miss_latency::total 75204914 # number of overall miss cycles 77411103SN/Asystem.cpu.dcache.ReadReq_accesses::cpu.data 4066 # number of ReadReq accesses(hits+misses) 77511103SN/Asystem.cpu.dcache.ReadReq_accesses::total 4066 # number of ReadReq accesses(hits+misses) 77610628SN/Asystem.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) 77710628SN/Asystem.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) 77811103SN/Asystem.cpu.dcache.demand_accesses::cpu.data 5796 # number of demand (read+write) accesses 77911103SN/Asystem.cpu.dcache.demand_accesses::total 5796 # number of demand (read+write) accesses 78011103SN/Asystem.cpu.dcache.overall_accesses::cpu.data 5796 # number of overall (read+write) accesses 78111103SN/Asystem.cpu.dcache.overall_accesses::total 5796 # number of overall (read+write) accesses 78211103SN/Asystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078210 # miss rate for ReadReq accesses 78311103SN/Asystem.cpu.dcache.ReadReq_miss_rate::total 0.078210 # miss rate for ReadReq accesses 78411103SN/Asystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409827 # miss rate for WriteReq accesses 78511103SN/Asystem.cpu.dcache.WriteReq_miss_rate::total 0.409827 # miss rate for WriteReq accesses 78611103SN/Asystem.cpu.dcache.demand_miss_rate::cpu.data 0.177191 # miss rate for demand accesses 78711103SN/Asystem.cpu.dcache.demand_miss_rate::total 0.177191 # miss rate for demand accesses 78811103SN/Asystem.cpu.dcache.overall_miss_rate::cpu.data 0.177191 # miss rate for overall accesses 78911103SN/Asystem.cpu.dcache.overall_miss_rate::total 0.177191 # miss rate for overall accesses 79011103SN/Asystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76715.408805 # average ReadReq miss latency 79111103SN/Asystem.cpu.dcache.ReadReq_avg_miss_latency::total 76715.408805 # average ReadReq miss latency 79211103SN/Asystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71663.489422 # average WriteReq miss latency 79311103SN/Asystem.cpu.dcache.WriteReq_avg_miss_latency::total 71663.489422 # average WriteReq miss latency 79411103SN/Asystem.cpu.dcache.demand_avg_miss_latency::cpu.data 73227.764362 # average overall miss latency 79511103SN/Asystem.cpu.dcache.demand_avg_miss_latency::total 73227.764362 # average overall miss latency 79611103SN/Asystem.cpu.dcache.overall_avg_miss_latency::cpu.data 73227.764362 # average overall miss latency 79711103SN/Asystem.cpu.dcache.overall_avg_miss_latency::total 73227.764362 # average overall miss latency 79811103SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 5829 # number of cycles access was blocked 79910628SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 80011103SN/Asystem.cpu.dcache.blocked::no_mshrs 135 # number of cycles access was blocked 80110628SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 80211103SN/Asystem.cpu.dcache.avg_blocked_cycles::no_mshrs 43.177778 # average number of cycles each access was blocked 80310628SN/Asystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 80410628SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 80510628SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 80611103SN/Asystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 120 # number of ReadReq MSHR hits 80711103SN/Asystem.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits 80811103SN/Asystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 563 # number of WriteReq MSHR hits 80911103SN/Asystem.cpu.dcache.WriteReq_mshr_hits::total 563 # number of WriteReq MSHR hits 81011103SN/Asystem.cpu.dcache.demand_mshr_hits::cpu.data 683 # number of demand (read+write) MSHR hits 81111103SN/Asystem.cpu.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits 81211103SN/Asystem.cpu.dcache.overall_mshr_hits::cpu.data 683 # number of overall MSHR hits 81311103SN/Asystem.cpu.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits 81411103SN/Asystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 198 # number of ReadReq MSHR misses 81511103SN/Asystem.cpu.dcache.ReadReq_mshr_misses::total 198 # number of ReadReq MSHR misses 81611103SN/Asystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses 81711103SN/Asystem.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses 81811103SN/Asystem.cpu.dcache.demand_mshr_misses::cpu.data 344 # number of demand (read+write) MSHR misses 81911103SN/Asystem.cpu.dcache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses 82011103SN/Asystem.cpu.dcache.overall_mshr_misses::cpu.data 344 # number of overall MSHR misses 82111103SN/Asystem.cpu.dcache.overall_mshr_misses::total 344 # number of overall MSHR misses 82211103SN/Asystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17299000 # number of ReadReq MSHR miss cycles 82311103SN/Asystem.cpu.dcache.ReadReq_mshr_miss_latency::total 17299000 # number of ReadReq MSHR miss cycles 82411103SN/Asystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12670989 # number of WriteReq MSHR miss cycles 82511103SN/Asystem.cpu.dcache.WriteReq_mshr_miss_latency::total 12670989 # number of WriteReq MSHR miss cycles 82611103SN/Asystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 29969989 # number of demand (read+write) MSHR miss cycles 82711103SN/Asystem.cpu.dcache.demand_mshr_miss_latency::total 29969989 # number of demand (read+write) MSHR miss cycles 82811103SN/Asystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 29969989 # number of overall MSHR miss cycles 82911103SN/Asystem.cpu.dcache.overall_mshr_miss_latency::total 29969989 # number of overall MSHR miss cycles 83011103SN/Asystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048697 # mshr miss rate for ReadReq accesses 83111103SN/Asystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048697 # mshr miss rate for ReadReq accesses 83211103SN/Asystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 83311103SN/Asystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 83411103SN/Asystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059351 # mshr miss rate for demand accesses 83511103SN/Asystem.cpu.dcache.demand_mshr_miss_rate::total 0.059351 # mshr miss rate for demand accesses 83611103SN/Asystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059351 # mshr miss rate for overall accesses 83711103SN/Asystem.cpu.dcache.overall_mshr_miss_rate::total 0.059351 # mshr miss rate for overall accesses 83811103SN/Asystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87368.686869 # average ReadReq mshr miss latency 83911103SN/Asystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87368.686869 # average ReadReq mshr miss latency 84011103SN/Asystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86787.595890 # average WriteReq mshr miss latency 84111103SN/Asystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86787.595890 # average WriteReq mshr miss latency 84211103SN/Asystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87122.061047 # average overall mshr miss latency 84311103SN/Asystem.cpu.dcache.demand_avg_mshr_miss_latency::total 87122.061047 # average overall mshr miss latency 84411103SN/Asystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87122.061047 # average overall mshr miss latency 84511103SN/Asystem.cpu.dcache.overall_avg_mshr_miss_latency::total 87122.061047 # average overall mshr miss latency 84610628SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 84710726SN/Asystem.cpu.icache.tags.replacements::0 8 # number of replacements 8489838SN/Asystem.cpu.icache.tags.replacements::1 0 # number of replacements 84910726SN/Asystem.cpu.icache.tags.replacements::total 8 # number of replacements 85011138SN/Asystem.cpu.icache.tags.tagsinuse 317.014953 # Cycle average of tags in use 85111103SN/Asystem.cpu.icache.tags.total_refs 4463 # Total number of references to valid blocks. 85211103SN/Asystem.cpu.icache.tags.sampled_refs 634 # Sample count of references to valid blocks. 85311103SN/Asystem.cpu.icache.tags.avg_refs 7.039432 # Average number of references to valid blocks. 8549838SN/Asystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 85511138SN/Asystem.cpu.icache.tags.occ_blocks::cpu.inst 317.014953 # Average occupied blocks per requestor 85611103SN/Asystem.cpu.icache.tags.occ_percent::cpu.inst 0.154792 # Average percentage of cache occupancy 85711103SN/Asystem.cpu.icache.tags.occ_percent::total 0.154792 # Average percentage of cache occupancy 85811103SN/Asystem.cpu.icache.tags.occ_task_id_blocks::1024 626 # Occupied blocks per task id 85911103SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id 86011103SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id 86111103SN/Asystem.cpu.icache.tags.occ_task_id_percent::1024 0.305664 # Percentage of cache occupancy per task id 86211103SN/Asystem.cpu.icache.tags.tag_accesses 11430 # Number of tag accesses 86311103SN/Asystem.cpu.icache.tags.data_accesses 11430 # Number of data accesses 86411103SN/Asystem.cpu.icache.ReadReq_hits::cpu.inst 4463 # number of ReadReq hits 86511103SN/Asystem.cpu.icache.ReadReq_hits::total 4463 # number of ReadReq hits 86611103SN/Asystem.cpu.icache.demand_hits::cpu.inst 4463 # number of demand (read+write) hits 86711103SN/Asystem.cpu.icache.demand_hits::total 4463 # number of demand (read+write) hits 86811103SN/Asystem.cpu.icache.overall_hits::cpu.inst 4463 # number of overall hits 86911103SN/Asystem.cpu.icache.overall_hits::total 4463 # number of overall hits 87011103SN/Asystem.cpu.icache.ReadReq_misses::cpu.inst 935 # number of ReadReq misses 87111103SN/Asystem.cpu.icache.ReadReq_misses::total 935 # number of ReadReq misses 87211103SN/Asystem.cpu.icache.demand_misses::cpu.inst 935 # number of demand (read+write) misses 87311103SN/Asystem.cpu.icache.demand_misses::total 935 # number of demand (read+write) misses 87411103SN/Asystem.cpu.icache.overall_misses::cpu.inst 935 # number of overall misses 87511103SN/Asystem.cpu.icache.overall_misses::total 935 # number of overall misses 87611138SN/Asystem.cpu.icache.ReadReq_miss_latency::cpu.inst 70147997 # number of ReadReq miss cycles 87711138SN/Asystem.cpu.icache.ReadReq_miss_latency::total 70147997 # number of ReadReq miss cycles 87811138SN/Asystem.cpu.icache.demand_miss_latency::cpu.inst 70147997 # number of demand (read+write) miss cycles 87911138SN/Asystem.cpu.icache.demand_miss_latency::total 70147997 # number of demand (read+write) miss cycles 88011138SN/Asystem.cpu.icache.overall_miss_latency::cpu.inst 70147997 # number of overall miss cycles 88111138SN/Asystem.cpu.icache.overall_miss_latency::total 70147997 # number of overall miss cycles 88211103SN/Asystem.cpu.icache.ReadReq_accesses::cpu.inst 5398 # number of ReadReq accesses(hits+misses) 88311103SN/Asystem.cpu.icache.ReadReq_accesses::total 5398 # number of ReadReq accesses(hits+misses) 88411103SN/Asystem.cpu.icache.demand_accesses::cpu.inst 5398 # number of demand (read+write) accesses 88511103SN/Asystem.cpu.icache.demand_accesses::total 5398 # number of demand (read+write) accesses 88611103SN/Asystem.cpu.icache.overall_accesses::cpu.inst 5398 # number of overall (read+write) accesses 88711103SN/Asystem.cpu.icache.overall_accesses::total 5398 # number of overall (read+write) accesses 88811103SN/Asystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.173212 # miss rate for ReadReq accesses 88911103SN/Asystem.cpu.icache.ReadReq_miss_rate::total 0.173212 # miss rate for ReadReq accesses 89011103SN/Asystem.cpu.icache.demand_miss_rate::cpu.inst 0.173212 # miss rate for demand accesses 89111103SN/Asystem.cpu.icache.demand_miss_rate::total 0.173212 # miss rate for demand accesses 89211103SN/Asystem.cpu.icache.overall_miss_rate::cpu.inst 0.173212 # miss rate for overall accesses 89311103SN/Asystem.cpu.icache.overall_miss_rate::total 0.173212 # miss rate for overall accesses 89411138SN/Asystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75024.595722 # average ReadReq miss latency 89511138SN/Asystem.cpu.icache.ReadReq_avg_miss_latency::total 75024.595722 # average ReadReq miss latency 89611138SN/Asystem.cpu.icache.demand_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency 89711138SN/Asystem.cpu.icache.demand_avg_miss_latency::total 75024.595722 # average overall miss latency 89811138SN/Asystem.cpu.icache.overall_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency 89911138SN/Asystem.cpu.icache.overall_avg_miss_latency::total 75024.595722 # average overall miss latency 90011103SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 3484 # number of cycles access was blocked 9018464SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 90211103SN/Asystem.cpu.icache.blocked::no_mshrs 77 # number of cycles access was blocked 9038464SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 90411103SN/Asystem.cpu.icache.avg_blocked_cycles::no_mshrs 45.246753 # average number of cycles each access was blocked 9058983SN/Asystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9068464SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 9078464SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 90811201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 8 # number of writebacks 90911201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 8 # number of writebacks 91011103SN/Asystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 301 # number of ReadReq MSHR hits 91111103SN/Asystem.cpu.icache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits 91211103SN/Asystem.cpu.icache.demand_mshr_hits::cpu.inst 301 # number of demand (read+write) MSHR hits 91311103SN/Asystem.cpu.icache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits 91411103SN/Asystem.cpu.icache.overall_mshr_hits::cpu.inst 301 # number of overall MSHR hits 91511103SN/Asystem.cpu.icache.overall_mshr_hits::total 301 # number of overall MSHR hits 91611103SN/Asystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 634 # number of ReadReq MSHR misses 91711103SN/Asystem.cpu.icache.ReadReq_mshr_misses::total 634 # number of ReadReq MSHR misses 91811103SN/Asystem.cpu.icache.demand_mshr_misses::cpu.inst 634 # number of demand (read+write) MSHR misses 91911103SN/Asystem.cpu.icache.demand_mshr_misses::total 634 # number of demand (read+write) MSHR misses 92011103SN/Asystem.cpu.icache.overall_mshr_misses::cpu.inst 634 # number of overall MSHR misses 92111103SN/Asystem.cpu.icache.overall_mshr_misses::total 634 # number of overall MSHR misses 92211138SN/Asystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51561499 # number of ReadReq MSHR miss cycles 92311138SN/Asystem.cpu.icache.ReadReq_mshr_miss_latency::total 51561499 # number of ReadReq MSHR miss cycles 92411138SN/Asystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 51561499 # number of demand (read+write) MSHR miss cycles 92511138SN/Asystem.cpu.icache.demand_mshr_miss_latency::total 51561499 # number of demand (read+write) MSHR miss cycles 92611138SN/Asystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 51561499 # number of overall MSHR miss cycles 92711138SN/Asystem.cpu.icache.overall_mshr_miss_latency::total 51561499 # number of overall MSHR miss cycles 92811103SN/Asystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for ReadReq accesses 92911103SN/Asystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.117451 # mshr miss rate for ReadReq accesses 93011103SN/Asystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for demand accesses 93111103SN/Asystem.cpu.icache.demand_mshr_miss_rate::total 0.117451 # mshr miss rate for demand accesses 93211103SN/Asystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for overall accesses 93311103SN/Asystem.cpu.icache.overall_mshr_miss_rate::total 0.117451 # mshr miss rate for overall accesses 93411138SN/Asystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81327.285489 # average ReadReq mshr miss latency 93511138SN/Asystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81327.285489 # average ReadReq mshr miss latency 93611138SN/Asystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81327.285489 # average overall mshr miss latency 93711138SN/Asystem.cpu.icache.demand_avg_mshr_miss_latency::total 81327.285489 # average overall mshr miss latency 93811138SN/Asystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81327.285489 # average overall mshr miss latency 93911138SN/Asystem.cpu.icache.overall_avg_mshr_miss_latency::total 81327.285489 # average overall mshr miss latency 9408464SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 9419838SN/Asystem.cpu.l2cache.tags.replacements::0 0 # number of replacements 9429838SN/Asystem.cpu.l2cache.tags.replacements::1 0 # number of replacements 9439838SN/Asystem.cpu.l2cache.tags.replacements::total 0 # number of replacements 94411103SN/Asystem.cpu.l2cache.tags.tagsinuse 436.545027 # Cycle average of tags in use 94510892SN/Asystem.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. 94611103SN/Asystem.cpu.l2cache.tags.sampled_refs 830 # Sample count of references to valid blocks. 94711103SN/Asystem.cpu.l2cache.tags.avg_refs 0.012048 # Average number of references to valid blocks. 9489838SN/Asystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 94911103SN/Asystem.cpu.l2cache.tags.occ_blocks::cpu.inst 317.712929 # Average occupied blocks per requestor 95011103SN/Asystem.cpu.l2cache.tags.occ_blocks::cpu.data 118.832098 # Average occupied blocks per requestor 95111103SN/Asystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.009696 # Average percentage of cache occupancy 95211103SN/Asystem.cpu.l2cache.tags.occ_percent::cpu.data 0.003626 # Average percentage of cache occupancy 95311103SN/Asystem.cpu.l2cache.tags.occ_percent::total 0.013322 # Average percentage of cache occupancy 95411103SN/Asystem.cpu.l2cache.tags.occ_task_id_blocks::1024 830 # Occupied blocks per task id 95511103SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 326 # Occupied blocks per task id 95611103SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 504 # Occupied blocks per task id 95711103SN/Asystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.025330 # Percentage of cache occupancy per task id 95811103SN/Asystem.cpu.l2cache.tags.tag_accesses 8864 # Number of tag accesses 95911103SN/Asystem.cpu.l2cache.tags.data_accesses 8864 # Number of data accesses 96011201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 8 # number of WritebackClean hits 96111201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 8 # number of WritebackClean hits 96210892SN/Asystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 96310892SN/Asystem.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 9649490SN/Asystem.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 9659490SN/Asystem.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 9669490SN/Asystem.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 9679490SN/Asystem.cpu.l2cache.overall_hits::total 2 # number of overall hits 96811103SN/Asystem.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses 96911103SN/Asystem.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses 97011103SN/Asystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 632 # number of ReadCleanReq misses 97111103SN/Asystem.cpu.l2cache.ReadCleanReq_misses::total 632 # number of ReadCleanReq misses 97211103SN/Asystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 198 # number of ReadSharedReq misses 97311103SN/Asystem.cpu.l2cache.ReadSharedReq_misses::total 198 # number of ReadSharedReq misses 97411103SN/Asystem.cpu.l2cache.demand_misses::cpu.inst 632 # number of demand (read+write) misses 97511103SN/Asystem.cpu.l2cache.demand_misses::cpu.data 344 # number of demand (read+write) misses 97611103SN/Asystem.cpu.l2cache.demand_misses::total 976 # number of demand (read+write) misses 97711103SN/Asystem.cpu.l2cache.overall_misses::cpu.inst 632 # number of overall misses 97811103SN/Asystem.cpu.l2cache.overall_misses::cpu.data 344 # number of overall misses 97911103SN/Asystem.cpu.l2cache.overall_misses::total 976 # number of overall misses 98011103SN/Asystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12444500 # number of ReadExReq miss cycles 98111103SN/Asystem.cpu.l2cache.ReadExReq_miss_latency::total 12444500 # number of ReadExReq miss cycles 98211103SN/Asystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 50583000 # number of ReadCleanReq miss cycles 98311103SN/Asystem.cpu.l2cache.ReadCleanReq_miss_latency::total 50583000 # number of ReadCleanReq miss cycles 98411103SN/Asystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16994000 # number of ReadSharedReq miss cycles 98511103SN/Asystem.cpu.l2cache.ReadSharedReq_miss_latency::total 16994000 # number of ReadSharedReq miss cycles 98611103SN/Asystem.cpu.l2cache.demand_miss_latency::cpu.inst 50583000 # number of demand (read+write) miss cycles 98711103SN/Asystem.cpu.l2cache.demand_miss_latency::cpu.data 29438500 # number of demand (read+write) miss cycles 98811103SN/Asystem.cpu.l2cache.demand_miss_latency::total 80021500 # number of demand (read+write) miss cycles 98911103SN/Asystem.cpu.l2cache.overall_miss_latency::cpu.inst 50583000 # number of overall miss cycles 99011103SN/Asystem.cpu.l2cache.overall_miss_latency::cpu.data 29438500 # number of overall miss cycles 99111103SN/Asystem.cpu.l2cache.overall_miss_latency::total 80021500 # number of overall miss cycles 99211201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 8 # number of WritebackClean accesses(hits+misses) 99311201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 8 # number of WritebackClean accesses(hits+misses) 99411103SN/Asystem.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) 99511103SN/Asystem.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) 99611103SN/Asystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 634 # number of ReadCleanReq accesses(hits+misses) 99711103SN/Asystem.cpu.l2cache.ReadCleanReq_accesses::total 634 # number of ReadCleanReq accesses(hits+misses) 99811103SN/Asystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 198 # number of ReadSharedReq accesses(hits+misses) 99911103SN/Asystem.cpu.l2cache.ReadSharedReq_accesses::total 198 # number of ReadSharedReq accesses(hits+misses) 100011103SN/Asystem.cpu.l2cache.demand_accesses::cpu.inst 634 # number of demand (read+write) accesses 100111103SN/Asystem.cpu.l2cache.demand_accesses::cpu.data 344 # number of demand (read+write) accesses 100211103SN/Asystem.cpu.l2cache.demand_accesses::total 978 # number of demand (read+write) accesses 100311103SN/Asystem.cpu.l2cache.overall_accesses::cpu.inst 634 # number of overall (read+write) accesses 100411103SN/Asystem.cpu.l2cache.overall_accesses::cpu.data 344 # number of overall (read+write) accesses 100511103SN/Asystem.cpu.l2cache.overall_accesses::total 978 # number of overall (read+write) accesses 10068835SN/Asystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 10079055SN/Asystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 100811103SN/Asystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996845 # miss rate for ReadCleanReq accesses 100911103SN/Asystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996845 # miss rate for ReadCleanReq accesses 101010892SN/Asystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 101110892SN/Asystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 101211103SN/Asystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996845 # miss rate for demand accesses 10138835SN/Asystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 101411103SN/Asystem.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses 101511103SN/Asystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996845 # miss rate for overall accesses 10168835SN/Asystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 101711103SN/Asystem.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses 101811103SN/Asystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85236.301370 # average ReadExReq miss latency 101911103SN/Asystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 85236.301370 # average ReadExReq miss latency 102011103SN/Asystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80036.392405 # average ReadCleanReq miss latency 102111103SN/Asystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80036.392405 # average ReadCleanReq miss latency 102211103SN/Asystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85828.282828 # average ReadSharedReq miss latency 102311103SN/Asystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85828.282828 # average ReadSharedReq miss latency 102411103SN/Asystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80036.392405 # average overall miss latency 102511103SN/Asystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 85577.034884 # average overall miss latency 102611103SN/Asystem.cpu.l2cache.demand_avg_miss_latency::total 81989.241803 # average overall miss latency 102711103SN/Asystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80036.392405 # average overall miss latency 102811103SN/Asystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 85577.034884 # average overall miss latency 102911103SN/Asystem.cpu.l2cache.overall_avg_miss_latency::total 81989.241803 # average overall miss latency 10309322SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 10318464SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 10329322SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 10336127SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 10349322SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 10358983SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 10368464SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 10373147SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 103811103SN/Asystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses 103911103SN/Asystem.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses 104011103SN/Asystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 632 # number of ReadCleanReq MSHR misses 104111103SN/Asystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 632 # number of ReadCleanReq MSHR misses 104211103SN/Asystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 198 # number of ReadSharedReq MSHR misses 104311103SN/Asystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 198 # number of ReadSharedReq MSHR misses 104411103SN/Asystem.cpu.l2cache.demand_mshr_misses::cpu.inst 632 # number of demand (read+write) MSHR misses 104511103SN/Asystem.cpu.l2cache.demand_mshr_misses::cpu.data 344 # number of demand (read+write) MSHR misses 104611103SN/Asystem.cpu.l2cache.demand_mshr_misses::total 976 # number of demand (read+write) MSHR misses 104711103SN/Asystem.cpu.l2cache.overall_mshr_misses::cpu.inst 632 # number of overall MSHR misses 104811103SN/Asystem.cpu.l2cache.overall_mshr_misses::cpu.data 344 # number of overall MSHR misses 104911103SN/Asystem.cpu.l2cache.overall_mshr_misses::total 976 # number of overall MSHR misses 105011103SN/Asystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10984500 # number of ReadExReq MSHR miss cycles 105111103SN/Asystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10984500 # number of ReadExReq MSHR miss cycles 105211103SN/Asystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44263000 # number of ReadCleanReq MSHR miss cycles 105311103SN/Asystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44263000 # number of ReadCleanReq MSHR miss cycles 105411103SN/Asystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15014000 # number of ReadSharedReq MSHR miss cycles 105511103SN/Asystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15014000 # number of ReadSharedReq MSHR miss cycles 105611103SN/Asystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44263000 # number of demand (read+write) MSHR miss cycles 105711103SN/Asystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25998500 # number of demand (read+write) MSHR miss cycles 105811103SN/Asystem.cpu.l2cache.demand_mshr_miss_latency::total 70261500 # number of demand (read+write) MSHR miss cycles 105911103SN/Asystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44263000 # number of overall MSHR miss cycles 106011103SN/Asystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25998500 # number of overall MSHR miss cycles 106111103SN/Asystem.cpu.l2cache.overall_mshr_miss_latency::total 70261500 # number of overall MSHR miss cycles 10628835SN/Asystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 10639055SN/Asystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 106411103SN/Asystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for ReadCleanReq accesses 106511103SN/Asystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996845 # mshr miss rate for ReadCleanReq accesses 106610892SN/Asystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 106710892SN/Asystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 106811103SN/Asystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for demand accesses 10698835SN/Asystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 107011103SN/Asystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses 107111103SN/Asystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for overall accesses 10728835SN/Asystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 107311103SN/Asystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses 107411103SN/Asystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75236.301370 # average ReadExReq mshr miss latency 107511103SN/Asystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75236.301370 # average ReadExReq mshr miss latency 107611103SN/Asystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70036.392405 # average ReadCleanReq mshr miss latency 107711103SN/Asystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70036.392405 # average ReadCleanReq mshr miss latency 107811103SN/Asystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75828.282828 # average ReadSharedReq mshr miss latency 107911103SN/Asystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75828.282828 # average ReadSharedReq mshr miss latency 108011103SN/Asystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70036.392405 # average overall mshr miss latency 108111103SN/Asystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75577.034884 # average overall mshr miss latency 108211103SN/Asystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 71989.241803 # average overall mshr miss latency 108311103SN/Asystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70036.392405 # average overall mshr miss latency 108411103SN/Asystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75577.034884 # average overall mshr miss latency 108511103SN/Asystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 71989.241803 # average overall mshr miss latency 10868464SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 108711138SN/Asystem.cpu.toL2Bus.snoop_filter.tot_requests 986 # Total number of requests made to the snoop filter. 108811138SN/Asystem.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. 108911138SN/Asystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 109011138SN/Asystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 109111138SN/Asystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 109211138SN/Asystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 109311103SN/Asystem.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution 109411201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 8 # Transaction distribution 109511103SN/Asystem.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution 109611103SN/Asystem.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution 109711103SN/Asystem.cpu.toL2Bus.trans_dist::ReadCleanReq 634 # Transaction distribution 109811103SN/Asystem.cpu.toL2Bus.trans_dist::ReadSharedReq 198 # Transaction distribution 109911103SN/Asystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) 110011103SN/Asystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes) 110111103SN/Asystem.cpu.toL2Bus.pkt_count::total 1964 # Packet count per connected master and slave (bytes) 110211201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41088 # Cumulative packet size per connected master and slave (bytes) 110311103SN/Asystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22016 # Cumulative packet size per connected master and slave (bytes) 110411201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 63104 # Cumulative packet size per connected master and slave (bytes) 110510628SN/Asystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 110611201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 978 # Request fanout histogram 110711201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.002045 # Request fanout histogram 110811201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.045198 # Request fanout histogram 110910628SN/Asystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 111011201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 976 99.80% 99.80% # Request fanout histogram 111111138SN/Asystem.cpu.toL2Bus.snoop_fanout::1 2 0.20% 100.00% # Request fanout histogram 111210628SN/Asystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 111310628SN/Asystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 111411138SN/Asystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 111510628SN/Asystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 111611201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 978 # Request fanout histogram 111711201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 501000 # Layer occupancy (ticks) 111810892SN/Asystem.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) 111911103SN/Asystem.cpu.toL2Bus.respLayer0.occupancy 951000 # Layer occupancy (ticks) 112011103SN/Asystem.cpu.toL2Bus.respLayer0.utilization 3.8 # Layer utilization (%) 112111103SN/Asystem.cpu.toL2Bus.respLayer1.occupancy 516000 # Layer occupancy (ticks) 112210892SN/Asystem.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) 112311103SN/Asystem.membus.trans_dist::ReadResp 830 # Transaction distribution 112411103SN/Asystem.membus.trans_dist::ReadExReq 146 # Transaction distribution 112511103SN/Asystem.membus.trans_dist::ReadExResp 146 # Transaction distribution 112611103SN/Asystem.membus.trans_dist::ReadSharedReq 830 # Transaction distribution 112711103SN/Asystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1952 # Packet count per connected master and slave (bytes) 112811103SN/Asystem.membus.pkt_count::total 1952 # Packet count per connected master and slave (bytes) 112911103SN/Asystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62464 # Cumulative packet size per connected master and slave (bytes) 113011103SN/Asystem.membus.pkt_size::total 62464 # Cumulative packet size per connected master and slave (bytes) 113110628SN/Asystem.membus.snoops 0 # Total snoops (count) 113211103SN/Asystem.membus.snoop_fanout::samples 976 # Request fanout histogram 113310628SN/Asystem.membus.snoop_fanout::mean 0 # Request fanout histogram 113410628SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 113510628SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 113611103SN/Asystem.membus.snoop_fanout::0 976 100.00% 100.00% # Request fanout histogram 113710628SN/Asystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 113810628SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 113910628SN/Asystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 114010628SN/Asystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 114111103SN/Asystem.membus.snoop_fanout::total 976 # Request fanout histogram 114211103SN/Asystem.membus.reqLayer0.occupancy 1189000 # Layer occupancy (ticks) 114310726SN/Asystem.membus.reqLayer0.utilization 4.8 # Layer utilization (%) 114411103SN/Asystem.membus.respLayer1.occupancy 5195000 # Layer occupancy (ticks) 114511103SN/Asystem.membus.respLayer1.utilization 20.9 # Layer utilization (%) 11463142SN/A 11473142SN/A---------- End Simulation Statistics ---------- 1148