stats.txt revision 10352
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000023 # Number of seconds simulated 4sim_ticks 23170000 # Number of ticks simulated 5final_tick 23170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 44420 # Simulator instruction rate (inst/s) 8host_op_rate 44416 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 80747825 # Simulator tick rate (ticks/s) 10host_mem_usage 237048 # Number of bytes of host memory used 11host_seconds 0.29 # Real time elapsed on the host 12sim_insts 12744 # Number of instructions simulated 13sim_ops 12744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 40384 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 22272 # Number of bytes read from this memory 18system.physmem.bytes_read::total 62656 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 40384 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 40384 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 631 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 348 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 979 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1742943461 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 961242987 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2704186448 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1742943461 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1742943461 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1742943461 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 961242987 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2704186448 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 979 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 979 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 62656 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 62656 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 84 # Per bank write bursts 45system.physmem.perBankRdBursts::1 151 # Per bank write bursts 46system.physmem.perBankRdBursts::2 78 # Per bank write bursts 47system.physmem.perBankRdBursts::3 58 # Per bank write bursts 48system.physmem.perBankRdBursts::4 88 # Per bank write bursts 49system.physmem.perBankRdBursts::5 48 # Per bank write bursts 50system.physmem.perBankRdBursts::6 33 # Per bank write bursts 51system.physmem.perBankRdBursts::7 51 # Per bank write bursts 52system.physmem.perBankRdBursts::8 42 # Per bank write bursts 53system.physmem.perBankRdBursts::9 39 # Per bank write bursts 54system.physmem.perBankRdBursts::10 31 # Per bank write bursts 55system.physmem.perBankRdBursts::11 34 # Per bank write bursts 56system.physmem.perBankRdBursts::12 15 # Per bank write bursts 57system.physmem.perBankRdBursts::13 120 # Per bank write bursts 58system.physmem.perBankRdBursts::14 70 # Per bank write bursts 59system.physmem.perBankRdBursts::15 37 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 23015000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 979 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 351 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 324 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 193 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 75 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 196 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 289.959184 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 186.164854 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 288.512504 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 61 31.12% 31.12% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 60 30.61% 61.73% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 22 11.22% 72.96% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 9 4.59% 77.55% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 16 8.16% 85.71% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 6 3.06% 88.78% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 5 2.55% 91.33% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 4 2.04% 93.37% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 13 6.63% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 196 # Bytes accessed per row activation 203system.physmem.totQLat 11386250 # Total ticks spent queuing 204system.physmem.totMemAccLat 29742500 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 4895000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 11630.49 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 30380.49 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 2704.19 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 2704.19 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 21.13 # Data bus utilization in percentage 215system.physmem.busUtilRead 21.13 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 2.40 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 767 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 78.35 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 23508.68 # Average gap between requests 224system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 25750 # Time in different power states 226system.physmem.memoryStateTime::REF 520000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 15300500 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.membus.throughput 2704186448 # Throughput (bytes/s) 231system.membus.trans_dist::ReadReq 833 # Transaction distribution 232system.membus.trans_dist::ReadResp 833 # Transaction distribution 233system.membus.trans_dist::ReadExReq 146 # Transaction distribution 234system.membus.trans_dist::ReadExResp 146 # Transaction distribution 235system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1958 # Packet count per connected master and slave (bytes) 236system.membus.pkt_count::total 1958 # Packet count per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62656 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 62656 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 62656 # Total data (bytes) 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 241system.membus.reqLayer0.occupancy 1208500 # Layer occupancy (ticks) 242system.membus.reqLayer0.utilization 5.2 # Layer utilization (%) 243system.membus.respLayer1.occupancy 9081250 # Layer occupancy (ticks) 244system.membus.respLayer1.utilization 39.2 # Layer utilization (%) 245system.cpu_clk_domain.clock 500 # Clock period in ticks 246system.cpu.branchPred.lookups 7166 # Number of BP lookups 247system.cpu.branchPred.condPredicted 4000 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 1467 # Number of conditional branches incorrect 249system.cpu.branchPred.BTBLookups 5305 # Number of BTB lookups 250system.cpu.branchPred.BTBHits 908 # Number of BTB hits 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 252system.cpu.branchPred.BTBHitPct 17.115928 # BTB Hit Percentage 253system.cpu.branchPred.usedRAS 981 # Number of times the RAS was used to get a target. 254system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. 255system.cpu.dtb.fetch_hits 0 # ITB hits 256system.cpu.dtb.fetch_misses 0 # ITB misses 257system.cpu.dtb.fetch_acv 0 # ITB acv 258system.cpu.dtb.fetch_accesses 0 # ITB accesses 259system.cpu.dtb.read_hits 4855 # DTB read hits 260system.cpu.dtb.read_misses 98 # DTB read misses 261system.cpu.dtb.read_acv 0 # DTB read access violations 262system.cpu.dtb.read_accesses 4953 # DTB read accesses 263system.cpu.dtb.write_hits 2092 # DTB write hits 264system.cpu.dtb.write_misses 62 # DTB write misses 265system.cpu.dtb.write_acv 0 # DTB write access violations 266system.cpu.dtb.write_accesses 2154 # DTB write accesses 267system.cpu.dtb.data_hits 6947 # DTB hits 268system.cpu.dtb.data_misses 160 # DTB misses 269system.cpu.dtb.data_acv 0 # DTB access violations 270system.cpu.dtb.data_accesses 7107 # DTB accesses 271system.cpu.itb.fetch_hits 5289 # ITB hits 272system.cpu.itb.fetch_misses 59 # ITB misses 273system.cpu.itb.fetch_acv 0 # ITB acv 274system.cpu.itb.fetch_accesses 5348 # ITB accesses 275system.cpu.itb.read_hits 0 # DTB read hits 276system.cpu.itb.read_misses 0 # DTB read misses 277system.cpu.itb.read_acv 0 # DTB read access violations 278system.cpu.itb.read_accesses 0 # DTB read accesses 279system.cpu.itb.write_hits 0 # DTB write hits 280system.cpu.itb.write_misses 0 # DTB write misses 281system.cpu.itb.write_acv 0 # DTB write access violations 282system.cpu.itb.write_accesses 0 # DTB write accesses 283system.cpu.itb.data_hits 0 # DTB hits 284system.cpu.itb.data_misses 0 # DTB misses 285system.cpu.itb.data_acv 0 # DTB access violations 286system.cpu.itb.data_accesses 0 # DTB accesses 287system.cpu.workload0.num_syscalls 17 # Number of system calls 288system.cpu.workload1.num_syscalls 17 # Number of system calls 289system.cpu.numCycles 46341 # number of cpu cycles simulated 290system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 291system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 292system.cpu.fetch.icacheStallCycles 1308 # Number of cycles fetch is stalled on an Icache miss 293system.cpu.fetch.Insts 39806 # Number of instructions fetch has processed 294system.cpu.fetch.Branches 7166 # Number of branches that fetch encountered 295system.cpu.fetch.predictedBranches 1889 # Number of branches that fetch has predicted taken 296system.cpu.fetch.Cycles 11048 # Number of cycles fetch has run and was not squashing or blocked 297system.cpu.fetch.SquashCycles 1548 # Number of cycles fetch has spent squashing 298system.cpu.fetch.MiscStallCycles 233 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 299system.cpu.fetch.CacheLines 5289 # Number of cache lines fetched 300system.cpu.fetch.IcacheSquashes 806 # Number of outstanding Icache misses that were squashed 301system.cpu.fetch.rateDist::samples 28474 # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::mean 1.397977 # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::stdev 2.796585 # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::0 21786 76.51% 76.51% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::1 553 1.94% 78.45% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::2 412 1.45% 79.90% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::3 526 1.85% 81.75% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::4 512 1.80% 83.55% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::5 421 1.48% 85.02% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::6 497 1.75% 86.77% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::7 420 1.48% 88.25% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::8 3347 11.75% 100.00% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::total 28474 # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.branchRate 0.154636 # Number of branch fetches per cycle 319system.cpu.fetch.rate 0.858980 # Number of inst fetches per cycle 320system.cpu.decode.IdleCycles 37975 # Number of cycles decode is idle 321system.cpu.decode.BlockedCycles 11845 # Number of cycles decode is blocked 322system.cpu.decode.RunCycles 5079 # Number of cycles decode is running 323system.cpu.decode.UnblockCycles 648 # Number of cycles decode is unblocking 324system.cpu.decode.SquashCycles 1147 # Number of cycles decode is squashing 325system.cpu.decode.BranchResolved 634 # Number of times decode resolved a branch 326system.cpu.decode.BranchMispred 427 # Number of times decode detected a branch misprediction 327system.cpu.decode.DecodedInsts 32375 # Number of instructions handled by decode 328system.cpu.decode.SquashedInsts 893 # Number of squashed instructions handled by decode 329system.cpu.rename.SquashCycles 1147 # Number of cycles rename is squashing 330system.cpu.rename.IdleCycles 38612 # Number of cycles rename is idle 331system.cpu.rename.BlockCycles 4919 # Number of cycles rename is blocking 332system.cpu.rename.serializeStallCycles 1229 # count of cycles rename stalled for serializing inst 333system.cpu.rename.RunCycles 5110 # Number of cycles rename is running 334system.cpu.rename.UnblockCycles 5677 # Number of cycles rename is unblocking 335system.cpu.rename.RenamedInsts 30348 # Number of instructions processed by rename 336system.cpu.rename.ROBFullEvents 40 # Number of times rename has blocked due to ROB full 337system.cpu.rename.IQFullEvents 343 # Number of times rename has blocked due to IQ full 338system.cpu.rename.LQFullEvents 655 # Number of times rename has blocked due to LQ full 339system.cpu.rename.SQFullEvents 4509 # Number of times rename has blocked due to SQ full 340system.cpu.rename.RenamedOperands 22899 # Number of destination operands rename has renamed 341system.cpu.rename.RenameLookups 37890 # Number of register rename lookups that rename has made 342system.cpu.rename.int_rename_lookups 37872 # Number of integer rename lookups 343system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 344system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed 345system.cpu.rename.UndoneMaps 13759 # Number of HB maps that are undone due to squashing 346system.cpu.rename.serializingInsts 60 # count of serializing insts renamed 347system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed 348system.cpu.rename.skidInsts 2110 # count of insts added to the skid buffer 349system.cpu.memDep0.insertedLoads 2877 # Number of loads inserted to the mem dependence unit. 350system.cpu.memDep0.insertedStores 1488 # Number of stores inserted to the mem dependence unit. 351system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads. 352system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. 353system.cpu.memDep1.insertedLoads 2903 # Number of loads inserted to the mem dependence unit. 354system.cpu.memDep1.insertedStores 1354 # Number of stores inserted to the mem dependence unit. 355system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads. 356system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. 357system.cpu.iq.iqInstsAdded 27058 # Number of instructions added to the IQ (excludes non-spec) 358system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ 359system.cpu.iq.iqInstsIssued 22518 # Number of instructions issued 360system.cpu.iq.iqSquashedInstsIssued 66 # Number of squashed instructions issued 361system.cpu.iq.iqSquashedInstsExamined 13496 # Number of squashed instructions iterated over during squash; mainly for profiling 362system.cpu.iq.iqSquashedOperandsExamined 7946 # Number of squashed operands that are examined and possibly removed from graph 363system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed 364system.cpu.iq.issued_per_cycle::samples 28474 # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::mean 0.790827 # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::stdev 1.507053 # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::0 20065 70.47% 70.47% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::1 2633 9.25% 79.71% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::2 1896 6.66% 86.37% # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::3 1407 4.94% 91.31% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::4 1291 4.53% 95.85% # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::5 643 2.26% 98.11% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::6 327 1.15% 99.26% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::7 165 0.58% 99.83% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::8 47 0.17% 100.00% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::total 28474 # Number of insts issued each cycle 381system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 382system.cpu.iq.fu_full::IntAlu 21 6.95% 6.95% # attempts to use FU when none available 383system.cpu.iq.fu_full::IntMult 0 0.00% 6.95% # attempts to use FU when none available 384system.cpu.iq.fu_full::IntDiv 0 0.00% 6.95% # attempts to use FU when none available 385system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.95% # attempts to use FU when none available 386system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.95% # attempts to use FU when none available 387system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.95% # attempts to use FU when none available 388system.cpu.iq.fu_full::FloatMult 0 0.00% 6.95% # attempts to use FU when none available 389system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.95% # attempts to use FU when none available 390system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.95% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.95% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.95% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.95% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.95% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.95% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.95% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdMult 0 0.00% 6.95% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.95% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdShift 0 0.00% 6.95% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.95% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.95% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.95% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.95% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.95% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.95% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.95% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.95% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.95% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.95% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.95% # attempts to use FU when none available 411system.cpu.iq.fu_full::MemRead 199 65.89% 72.85% # attempts to use FU when none available 412system.cpu.iq.fu_full::MemWrite 82 27.15% 100.00% # attempts to use FU when none available 413system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 414system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 415system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 416system.cpu.iq.FU_type_0::IntAlu 7409 65.93% 65.95% # Type of FU issued 417system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.95% # Type of FU issued 418system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.95% # Type of FU issued 419system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.97% # Type of FU issued 420system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.97% # Type of FU issued 421system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.97% # Type of FU issued 422system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.97% # Type of FU issued 423system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.97% # Type of FU issued 424system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.97% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.97% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.97% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.97% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.97% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.97% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.97% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.97% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.97% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.97% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.97% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.97% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.97% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.97% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.97% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.97% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.97% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.97% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.97% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.97% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.97% # Type of FU issued 445system.cpu.iq.FU_type_0::MemRead 2656 23.63% 89.61% # Type of FU issued 446system.cpu.iq.FU_type_0::MemWrite 1168 10.39% 100.00% # Type of FU issued 447system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 448system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 449system.cpu.iq.FU_type_0::total 11238 # Type of FU issued 450system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued 451system.cpu.iq.FU_type_1::IntAlu 7461 66.14% 66.16% # Type of FU issued 452system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.17% # Type of FU issued 453system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.17% # Type of FU issued 454system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.19% # Type of FU issued 455system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.19% # Type of FU issued 456system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.19% # Type of FU issued 457system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.19% # Type of FU issued 458system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.19% # Type of FU issued 459system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.19% # Type of FU issued 460system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.19% # Type of FU issued 461system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.19% # Type of FU issued 462system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.19% # Type of FU issued 463system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.19% # Type of FU issued 464system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.19% # Type of FU issued 465system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.19% # Type of FU issued 466system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.19% # Type of FU issued 467system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.19% # Type of FU issued 468system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.19% # Type of FU issued 469system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.19% # Type of FU issued 470system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.19% # Type of FU issued 471system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.19% # Type of FU issued 472system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.19% # Type of FU issued 473system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.19% # Type of FU issued 474system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.19% # Type of FU issued 475system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.19% # Type of FU issued 476system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.19% # Type of FU issued 477system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.19% # Type of FU issued 478system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued 479system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued 480system.cpu.iq.FU_type_1::MemRead 2675 23.71% 89.90% # Type of FU issued 481system.cpu.iq.FU_type_1::MemWrite 1139 10.10% 100.00% # Type of FU issued 482system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 483system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued 484system.cpu.iq.FU_type_1::total 11280 # Type of FU issued 485system.cpu.iq.FU_type::total 22518 0.00% 0.00% # Type of FU issued 486system.cpu.iq.rate 0.485920 # Inst issue rate 487system.cpu.iq.fu_busy_cnt::0 151 # FU busy when requested 488system.cpu.iq.fu_busy_cnt::1 151 # FU busy when requested 489system.cpu.iq.fu_busy_cnt::total 302 # FU busy when requested 490system.cpu.iq.fu_busy_rate::0 0.006706 # FU busy rate (busy events/executed inst) 491system.cpu.iq.fu_busy_rate::1 0.006706 # FU busy rate (busy events/executed inst) 492system.cpu.iq.fu_busy_rate::total 0.013411 # FU busy rate (busy events/executed inst) 493system.cpu.iq.int_inst_queue_reads 73836 # Number of integer instruction queue reads 494system.cpu.iq.int_inst_queue_writes 40624 # Number of integer instruction queue writes 495system.cpu.iq.int_inst_queue_wakeup_accesses 19843 # Number of integer instruction queue wakeup accesses 496system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads 497system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 498system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses 499system.cpu.iq.int_alu_accesses 22794 # Number of integer alu accesses 500system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses 501system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores 502system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 503system.cpu.iew.lsq.thread0.squashedLoads 1694 # Number of loads squashed 504system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 505system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations 506system.cpu.iew.lsq.thread0.squashedStores 623 # Number of stores squashed 507system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 508system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 509system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 510system.cpu.iew.lsq.thread0.cacheBlocked 321 # Number of times an access to memory failed due to the cache being blocked 511system.cpu.iew.lsq.thread1.forwLoads 81 # Number of loads that had data forwarded from stores 512system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address 513system.cpu.iew.lsq.thread1.squashedLoads 1720 # Number of loads squashed 514system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 515system.cpu.iew.lsq.thread1.memOrderViolation 21 # Number of memory ordering violations 516system.cpu.iew.lsq.thread1.squashedStores 489 # Number of stores squashed 517system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 518system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 519system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled 520system.cpu.iew.lsq.thread1.cacheBlocked 265 # Number of times an access to memory failed due to the cache being blocked 521system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 522system.cpu.iew.iewSquashCycles 1147 # Number of cycles IEW is squashing 523system.cpu.iew.iewBlockCycles 2751 # Number of cycles IEW is blocking 524system.cpu.iew.iewUnblockCycles 416 # Number of cycles IEW is unblocking 525system.cpu.iew.iewDispatchedInsts 27257 # Number of instructions dispatched to IQ 526system.cpu.iew.iewDispSquashedInsts 298 # Number of squashed instructions skipped by dispatch 527system.cpu.iew.iewDispLoadInsts 5780 # Number of dispatched load instructions 528system.cpu.iew.iewDispStoreInsts 2842 # Number of dispatched store instructions 529system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions 530system.cpu.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall 531system.cpu.iew.iewLSQFullEvents 391 # Number of times the LSQ has become full, causing a stall 532system.cpu.iew.memOrderViolationEvents 39 # Number of memory order violations 533system.cpu.iew.predictedTakenIncorrect 140 # Number of branches that were predicted taken incorrectly 534system.cpu.iew.predictedNotTakenIncorrect 1160 # Number of branches that were predicted not taken incorrectly 535system.cpu.iew.branchMispredicts 1300 # Number of branch mispredicts detected at execute 536system.cpu.iew.iewExecutedInsts 21263 # Number of executed instructions 537system.cpu.iew.iewExecLoadInsts::0 2485 # Number of load instructions executed 538system.cpu.iew.iewExecLoadInsts::1 2477 # Number of load instructions executed 539system.cpu.iew.iewExecLoadInsts::total 4962 # Number of load instructions executed 540system.cpu.iew.iewExecSquashedInsts 1255 # Number of squashed instructions skipped in execute 541system.cpu.iew.exec_swp::0 0 # number of swp insts executed 542system.cpu.iew.exec_swp::1 0 # number of swp insts executed 543system.cpu.iew.exec_swp::total 0 # number of swp insts executed 544system.cpu.iew.exec_nop::0 73 # number of nop insts executed 545system.cpu.iew.exec_nop::1 73 # number of nop insts executed 546system.cpu.iew.exec_nop::total 146 # number of nop insts executed 547system.cpu.iew.exec_refs::0 3579 # number of memory reference insts executed 548system.cpu.iew.exec_refs::1 3558 # number of memory reference insts executed 549system.cpu.iew.exec_refs::total 7137 # number of memory reference insts executed 550system.cpu.iew.exec_branches::0 1685 # Number of branches executed 551system.cpu.iew.exec_branches::1 1728 # Number of branches executed 552system.cpu.iew.exec_branches::total 3413 # Number of branches executed 553system.cpu.iew.exec_stores::0 1094 # Number of stores executed 554system.cpu.iew.exec_stores::1 1081 # Number of stores executed 555system.cpu.iew.exec_stores::total 2175 # Number of stores executed 556system.cpu.iew.exec_rate 0.458838 # Inst execution rate 557system.cpu.iew.wb_sent::0 10071 # cumulative count of insts sent to commit 558system.cpu.iew.wb_sent::1 10174 # cumulative count of insts sent to commit 559system.cpu.iew.wb_sent::total 20245 # cumulative count of insts sent to commit 560system.cpu.iew.wb_count::0 9887 # cumulative count of insts written-back 561system.cpu.iew.wb_count::1 9976 # cumulative count of insts written-back 562system.cpu.iew.wb_count::total 19863 # cumulative count of insts written-back 563system.cpu.iew.wb_producers::0 5227 # num instructions producing a value 564system.cpu.iew.wb_producers::1 5224 # num instructions producing a value 565system.cpu.iew.wb_producers::total 10451 # num instructions producing a value 566system.cpu.iew.wb_consumers::0 6995 # num instructions consuming a value 567system.cpu.iew.wb_consumers::1 6944 # num instructions consuming a value 568system.cpu.iew.wb_consumers::total 13939 # num instructions consuming a value 569system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ 570system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ 571system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ 572system.cpu.iew.wb_rate::0 0.213353 # insts written-back per cycle 573system.cpu.iew.wb_rate::1 0.215274 # insts written-back per cycle 574system.cpu.iew.wb_rate::total 0.428627 # insts written-back per cycle 575system.cpu.iew.wb_fanout::0 0.747248 # average fanout of values written-back 576system.cpu.iew.wb_fanout::1 0.752304 # average fanout of values written-back 577system.cpu.iew.wb_fanout::total 0.749767 # average fanout of values written-back 578system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ 579system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ 580system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ 581system.cpu.commit.commitSquashedInsts 14469 # The number of squashed insts skipped by commit 582system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards 583system.cpu.commit.branchMispredicts 1066 # The number of times a branch was mispredicted 584system.cpu.commit.committed_per_cycle::samples 28402 # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::mean 0.449898 # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::stdev 1.318202 # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::0 23341 82.18% 82.18% # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::1 2401 8.45% 90.63% # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::2 1094 3.85% 94.49% # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::3 390 1.37% 95.86% # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::4 322 1.13% 96.99% # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::5 184 0.65% 97.64% # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::6 208 0.73% 98.37% # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::7 133 0.47% 98.84% # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::8 329 1.16% 100.00% # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::total 28402 # Number of insts commited each cycle 601system.cpu.commit.committedInsts::0 6389 # Number of instructions committed 602system.cpu.commit.committedInsts::1 6389 # Number of instructions committed 603system.cpu.commit.committedInsts::total 12778 # Number of instructions committed 604system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed 605system.cpu.commit.committedOps::1 6389 # Number of ops (including micro ops) committed 606system.cpu.commit.committedOps::total 12778 # Number of ops (including micro ops) committed 607system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 608system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed 609system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed 610system.cpu.commit.refs::0 2048 # Number of memory references committed 611system.cpu.commit.refs::1 2048 # Number of memory references committed 612system.cpu.commit.refs::total 4096 # Number of memory references committed 613system.cpu.commit.loads::0 1183 # Number of loads committed 614system.cpu.commit.loads::1 1183 # Number of loads committed 615system.cpu.commit.loads::total 2366 # Number of loads committed 616system.cpu.commit.membars::0 0 # Number of memory barriers committed 617system.cpu.commit.membars::1 0 # Number of memory barriers committed 618system.cpu.commit.membars::total 0 # Number of memory barriers committed 619system.cpu.commit.branches::0 1050 # Number of branches committed 620system.cpu.commit.branches::1 1050 # Number of branches committed 621system.cpu.commit.branches::total 2100 # Number of branches committed 622system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. 623system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. 624system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. 625system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions. 626system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions. 627system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions. 628system.cpu.commit.function_calls::0 127 # Number of function calls committed. 629system.cpu.commit.function_calls::1 127 # Number of function calls committed. 630system.cpu.commit.function_calls::total 254 # Number of function calls committed. 631system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 632system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction 633system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction 634system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction 635system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction 636system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction 637system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction 638system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction 639system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction 640system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction 641system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction 642system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction 643system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction 644system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction 645system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction 646system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction 647system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction 648system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction 649system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction 654system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction 655system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction 656system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction 657system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction 658system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 659system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 660system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 661system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction 662system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction 663system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 664system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 665system.cpu.commit.op_class_0::total 6389 # Class of committed instruction 666system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction 667system.cpu.commit.op_class_1::IntAlu 4319 67.60% 67.90% # Class of committed instruction 668system.cpu.commit.op_class_1::IntMult 1 0.02% 67.91% # Class of committed instruction 669system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.91% # Class of committed instruction 670system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.94% # Class of committed instruction 671system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.94% # Class of committed instruction 672system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.94% # Class of committed instruction 673system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.94% # Class of committed instruction 674system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.94% # Class of committed instruction 675system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.94% # Class of committed instruction 676system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.94% # Class of committed instruction 677system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction 678system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.94% # Class of committed instruction 679system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.94% # Class of committed instruction 680system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.94% # Class of committed instruction 681system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.94% # Class of committed instruction 682system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.94% # Class of committed instruction 683system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction 684system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.94% # Class of committed instruction 685system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction 686system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.94% # Class of committed instruction 687system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction 688system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction 689system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction 690system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction 691system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction 692system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction 693system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 694system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 695system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 696system.cpu.commit.op_class_1::MemRead 1183 18.52% 86.46% # Class of committed instruction 697system.cpu.commit.op_class_1::MemWrite 865 13.54% 100.00% # Class of committed instruction 698system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction 699system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 700system.cpu.commit.op_class_1::total 6389 # Class of committed instruction 701system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction 702system.cpu.commit.bw_lim_events 329 # number cycles where commit BW limit reached 703system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits 704system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits 705system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits 706system.cpu.rob.rob_reads 131970 # The number of ROB reads 707system.cpu.rob.rob_writes 57167 # The number of ROB writes 708system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself 709system.cpu.idleCycles 17867 # Total number of cycles that the CPU has spent unscheduled due to idling 710system.cpu.committedInsts::0 6372 # Number of Instructions Simulated 711system.cpu.committedInsts::1 6372 # Number of Instructions Simulated 712system.cpu.committedInsts::total 12744 # Number of Instructions Simulated 713system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated 714system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated 715system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated 716system.cpu.cpi::0 7.272599 # CPI: Cycles Per Instruction 717system.cpu.cpi::1 7.272599 # CPI: Cycles Per Instruction 718system.cpu.cpi_total 3.636299 # CPI: Total CPI of All Threads 719system.cpu.ipc::0 0.137502 # IPC: Instructions Per Cycle 720system.cpu.ipc::1 0.137502 # IPC: Instructions Per Cycle 721system.cpu.ipc_total 0.275005 # IPC: Total IPC of All Threads 722system.cpu.int_regfile_reads 26712 # number of integer regfile reads 723system.cpu.int_regfile_writes 15170 # number of integer regfile writes 724system.cpu.fp_regfile_reads 16 # number of floating regfile reads 725system.cpu.fp_regfile_writes 4 # number of floating regfile writes 726system.cpu.misc_regfile_reads 2 # number of misc regfile reads 727system.cpu.misc_regfile_writes 2 # number of misc regfile writes 728system.cpu.toL2Bus.throughput 2709710833 # Throughput (bytes/s) 729system.cpu.toL2Bus.trans_dist::ReadReq 835 # Transaction distribution 730system.cpu.toL2Bus.trans_dist::ReadResp 835 # Transaction distribution 731system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution 732system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution 733system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1266 # Packet count per connected master and slave (bytes) 734system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 696 # Packet count per connected master and slave (bytes) 735system.cpu.toL2Bus.pkt_count::total 1962 # Packet count per connected master and slave (bytes) 736system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40512 # Cumulative packet size per connected master and slave (bytes) 737system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22272 # Cumulative packet size per connected master and slave (bytes) 738system.cpu.toL2Bus.tot_pkt_size::total 62784 # Cumulative packet size per connected master and slave (bytes) 739system.cpu.toL2Bus.data_through_bus 62784 # Total data (bytes) 740system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 741system.cpu.toL2Bus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) 742system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) 743system.cpu.toL2Bus.respLayer0.occupancy 1042000 # Layer occupancy (ticks) 744system.cpu.toL2Bus.respLayer0.utilization 4.5 # Layer utilization (%) 745system.cpu.toL2Bus.respLayer1.occupancy 550750 # Layer occupancy (ticks) 746system.cpu.toL2Bus.respLayer1.utilization 2.4 # Layer utilization (%) 747system.cpu.icache.tags.replacements::0 7 # number of replacements 748system.cpu.icache.tags.replacements::1 0 # number of replacements 749system.cpu.icache.tags.replacements::total 7 # number of replacements 750system.cpu.icache.tags.tagsinuse 316.397057 # Cycle average of tags in use 751system.cpu.icache.tags.total_refs 4348 # Total number of references to valid blocks. 752system.cpu.icache.tags.sampled_refs 633 # Sample count of references to valid blocks. 753system.cpu.icache.tags.avg_refs 6.868878 # Average number of references to valid blocks. 754system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 755system.cpu.icache.tags.occ_blocks::cpu.inst 316.397057 # Average occupied blocks per requestor 756system.cpu.icache.tags.occ_percent::cpu.inst 0.154491 # Average percentage of cache occupancy 757system.cpu.icache.tags.occ_percent::total 0.154491 # Average percentage of cache occupancy 758system.cpu.icache.tags.occ_task_id_blocks::1024 626 # Occupied blocks per task id 759system.cpu.icache.tags.age_task_id_blocks_1024::0 275 # Occupied blocks per task id 760system.cpu.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id 761system.cpu.icache.tags.occ_task_id_percent::1024 0.305664 # Percentage of cache occupancy per task id 762system.cpu.icache.tags.tag_accesses 11201 # Number of tag accesses 763system.cpu.icache.tags.data_accesses 11201 # Number of data accesses 764system.cpu.icache.ReadReq_hits::cpu.inst 4348 # number of ReadReq hits 765system.cpu.icache.ReadReq_hits::total 4348 # number of ReadReq hits 766system.cpu.icache.demand_hits::cpu.inst 4348 # number of demand (read+write) hits 767system.cpu.icache.demand_hits::total 4348 # number of demand (read+write) hits 768system.cpu.icache.overall_hits::cpu.inst 4348 # number of overall hits 769system.cpu.icache.overall_hits::total 4348 # number of overall hits 770system.cpu.icache.ReadReq_misses::cpu.inst 936 # number of ReadReq misses 771system.cpu.icache.ReadReq_misses::total 936 # number of ReadReq misses 772system.cpu.icache.demand_misses::cpu.inst 936 # number of demand (read+write) misses 773system.cpu.icache.demand_misses::total 936 # number of demand (read+write) misses 774system.cpu.icache.overall_misses::cpu.inst 936 # number of overall misses 775system.cpu.icache.overall_misses::total 936 # number of overall misses 776system.cpu.icache.ReadReq_miss_latency::cpu.inst 64563991 # number of ReadReq miss cycles 777system.cpu.icache.ReadReq_miss_latency::total 64563991 # number of ReadReq miss cycles 778system.cpu.icache.demand_miss_latency::cpu.inst 64563991 # number of demand (read+write) miss cycles 779system.cpu.icache.demand_miss_latency::total 64563991 # number of demand (read+write) miss cycles 780system.cpu.icache.overall_miss_latency::cpu.inst 64563991 # number of overall miss cycles 781system.cpu.icache.overall_miss_latency::total 64563991 # number of overall miss cycles 782system.cpu.icache.ReadReq_accesses::cpu.inst 5284 # number of ReadReq accesses(hits+misses) 783system.cpu.icache.ReadReq_accesses::total 5284 # number of ReadReq accesses(hits+misses) 784system.cpu.icache.demand_accesses::cpu.inst 5284 # number of demand (read+write) accesses 785system.cpu.icache.demand_accesses::total 5284 # number of demand (read+write) accesses 786system.cpu.icache.overall_accesses::cpu.inst 5284 # number of overall (read+write) accesses 787system.cpu.icache.overall_accesses::total 5284 # number of overall (read+write) accesses 788system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.177139 # miss rate for ReadReq accesses 789system.cpu.icache.ReadReq_miss_rate::total 0.177139 # miss rate for ReadReq accesses 790system.cpu.icache.demand_miss_rate::cpu.inst 0.177139 # miss rate for demand accesses 791system.cpu.icache.demand_miss_rate::total 0.177139 # miss rate for demand accesses 792system.cpu.icache.overall_miss_rate::cpu.inst 0.177139 # miss rate for overall accesses 793system.cpu.icache.overall_miss_rate::total 0.177139 # miss rate for overall accesses 794system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68978.622863 # average ReadReq miss latency 795system.cpu.icache.ReadReq_avg_miss_latency::total 68978.622863 # average ReadReq miss latency 796system.cpu.icache.demand_avg_miss_latency::cpu.inst 68978.622863 # average overall miss latency 797system.cpu.icache.demand_avg_miss_latency::total 68978.622863 # average overall miss latency 798system.cpu.icache.overall_avg_miss_latency::cpu.inst 68978.622863 # average overall miss latency 799system.cpu.icache.overall_avg_miss_latency::total 68978.622863 # average overall miss latency 800system.cpu.icache.blocked_cycles::no_mshrs 3153 # number of cycles access was blocked 801system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 802system.cpu.icache.blocked::no_mshrs 83 # number of cycles access was blocked 803system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 804system.cpu.icache.avg_blocked_cycles::no_mshrs 37.987952 # average number of cycles each access was blocked 805system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 806system.cpu.icache.fast_writes 0 # number of fast writes performed 807system.cpu.icache.cache_copies 0 # number of cache copies performed 808system.cpu.icache.ReadReq_mshr_hits::cpu.inst 303 # number of ReadReq MSHR hits 809system.cpu.icache.ReadReq_mshr_hits::total 303 # number of ReadReq MSHR hits 810system.cpu.icache.demand_mshr_hits::cpu.inst 303 # number of demand (read+write) MSHR hits 811system.cpu.icache.demand_mshr_hits::total 303 # number of demand (read+write) MSHR hits 812system.cpu.icache.overall_mshr_hits::cpu.inst 303 # number of overall MSHR hits 813system.cpu.icache.overall_mshr_hits::total 303 # number of overall MSHR hits 814system.cpu.icache.ReadReq_mshr_misses::cpu.inst 633 # number of ReadReq MSHR misses 815system.cpu.icache.ReadReq_mshr_misses::total 633 # number of ReadReq MSHR misses 816system.cpu.icache.demand_mshr_misses::cpu.inst 633 # number of demand (read+write) MSHR misses 817system.cpu.icache.demand_mshr_misses::total 633 # number of demand (read+write) MSHR misses 818system.cpu.icache.overall_mshr_misses::cpu.inst 633 # number of overall MSHR misses 819system.cpu.icache.overall_mshr_misses::total 633 # number of overall MSHR misses 820system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46517493 # number of ReadReq MSHR miss cycles 821system.cpu.icache.ReadReq_mshr_miss_latency::total 46517493 # number of ReadReq MSHR miss cycles 822system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46517493 # number of demand (read+write) MSHR miss cycles 823system.cpu.icache.demand_mshr_miss_latency::total 46517493 # number of demand (read+write) MSHR miss cycles 824system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46517493 # number of overall MSHR miss cycles 825system.cpu.icache.overall_mshr_miss_latency::total 46517493 # number of overall MSHR miss cycles 826system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.119796 # mshr miss rate for ReadReq accesses 827system.cpu.icache.ReadReq_mshr_miss_rate::total 0.119796 # mshr miss rate for ReadReq accesses 828system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.119796 # mshr miss rate for demand accesses 829system.cpu.icache.demand_mshr_miss_rate::total 0.119796 # mshr miss rate for demand accesses 830system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.119796 # mshr miss rate for overall accesses 831system.cpu.icache.overall_mshr_miss_rate::total 0.119796 # mshr miss rate for overall accesses 832system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73487.350711 # average ReadReq mshr miss latency 833system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73487.350711 # average ReadReq mshr miss latency 834system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73487.350711 # average overall mshr miss latency 835system.cpu.icache.demand_avg_mshr_miss_latency::total 73487.350711 # average overall mshr miss latency 836system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73487.350711 # average overall mshr miss latency 837system.cpu.icache.overall_avg_mshr_miss_latency::total 73487.350711 # average overall mshr miss latency 838system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 839system.cpu.l2cache.tags.replacements::0 0 # number of replacements 840system.cpu.l2cache.tags.replacements::1 0 # number of replacements 841system.cpu.l2cache.tags.replacements::total 0 # number of replacements 842system.cpu.l2cache.tags.tagsinuse 435.916526 # Cycle average of tags in use 843system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 844system.cpu.l2cache.tags.sampled_refs 833 # Sample count of references to valid blocks. 845system.cpu.l2cache.tags.avg_refs 0.002401 # Average number of references to valid blocks. 846system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 847system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.007070 # Average occupied blocks per requestor 848system.cpu.l2cache.tags.occ_blocks::cpu.data 118.909455 # Average occupied blocks per requestor 849system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009674 # Average percentage of cache occupancy 850system.cpu.l2cache.tags.occ_percent::cpu.data 0.003629 # Average percentage of cache occupancy 851system.cpu.l2cache.tags.occ_percent::total 0.013303 # Average percentage of cache occupancy 852system.cpu.l2cache.tags.occ_task_id_blocks::1024 833 # Occupied blocks per task id 853system.cpu.l2cache.tags.age_task_id_blocks_1024::0 350 # Occupied blocks per task id 854system.cpu.l2cache.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id 855system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025421 # Percentage of cache occupancy per task id 856system.cpu.l2cache.tags.tag_accesses 8827 # Number of tag accesses 857system.cpu.l2cache.tags.data_accesses 8827 # Number of data accesses 858system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 859system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 860system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 861system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 862system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 863system.cpu.l2cache.overall_hits::total 2 # number of overall hits 864system.cpu.l2cache.ReadReq_misses::cpu.inst 631 # number of ReadReq misses 865system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses 866system.cpu.l2cache.ReadReq_misses::total 833 # number of ReadReq misses 867system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses 868system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses 869system.cpu.l2cache.demand_misses::cpu.inst 631 # number of demand (read+write) misses 870system.cpu.l2cache.demand_misses::cpu.data 348 # number of demand (read+write) misses 871system.cpu.l2cache.demand_misses::total 979 # number of demand (read+write) misses 872system.cpu.l2cache.overall_misses::cpu.inst 631 # number of overall misses 873system.cpu.l2cache.overall_misses::cpu.data 348 # number of overall misses 874system.cpu.l2cache.overall_misses::total 979 # number of overall misses 875system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45857000 # number of ReadReq miss cycles 876system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16325500 # number of ReadReq miss cycles 877system.cpu.l2cache.ReadReq_miss_latency::total 62182500 # number of ReadReq miss cycles 878system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11847250 # number of ReadExReq miss cycles 879system.cpu.l2cache.ReadExReq_miss_latency::total 11847250 # number of ReadExReq miss cycles 880system.cpu.l2cache.demand_miss_latency::cpu.inst 45857000 # number of demand (read+write) miss cycles 881system.cpu.l2cache.demand_miss_latency::cpu.data 28172750 # number of demand (read+write) miss cycles 882system.cpu.l2cache.demand_miss_latency::total 74029750 # number of demand (read+write) miss cycles 883system.cpu.l2cache.overall_miss_latency::cpu.inst 45857000 # number of overall miss cycles 884system.cpu.l2cache.overall_miss_latency::cpu.data 28172750 # number of overall miss cycles 885system.cpu.l2cache.overall_miss_latency::total 74029750 # number of overall miss cycles 886system.cpu.l2cache.ReadReq_accesses::cpu.inst 633 # number of ReadReq accesses(hits+misses) 887system.cpu.l2cache.ReadReq_accesses::cpu.data 202 # number of ReadReq accesses(hits+misses) 888system.cpu.l2cache.ReadReq_accesses::total 835 # number of ReadReq accesses(hits+misses) 889system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) 890system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) 891system.cpu.l2cache.demand_accesses::cpu.inst 633 # number of demand (read+write) accesses 892system.cpu.l2cache.demand_accesses::cpu.data 348 # number of demand (read+write) accesses 893system.cpu.l2cache.demand_accesses::total 981 # number of demand (read+write) accesses 894system.cpu.l2cache.overall_accesses::cpu.inst 633 # number of overall (read+write) accesses 895system.cpu.l2cache.overall_accesses::cpu.data 348 # number of overall (read+write) accesses 896system.cpu.l2cache.overall_accesses::total 981 # number of overall (read+write) accesses 897system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996840 # miss rate for ReadReq accesses 898system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 899system.cpu.l2cache.ReadReq_miss_rate::total 0.997605 # miss rate for ReadReq accesses 900system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 901system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 902system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996840 # miss rate for demand accesses 903system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 904system.cpu.l2cache.demand_miss_rate::total 0.997961 # miss rate for demand accesses 905system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996840 # miss rate for overall accesses 906system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 907system.cpu.l2cache.overall_miss_rate::total 0.997961 # miss rate for overall accesses 908system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72673.534073 # average ReadReq miss latency 909system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80819.306931 # average ReadReq miss latency 910system.cpu.l2cache.ReadReq_avg_miss_latency::total 74648.859544 # average ReadReq miss latency 911system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81145.547945 # average ReadExReq miss latency 912system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81145.547945 # average ReadExReq miss latency 913system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72673.534073 # average overall miss latency 914system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80956.178161 # average overall miss latency 915system.cpu.l2cache.demand_avg_miss_latency::total 75617.722165 # average overall miss latency 916system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72673.534073 # average overall miss latency 917system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80956.178161 # average overall miss latency 918system.cpu.l2cache.overall_avg_miss_latency::total 75617.722165 # average overall miss latency 919system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 920system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 921system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 922system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 923system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 924system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 925system.cpu.l2cache.fast_writes 0 # number of fast writes performed 926system.cpu.l2cache.cache_copies 0 # number of cache copies performed 927system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 631 # number of ReadReq MSHR misses 928system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses 929system.cpu.l2cache.ReadReq_mshr_misses::total 833 # number of ReadReq MSHR misses 930system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses 931system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses 932system.cpu.l2cache.demand_mshr_misses::cpu.inst 631 # number of demand (read+write) MSHR misses 933system.cpu.l2cache.demand_mshr_misses::cpu.data 348 # number of demand (read+write) MSHR misses 934system.cpu.l2cache.demand_mshr_misses::total 979 # number of demand (read+write) MSHR misses 935system.cpu.l2cache.overall_mshr_misses::cpu.inst 631 # number of overall MSHR misses 936system.cpu.l2cache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses 937system.cpu.l2cache.overall_mshr_misses::total 979 # number of overall MSHR misses 938system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 37981000 # number of ReadReq MSHR miss cycles 939system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13848500 # number of ReadReq MSHR miss cycles 940system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51829500 # number of ReadReq MSHR miss cycles 941system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10060750 # number of ReadExReq MSHR miss cycles 942system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10060750 # number of ReadExReq MSHR miss cycles 943system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37981000 # number of demand (read+write) MSHR miss cycles 944system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23909250 # number of demand (read+write) MSHR miss cycles 945system.cpu.l2cache.demand_mshr_miss_latency::total 61890250 # number of demand (read+write) MSHR miss cycles 946system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37981000 # number of overall MSHR miss cycles 947system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23909250 # number of overall MSHR miss cycles 948system.cpu.l2cache.overall_mshr_miss_latency::total 61890250 # number of overall MSHR miss cycles 949system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996840 # mshr miss rate for ReadReq accesses 950system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 951system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997605 # mshr miss rate for ReadReq accesses 952system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 953system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 954system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996840 # mshr miss rate for demand accesses 955system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 956system.cpu.l2cache.demand_mshr_miss_rate::total 0.997961 # mshr miss rate for demand accesses 957system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996840 # mshr miss rate for overall accesses 958system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 959system.cpu.l2cache.overall_mshr_miss_rate::total 0.997961 # mshr miss rate for overall accesses 960system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60191.759113 # average ReadReq mshr miss latency 961system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68556.930693 # average ReadReq mshr miss latency 962system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62220.288115 # average ReadReq mshr miss latency 963system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68909.246575 # average ReadExReq mshr miss latency 964system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68909.246575 # average ReadExReq mshr miss latency 965system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60191.759113 # average overall mshr miss latency 966system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68704.741379 # average overall mshr miss latency 967system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63217.824311 # average overall mshr miss latency 968system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60191.759113 # average overall mshr miss latency 969system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68704.741379 # average overall mshr miss latency 970system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63217.824311 # average overall mshr miss latency 971system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 972system.cpu.dcache.tags.replacements::0 0 # number of replacements 973system.cpu.dcache.tags.replacements::1 0 # number of replacements 974system.cpu.dcache.tags.replacements::total 0 # number of replacements 975system.cpu.dcache.tags.tagsinuse 212.136486 # Cycle average of tags in use 976system.cpu.dcache.tags.total_refs 4920 # Total number of references to valid blocks. 977system.cpu.dcache.tags.sampled_refs 348 # Sample count of references to valid blocks. 978system.cpu.dcache.tags.avg_refs 14.137931 # Average number of references to valid blocks. 979system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 980system.cpu.dcache.tags.occ_blocks::cpu.data 212.136486 # Average occupied blocks per requestor 981system.cpu.dcache.tags.occ_percent::cpu.data 0.051791 # Average percentage of cache occupancy 982system.cpu.dcache.tags.occ_percent::total 0.051791 # Average percentage of cache occupancy 983system.cpu.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id 984system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id 985system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id 986system.cpu.dcache.tags.occ_task_id_percent::1024 0.084961 # Percentage of cache occupancy per task id 987system.cpu.dcache.tags.tag_accesses 12242 # Number of tag accesses 988system.cpu.dcache.tags.data_accesses 12242 # Number of data accesses 989system.cpu.dcache.ReadReq_hits::cpu.data 3896 # number of ReadReq hits 990system.cpu.dcache.ReadReq_hits::total 3896 # number of ReadReq hits 991system.cpu.dcache.WriteReq_hits::cpu.data 1024 # number of WriteReq hits 992system.cpu.dcache.WriteReq_hits::total 1024 # number of WriteReq hits 993system.cpu.dcache.demand_hits::cpu.data 4920 # number of demand (read+write) hits 994system.cpu.dcache.demand_hits::total 4920 # number of demand (read+write) hits 995system.cpu.dcache.overall_hits::cpu.data 4920 # number of overall hits 996system.cpu.dcache.overall_hits::total 4920 # number of overall hits 997system.cpu.dcache.ReadReq_misses::cpu.data 321 # number of ReadReq misses 998system.cpu.dcache.ReadReq_misses::total 321 # number of ReadReq misses 999system.cpu.dcache.WriteReq_misses::cpu.data 706 # number of WriteReq misses 1000system.cpu.dcache.WriteReq_misses::total 706 # number of WriteReq misses 1001system.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses 1002system.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses 1003system.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses 1004system.cpu.dcache.overall_misses::total 1027 # number of overall misses 1005system.cpu.dcache.ReadReq_miss_latency::cpu.data 23379250 # number of ReadReq miss cycles 1006system.cpu.dcache.ReadReq_miss_latency::total 23379250 # number of ReadReq miss cycles 1007system.cpu.dcache.WriteReq_miss_latency::cpu.data 51507169 # number of WriteReq miss cycles 1008system.cpu.dcache.WriteReq_miss_latency::total 51507169 # number of WriteReq miss cycles 1009system.cpu.dcache.demand_miss_latency::cpu.data 74886419 # number of demand (read+write) miss cycles 1010system.cpu.dcache.demand_miss_latency::total 74886419 # number of demand (read+write) miss cycles 1011system.cpu.dcache.overall_miss_latency::cpu.data 74886419 # number of overall miss cycles 1012system.cpu.dcache.overall_miss_latency::total 74886419 # number of overall miss cycles 1013system.cpu.dcache.ReadReq_accesses::cpu.data 4217 # number of ReadReq accesses(hits+misses) 1014system.cpu.dcache.ReadReq_accesses::total 4217 # number of ReadReq accesses(hits+misses) 1015system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) 1016system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) 1017system.cpu.dcache.demand_accesses::cpu.data 5947 # number of demand (read+write) accesses 1018system.cpu.dcache.demand_accesses::total 5947 # number of demand (read+write) accesses 1019system.cpu.dcache.overall_accesses::cpu.data 5947 # number of overall (read+write) accesses 1020system.cpu.dcache.overall_accesses::total 5947 # number of overall (read+write) accesses 1021system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076120 # miss rate for ReadReq accesses 1022system.cpu.dcache.ReadReq_miss_rate::total 0.076120 # miss rate for ReadReq accesses 1023system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.408092 # miss rate for WriteReq accesses 1024system.cpu.dcache.WriteReq_miss_rate::total 0.408092 # miss rate for WriteReq accesses 1025system.cpu.dcache.demand_miss_rate::cpu.data 0.172692 # miss rate for demand accesses 1026system.cpu.dcache.demand_miss_rate::total 0.172692 # miss rate for demand accesses 1027system.cpu.dcache.overall_miss_rate::cpu.data 0.172692 # miss rate for overall accesses 1028system.cpu.dcache.overall_miss_rate::total 0.172692 # miss rate for overall accesses 1029system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72832.554517 # average ReadReq miss latency 1030system.cpu.dcache.ReadReq_avg_miss_latency::total 72832.554517 # average ReadReq miss latency 1031system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72956.330028 # average WriteReq miss latency 1032system.cpu.dcache.WriteReq_avg_miss_latency::total 72956.330028 # average WriteReq miss latency 1033system.cpu.dcache.demand_avg_miss_latency::cpu.data 72917.642648 # average overall miss latency 1034system.cpu.dcache.demand_avg_miss_latency::total 72917.642648 # average overall miss latency 1035system.cpu.dcache.overall_avg_miss_latency::cpu.data 72917.642648 # average overall miss latency 1036system.cpu.dcache.overall_avg_miss_latency::total 72917.642648 # average overall miss latency 1037system.cpu.dcache.blocked_cycles::no_mshrs 5674 # number of cycles access was blocked 1038system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1039system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked 1040system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1041system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.820144 # average number of cycles each access was blocked 1042system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1043system.cpu.dcache.fast_writes 0 # number of fast writes performed 1044system.cpu.dcache.cache_copies 0 # number of cache copies performed 1045system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits 1046system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits 1047system.cpu.dcache.WriteReq_mshr_hits::cpu.data 560 # number of WriteReq MSHR hits 1048system.cpu.dcache.WriteReq_mshr_hits::total 560 # number of WriteReq MSHR hits 1049system.cpu.dcache.demand_mshr_hits::cpu.data 679 # number of demand (read+write) MSHR hits 1050system.cpu.dcache.demand_mshr_hits::total 679 # number of demand (read+write) MSHR hits 1051system.cpu.dcache.overall_mshr_hits::cpu.data 679 # number of overall MSHR hits 1052system.cpu.dcache.overall_mshr_hits::total 679 # number of overall MSHR hits 1053system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses 1054system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses 1055system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses 1056system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses 1057system.cpu.dcache.demand_mshr_misses::cpu.data 348 # number of demand (read+write) MSHR misses 1058system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses 1059system.cpu.dcache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses 1060system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses 1061system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16537500 # number of ReadReq MSHR miss cycles 1062system.cpu.dcache.ReadReq_mshr_miss_latency::total 16537500 # number of ReadReq MSHR miss cycles 1063system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11999490 # number of WriteReq MSHR miss cycles 1064system.cpu.dcache.WriteReq_mshr_miss_latency::total 11999490 # number of WriteReq MSHR miss cycles 1065system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28536990 # number of demand (read+write) MSHR miss cycles 1066system.cpu.dcache.demand_mshr_miss_latency::total 28536990 # number of demand (read+write) MSHR miss cycles 1067system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28536990 # number of overall MSHR miss cycles 1068system.cpu.dcache.overall_mshr_miss_latency::total 28536990 # number of overall MSHR miss cycles 1069system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047901 # mshr miss rate for ReadReq accesses 1070system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.047901 # mshr miss rate for ReadReq accesses 1071system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 1072system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 1073system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058517 # mshr miss rate for demand accesses 1074system.cpu.dcache.demand_mshr_miss_rate::total 0.058517 # mshr miss rate for demand accesses 1075system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058517 # mshr miss rate for overall accesses 1076system.cpu.dcache.overall_mshr_miss_rate::total 0.058517 # mshr miss rate for overall accesses 1077system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81868.811881 # average ReadReq mshr miss latency 1078system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81868.811881 # average ReadReq mshr miss latency 1079system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82188.287671 # average WriteReq mshr miss latency 1080system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82188.287671 # average WriteReq mshr miss latency 1081system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82002.844828 # average overall mshr miss latency 1082system.cpu.dcache.demand_avg_mshr_miss_latency::total 82002.844828 # average overall mshr miss latency 1083system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82002.844828 # average overall mshr miss latency 1084system.cpu.dcache.overall_avg_mshr_miss_latency::total 82002.844828 # average overall mshr miss latency 1085system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1086 1087---------- End Simulation Statistics ---------- 1088