stats.txt revision 10148
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000024 # Number of seconds simulated 4sim_ticks 24195500 # Number of ticks simulated 5final_tick 24195500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 65180 # Simulator instruction rate (inst/s) 8host_op_rate 65175 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 123719748 # Simulator tick rate (ticks/s) 10host_mem_usage 266292 # Number of bytes of host memory used 11host_seconds 0.20 # Real time elapsed on the host 12sim_insts 12745 # Number of instructions simulated 13sim_ops 12745 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory 18system.physmem.bytes_read::total 62336 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 39936 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 39936 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 624 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 974 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1650554855 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 925791986 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2576346841 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1650554855 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1650554855 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1650554855 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 925791986 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2576346841 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 974 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 974 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 62336 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 62336 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 83 # Per bank write bursts 45system.physmem.perBankRdBursts::1 153 # Per bank write bursts 46system.physmem.perBankRdBursts::2 77 # Per bank write bursts 47system.physmem.perBankRdBursts::3 59 # Per bank write bursts 48system.physmem.perBankRdBursts::4 87 # Per bank write bursts 49system.physmem.perBankRdBursts::5 49 # Per bank write bursts 50system.physmem.perBankRdBursts::6 32 # Per bank write bursts 51system.physmem.perBankRdBursts::7 49 # Per bank write bursts 52system.physmem.perBankRdBursts::8 42 # Per bank write bursts 53system.physmem.perBankRdBursts::9 38 # Per bank write bursts 54system.physmem.perBankRdBursts::10 30 # Per bank write bursts 55system.physmem.perBankRdBursts::11 33 # Per bank write bursts 56system.physmem.perBankRdBursts::12 15 # Per bank write bursts 57system.physmem.perBankRdBursts::13 121 # Per bank write bursts 58system.physmem.perBankRdBursts::14 70 # Per bank write bursts 59system.physmem.perBankRdBursts::15 36 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 24047500 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 974 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 336 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 371 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 175 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 71 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 173 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 267.838150 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 164.887930 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 289.529003 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 68 39.31% 39.31% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 43 24.86% 64.16% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 22 12.72% 76.88% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 7 4.05% 80.92% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 7 4.05% 84.97% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 7 4.05% 89.02% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 5 2.89% 91.91% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 2 1.16% 93.06% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 12 6.94% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 173 # Bytes accessed per row activation 203system.physmem.totQLat 8580250 # Total ticks spent queuing 204system.physmem.totMemAccLat 30335250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 4870000 # Total ticks spent in databus transfers 206system.physmem.totBankLat 16885000 # Total ticks spent accessing banks 207system.physmem.avgQLat 8809.29 # Average queueing delay per DRAM burst 208system.physmem.avgBankLat 17335.73 # Average bank access latency per DRAM burst 209system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 210system.physmem.avgMemAccLat 31145.02 # Average memory access latency per DRAM burst 211system.physmem.avgRdBW 2576.35 # Average DRAM read bandwidth in MiByte/s 212system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 213system.physmem.avgRdBWSys 2576.35 # Average system read bandwidth in MiByte/s 214system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 215system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 216system.physmem.busUtil 20.13 # Data bus utilization in percentage 217system.physmem.busUtilRead 20.13 # Data bus utilization in percentage for reads 218system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 219system.physmem.avgRdQLen 2.36 # Average read queue length when enqueuing 220system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 221system.physmem.readRowHits 752 # Number of row buffer hits during reads 222system.physmem.writeRowHits 0 # Number of row buffer hits during writes 223system.physmem.readRowHitRate 77.21 # Row buffer hit rate for reads 224system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 225system.physmem.avgGap 24689.43 # Average gap between requests 226system.physmem.pageHitRate 77.21 # Row buffer hit rate, read and write combined 227system.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state 228system.membus.throughput 2576346841 # Throughput (bytes/s) 229system.membus.trans_dist::ReadReq 828 # Transaction distribution 230system.membus.trans_dist::ReadResp 828 # Transaction distribution 231system.membus.trans_dist::ReadExReq 146 # Transaction distribution 232system.membus.trans_dist::ReadExResp 146 # Transaction distribution 233system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1948 # Packet count per connected master and slave (bytes) 234system.membus.pkt_count::total 1948 # Packet count per connected master and slave (bytes) 235system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62336 # Cumulative packet size per connected master and slave (bytes) 236system.membus.tot_pkt_size::total 62336 # Cumulative packet size per connected master and slave (bytes) 237system.membus.data_through_bus 62336 # Total data (bytes) 238system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 239system.membus.reqLayer0.occupancy 1237000 # Layer occupancy (ticks) 240system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) 241system.membus.respLayer1.occupancy 9035750 # Layer occupancy (ticks) 242system.membus.respLayer1.utilization 37.3 # Layer utilization (%) 243system.cpu_clk_domain.clock 500 # Clock period in ticks 244system.cpu.branchPred.lookups 6713 # Number of BP lookups 245system.cpu.branchPred.condPredicted 3825 # Number of conditional branches predicted 246system.cpu.branchPred.condIncorrect 1484 # Number of conditional branches incorrect 247system.cpu.branchPred.BTBLookups 4727 # Number of BTB lookups 248system.cpu.branchPred.BTBHits 847 # Number of BTB hits 249system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 250system.cpu.branchPred.BTBHitPct 17.918341 # BTB Hit Percentage 251system.cpu.branchPred.usedRAS 896 # Number of times the RAS was used to get a target. 252system.cpu.branchPred.RASInCorrect 174 # Number of incorrect RAS predictions. 253system.cpu.dtb.fetch_hits 0 # ITB hits 254system.cpu.dtb.fetch_misses 0 # ITB misses 255system.cpu.dtb.fetch_acv 0 # ITB acv 256system.cpu.dtb.fetch_accesses 0 # ITB accesses 257system.cpu.dtb.read_hits 4562 # DTB read hits 258system.cpu.dtb.read_misses 106 # DTB read misses 259system.cpu.dtb.read_acv 0 # DTB read access violations 260system.cpu.dtb.read_accesses 4668 # DTB read accesses 261system.cpu.dtb.write_hits 2031 # DTB write hits 262system.cpu.dtb.write_misses 86 # DTB write misses 263system.cpu.dtb.write_acv 0 # DTB write access violations 264system.cpu.dtb.write_accesses 2117 # DTB write accesses 265system.cpu.dtb.data_hits 6593 # DTB hits 266system.cpu.dtb.data_misses 192 # DTB misses 267system.cpu.dtb.data_acv 0 # DTB access violations 268system.cpu.dtb.data_accesses 6785 # DTB accesses 269system.cpu.itb.fetch_hits 5378 # ITB hits 270system.cpu.itb.fetch_misses 56 # ITB misses 271system.cpu.itb.fetch_acv 0 # ITB acv 272system.cpu.itb.fetch_accesses 5434 # ITB accesses 273system.cpu.itb.read_hits 0 # DTB read hits 274system.cpu.itb.read_misses 0 # DTB read misses 275system.cpu.itb.read_acv 0 # DTB read access violations 276system.cpu.itb.read_accesses 0 # DTB read accesses 277system.cpu.itb.write_hits 0 # DTB write hits 278system.cpu.itb.write_misses 0 # DTB write misses 279system.cpu.itb.write_acv 0 # DTB write access violations 280system.cpu.itb.write_accesses 0 # DTB write accesses 281system.cpu.itb.data_hits 0 # DTB hits 282system.cpu.itb.data_misses 0 # DTB misses 283system.cpu.itb.data_acv 0 # DTB access violations 284system.cpu.itb.data_accesses 0 # DTB accesses 285system.cpu.workload0.num_syscalls 17 # Number of system calls 286system.cpu.workload1.num_syscalls 17 # Number of system calls 287system.cpu.numCycles 48392 # number of cpu cycles simulated 288system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 289system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 290system.cpu.fetch.icacheStallCycles 1584 # Number of cycles fetch is stalled on an Icache miss 291system.cpu.fetch.Insts 37241 # Number of instructions fetch has processed 292system.cpu.fetch.Branches 6713 # Number of branches that fetch encountered 293system.cpu.fetch.predictedBranches 1743 # Number of branches that fetch has predicted taken 294system.cpu.fetch.Cycles 6224 # Number of cycles fetch has run and was not squashing or blocked 295system.cpu.fetch.SquashCycles 1851 # Number of cycles fetch has spent squashing 296system.cpu.fetch.MiscStallCycles 283 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 297system.cpu.fetch.CacheLines 5378 # Number of cache lines fetched 298system.cpu.fetch.IcacheSquashes 894 # Number of outstanding Icache misses that were squashed 299system.cpu.fetch.rateDist::samples 28253 # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::mean 1.318126 # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::stdev 2.738229 # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::0 22029 77.97% 77.97% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::1 543 1.92% 79.89% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::2 355 1.26% 81.15% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::3 435 1.54% 82.69% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::4 449 1.59% 84.28% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::5 397 1.41% 85.68% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::6 461 1.63% 87.31% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::7 536 1.90% 89.21% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::8 3048 10.79% 100.00% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::total 28253 # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.branchRate 0.138721 # Number of branch fetches per cycle 317system.cpu.fetch.rate 0.769569 # Number of inst fetches per cycle 318system.cpu.decode.IdleCycles 39403 # Number of cycles decode is idle 319system.cpu.decode.BlockedCycles 8381 # Number of cycles decode is blocked 320system.cpu.decode.RunCycles 5346 # Number of cycles decode is running 321system.cpu.decode.UnblockCycles 468 # Number of cycles decode is unblocking 322system.cpu.decode.SquashCycles 2729 # Number of cycles decode is squashing 323system.cpu.decode.BranchResolved 576 # Number of times decode resolved a branch 324system.cpu.decode.BranchMispred 358 # Number of times decode detected a branch misprediction 325system.cpu.decode.DecodedInsts 32540 # Number of instructions handled by decode 326system.cpu.decode.SquashedInsts 795 # Number of squashed instructions handled by decode 327system.cpu.rename.SquashCycles 2729 # Number of cycles rename is squashing 328system.cpu.rename.IdleCycles 40132 # Number of cycles rename is idle 329system.cpu.rename.BlockCycles 5179 # Number of cycles rename is blocking 330system.cpu.rename.serializeStallCycles 1042 # count of cycles rename stalled for serializing inst 331system.cpu.rename.RunCycles 4980 # Number of cycles rename is running 332system.cpu.rename.UnblockCycles 2265 # Number of cycles rename is unblocking 333system.cpu.rename.RenamedInsts 30075 # Number of instructions processed by rename 334system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full 335system.cpu.rename.LSQFullEvents 2305 # Number of times rename has blocked due to LSQ full 336system.cpu.rename.RenamedOperands 22490 # Number of destination operands rename has renamed 337system.cpu.rename.RenameLookups 37013 # Number of register rename lookups that rename has made 338system.cpu.rename.int_rename_lookups 36995 # Number of integer rename lookups 339system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 340system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed 341system.cpu.rename.UndoneMaps 13350 # Number of HB maps that are undone due to squashing 342system.cpu.rename.serializingInsts 49 # count of serializing insts renamed 343system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed 344system.cpu.rename.skidInsts 6315 # count of insts added to the skid buffer 345system.cpu.memDep0.insertedLoads 2908 # Number of loads inserted to the mem dependence unit. 346system.cpu.memDep0.insertedStores 1349 # Number of stores inserted to the mem dependence unit. 347system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. 348system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 349system.cpu.memDep1.insertedLoads 3030 # Number of loads inserted to the mem dependence unit. 350system.cpu.memDep1.insertedStores 1436 # Number of stores inserted to the mem dependence unit. 351system.cpu.memDep1.conflictingLoads 1 # Number of conflicting loads. 352system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. 353system.cpu.iq.iqInstsAdded 26280 # Number of instructions added to the IQ (excludes non-spec) 354system.cpu.iq.iqNonSpecInstsAdded 79 # Number of non-speculative instructions added to the IQ 355system.cpu.iq.iqInstsIssued 21655 # Number of instructions issued 356system.cpu.iq.iqSquashedInstsIssued 129 # Number of squashed instructions issued 357system.cpu.iq.iqSquashedInstsExamined 12548 # Number of squashed instructions iterated over during squash; mainly for profiling 358system.cpu.iq.iqSquashedOperandsExamined 7940 # Number of squashed operands that are examined and possibly removed from graph 359system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed 360system.cpu.iq.issued_per_cycle::samples 28253 # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::mean 0.766467 # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::stdev 1.344323 # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::0 18861 66.76% 66.76% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::1 3387 11.99% 78.75% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::2 2636 9.33% 88.08% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::3 1597 5.65% 93.73% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::4 1020 3.61% 97.34% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::5 473 1.67% 99.01% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::6 215 0.76% 99.77% # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::7 42 0.15% 99.92% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::8 22 0.08% 100.00% # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::total 28253 # Number of insts issued each cycle 377system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 378system.cpu.iq.fu_full::IntAlu 3 1.75% 1.75% # attempts to use FU when none available 379system.cpu.iq.fu_full::IntMult 0 0.00% 1.75% # attempts to use FU when none available 380system.cpu.iq.fu_full::IntDiv 0 0.00% 1.75% # attempts to use FU when none available 381system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.75% # attempts to use FU when none available 382system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.75% # attempts to use FU when none available 383system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.75% # attempts to use FU when none available 384system.cpu.iq.fu_full::FloatMult 0 0.00% 1.75% # attempts to use FU when none available 385system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.75% # attempts to use FU when none available 386system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.75% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.75% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.75% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.75% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.75% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.75% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.75% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdMult 0 0.00% 1.75% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.75% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdShift 0 0.00% 1.75% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.75% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.75% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.75% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.75% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.75% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.75% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.75% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.75% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.75% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.75% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.75% # attempts to use FU when none available 407system.cpu.iq.fu_full::MemRead 104 60.82% 62.57% # attempts to use FU when none available 408system.cpu.iq.fu_full::MemWrite 64 37.43% 100.00% # attempts to use FU when none available 409system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 410system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 411system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 412system.cpu.iq.FU_type_0::IntAlu 7084 66.01% 66.03% # Type of FU issued 413system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.04% # Type of FU issued 414system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.04% # Type of FU issued 415system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.05% # Type of FU issued 416system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.05% # Type of FU issued 417system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.05% # Type of FU issued 418system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.05% # Type of FU issued 419system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.05% # Type of FU issued 420system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.05% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.05% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.05% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.05% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.05% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.05% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.05% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.05% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.05% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.05% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.05% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.05% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.05% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.05% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.05% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.05% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.05% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.05% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.05% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.05% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.05% # Type of FU issued 441system.cpu.iq.FU_type_0::MemRead 2526 23.54% 89.59% # Type of FU issued 442system.cpu.iq.FU_type_0::MemWrite 1117 10.41% 100.00% # Type of FU issued 443system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 444system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 445system.cpu.iq.FU_type_0::total 10732 # Type of FU issued 446system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued 447system.cpu.iq.FU_type_1::IntAlu 7192 65.84% 65.86% # Type of FU issued 448system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.87% # Type of FU issued 449system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.87% # Type of FU issued 450system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.89% # Type of FU issued 451system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.89% # Type of FU issued 452system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.89% # Type of FU issued 453system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.89% # Type of FU issued 454system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.89% # Type of FU issued 455system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.89% # Type of FU issued 456system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.89% # Type of FU issued 457system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.89% # Type of FU issued 458system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.89% # Type of FU issued 459system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.89% # Type of FU issued 460system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.89% # Type of FU issued 461system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.89% # Type of FU issued 462system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.89% # Type of FU issued 463system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.89% # Type of FU issued 464system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.89% # Type of FU issued 465system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.89% # Type of FU issued 466system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.89% # Type of FU issued 467system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.89% # Type of FU issued 468system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.89% # Type of FU issued 469system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.89% # Type of FU issued 470system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.89% # Type of FU issued 471system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.89% # Type of FU issued 472system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.89% # Type of FU issued 473system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.89% # Type of FU issued 474system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.89% # Type of FU issued 475system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.89% # Type of FU issued 476system.cpu.iq.FU_type_1::MemRead 2608 23.88% 89.76% # Type of FU issued 477system.cpu.iq.FU_type_1::MemWrite 1118 10.24% 100.00% # Type of FU issued 478system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 479system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued 480system.cpu.iq.FU_type_1::total 10923 # Type of FU issued 481system.cpu.iq.FU_type::total 21655 0.00% 0.00% # Type of FU issued 482system.cpu.iq.rate 0.447491 # Inst issue rate 483system.cpu.iq.fu_busy_cnt::0 83 # FU busy when requested 484system.cpu.iq.fu_busy_cnt::1 88 # FU busy when requested 485system.cpu.iq.fu_busy_cnt::total 171 # FU busy when requested 486system.cpu.iq.fu_busy_rate::0 0.003833 # FU busy rate (busy events/executed inst) 487system.cpu.iq.fu_busy_rate::1 0.004064 # FU busy rate (busy events/executed inst) 488system.cpu.iq.fu_busy_rate::total 0.007897 # FU busy rate (busy events/executed inst) 489system.cpu.iq.int_inst_queue_reads 71821 # Number of integer instruction queue reads 490system.cpu.iq.int_inst_queue_writes 38912 # Number of integer instruction queue writes 491system.cpu.iq.int_inst_queue_wakeup_accesses 18708 # Number of integer instruction queue wakeup accesses 492system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads 493system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 494system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses 495system.cpu.iq.int_alu_accesses 21800 # Number of integer alu accesses 496system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses 497system.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores 498system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 499system.cpu.iew.lsq.thread0.squashedLoads 1725 # Number of loads squashed 500system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 501system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations 502system.cpu.iew.lsq.thread0.squashedStores 484 # Number of stores squashed 503system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 504system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 505system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 506system.cpu.iew.lsq.thread0.cacheBlocked 332 # Number of times an access to memory failed due to the cache being blocked 507system.cpu.iew.lsq.thread1.forwLoads 52 # Number of loads that had data forwarded from stores 508system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address 509system.cpu.iew.lsq.thread1.squashedLoads 1847 # Number of loads squashed 510system.cpu.iew.lsq.thread1.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed 511system.cpu.iew.lsq.thread1.memOrderViolation 14 # Number of memory ordering violations 512system.cpu.iew.lsq.thread1.squashedStores 571 # Number of stores squashed 513system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 514system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 515system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled 516system.cpu.iew.lsq.thread1.cacheBlocked 394 # Number of times an access to memory failed due to the cache being blocked 517system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 518system.cpu.iew.iewSquashCycles 2729 # Number of cycles IEW is squashing 519system.cpu.iew.iewBlockCycles 1818 # Number of cycles IEW is blocking 520system.cpu.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking 521system.cpu.iew.iewDispatchedInsts 26553 # Number of instructions dispatched to IQ 522system.cpu.iew.iewDispSquashedInsts 614 # Number of squashed instructions skipped by dispatch 523system.cpu.iew.iewDispLoadInsts 5938 # Number of dispatched load instructions 524system.cpu.iew.iewDispStoreInsts 2785 # Number of dispatched store instructions 525system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions 526system.cpu.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall 527system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall 528system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations 529system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly 530system.cpu.iew.predictedNotTakenIncorrect 1081 # Number of branches that were predicted not taken incorrectly 531system.cpu.iew.branchMispredicts 1321 # Number of branch mispredicts detected at execute 532system.cpu.iew.iewExecutedInsts 20146 # Number of executed instructions 533system.cpu.iew.iewExecLoadInsts::0 2319 # Number of load instructions executed 534system.cpu.iew.iewExecLoadInsts::1 2367 # Number of load instructions executed 535system.cpu.iew.iewExecLoadInsts::total 4686 # Number of load instructions executed 536system.cpu.iew.iewExecSquashedInsts 1509 # Number of squashed instructions skipped in execute 537system.cpu.iew.exec_swp::0 0 # number of swp insts executed 538system.cpu.iew.exec_swp::1 0 # number of swp insts executed 539system.cpu.iew.exec_swp::total 0 # number of swp insts executed 540system.cpu.iew.exec_nop::0 105 # number of nop insts executed 541system.cpu.iew.exec_nop::1 89 # number of nop insts executed 542system.cpu.iew.exec_nop::total 194 # number of nop insts executed 543system.cpu.iew.exec_refs::0 3378 # number of memory reference insts executed 544system.cpu.iew.exec_refs::1 3437 # number of memory reference insts executed 545system.cpu.iew.exec_refs::total 6815 # number of memory reference insts executed 546system.cpu.iew.exec_branches::0 1579 # Number of branches executed 547system.cpu.iew.exec_branches::1 1604 # Number of branches executed 548system.cpu.iew.exec_branches::total 3183 # Number of branches executed 549system.cpu.iew.exec_stores::0 1059 # Number of stores executed 550system.cpu.iew.exec_stores::1 1070 # Number of stores executed 551system.cpu.iew.exec_stores::total 2129 # Number of stores executed 552system.cpu.iew.exec_rate 0.416308 # Inst execution rate 553system.cpu.iew.wb_sent::0 9480 # cumulative count of insts sent to commit 554system.cpu.iew.wb_sent::1 9551 # cumulative count of insts sent to commit 555system.cpu.iew.wb_sent::total 19031 # cumulative count of insts sent to commit 556system.cpu.iew.wb_count::0 9310 # cumulative count of insts written-back 557system.cpu.iew.wb_count::1 9418 # cumulative count of insts written-back 558system.cpu.iew.wb_count::total 18728 # cumulative count of insts written-back 559system.cpu.iew.wb_producers::0 4774 # num instructions producing a value 560system.cpu.iew.wb_producers::1 4832 # num instructions producing a value 561system.cpu.iew.wb_producers::total 9606 # num instructions producing a value 562system.cpu.iew.wb_consumers::0 6221 # num instructions consuming a value 563system.cpu.iew.wb_consumers::1 6338 # num instructions consuming a value 564system.cpu.iew.wb_consumers::total 12559 # num instructions consuming a value 565system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ 566system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ 567system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ 568system.cpu.iew.wb_rate::0 0.192387 # insts written-back per cycle 569system.cpu.iew.wb_rate::1 0.194619 # insts written-back per cycle 570system.cpu.iew.wb_rate::total 0.387006 # insts written-back per cycle 571system.cpu.iew.wb_fanout::0 0.767401 # average fanout of values written-back 572system.cpu.iew.wb_fanout::1 0.762386 # average fanout of values written-back 573system.cpu.iew.wb_fanout::total 0.764870 # average fanout of values written-back 574system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ 575system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ 576system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ 577system.cpu.commit.commitSquashedInsts 13802 # The number of squashed insts skipped by commit 578system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards 579system.cpu.commit.branchMispredicts 1144 # The number of times a branch was mispredicted 580system.cpu.commit.committed_per_cycle::samples 28205 # Number of insts commited each cycle 581system.cpu.commit.committed_per_cycle::mean 0.453076 # Number of insts commited each cycle 582system.cpu.commit.committed_per_cycle::stdev 1.225022 # Number of insts commited each cycle 583system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 584system.cpu.commit.committed_per_cycle::0 22496 79.76% 79.76% # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::1 3008 10.66% 90.42% # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::2 1125 3.99% 94.41% # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::3 504 1.79% 96.20% # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::4 336 1.19% 97.39% # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::5 259 0.92% 98.31% # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::6 191 0.68% 98.99% # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::7 64 0.23% 99.21% # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::8 222 0.79% 100.00% # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::total 28205 # Number of insts commited each cycle 597system.cpu.commit.committedInsts::0 6390 # Number of instructions committed 598system.cpu.commit.committedInsts::1 6389 # Number of instructions committed 599system.cpu.commit.committedInsts::total 12779 # Number of instructions committed 600system.cpu.commit.committedOps::0 6390 # Number of ops (including micro ops) committed 601system.cpu.commit.committedOps::1 6389 # Number of ops (including micro ops) committed 602system.cpu.commit.committedOps::total 12779 # Number of ops (including micro ops) committed 603system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 604system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed 605system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed 606system.cpu.commit.refs::0 2048 # Number of memory references committed 607system.cpu.commit.refs::1 2048 # Number of memory references committed 608system.cpu.commit.refs::total 4096 # Number of memory references committed 609system.cpu.commit.loads::0 1183 # Number of loads committed 610system.cpu.commit.loads::1 1183 # Number of loads committed 611system.cpu.commit.loads::total 2366 # Number of loads committed 612system.cpu.commit.membars::0 0 # Number of memory barriers committed 613system.cpu.commit.membars::1 0 # Number of memory barriers committed 614system.cpu.commit.membars::total 0 # Number of memory barriers committed 615system.cpu.commit.branches::0 1050 # Number of branches committed 616system.cpu.commit.branches::1 1050 # Number of branches committed 617system.cpu.commit.branches::total 2100 # Number of branches committed 618system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. 619system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. 620system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. 621system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions. 622system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions. 623system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions. 624system.cpu.commit.function_calls::0 127 # Number of function calls committed. 625system.cpu.commit.function_calls::1 127 # Number of function calls committed. 626system.cpu.commit.function_calls::total 254 # Number of function calls committed. 627system.cpu.commit.bw_lim_events 222 # number cycles where commit BW limit reached 628system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits 629system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits 630system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits 631system.cpu.rob.rob_reads 130213 # The number of ROB reads 632system.cpu.rob.rob_writes 55909 # The number of ROB writes 633system.cpu.timesIdled 371 # Number of times that the entire CPU went into an idle state and unscheduled itself 634system.cpu.idleCycles 20139 # Total number of cycles that the CPU has spent unscheduled due to idling 635system.cpu.committedInsts::0 6373 # Number of Instructions Simulated 636system.cpu.committedInsts::1 6372 # Number of Instructions Simulated 637system.cpu.committedOps::0 6373 # Number of Ops (including micro ops) Simulated 638system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated 639system.cpu.committedInsts_total 12745 # Number of Instructions Simulated 640system.cpu.cpi::0 7.593284 # CPI: Cycles Per Instruction 641system.cpu.cpi::1 7.594476 # CPI: Cycles Per Instruction 642system.cpu.cpi_total 3.796940 # CPI: Total CPI of All Threads 643system.cpu.ipc::0 0.131695 # IPC: Instructions Per Cycle 644system.cpu.ipc::1 0.131675 # IPC: Instructions Per Cycle 645system.cpu.ipc_total 0.263370 # IPC: Total IPC of All Threads 646system.cpu.int_regfile_reads 25300 # number of integer regfile reads 647system.cpu.int_regfile_writes 14121 # number of integer regfile writes 648system.cpu.fp_regfile_reads 16 # number of floating regfile reads 649system.cpu.fp_regfile_writes 4 # number of floating regfile writes 650system.cpu.misc_regfile_reads 2 # number of misc regfile reads 651system.cpu.misc_regfile_writes 2 # number of misc regfile writes 652system.cpu.toL2Bus.throughput 2581637081 # Throughput (bytes/s) 653system.cpu.toL2Bus.trans_dist::ReadReq 830 # Transaction distribution 654system.cpu.toL2Bus.trans_dist::ReadResp 830 # Transaction distribution 655system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution 656system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution 657system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252 # Packet count per connected master and slave (bytes) 658system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700 # Packet count per connected master and slave (bytes) 659system.cpu.toL2Bus.pkt_count::total 1952 # Packet count per connected master and slave (bytes) 660system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40064 # Cumulative packet size per connected master and slave (bytes) 661system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22400 # Cumulative packet size per connected master and slave (bytes) 662system.cpu.toL2Bus.tot_pkt_size::total 62464 # Cumulative packet size per connected master and slave (bytes) 663system.cpu.toL2Bus.data_through_bus 62464 # Total data (bytes) 664system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 665system.cpu.toL2Bus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) 666system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) 667system.cpu.toL2Bus.respLayer0.occupancy 1025000 # Layer occupancy (ticks) 668system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%) 669system.cpu.toL2Bus.respLayer1.occupancy 559750 # Layer occupancy (ticks) 670system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 671system.cpu.icache.tags.replacements::0 6 # number of replacements 672system.cpu.icache.tags.replacements::1 0 # number of replacements 673system.cpu.icache.tags.replacements::total 6 # number of replacements 674system.cpu.icache.tags.tagsinuse 312.920483 # Cycle average of tags in use 675system.cpu.icache.tags.total_refs 4342 # Total number of references to valid blocks. 676system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks. 677system.cpu.icache.tags.avg_refs 6.936102 # Average number of references to valid blocks. 678system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 679system.cpu.icache.tags.occ_blocks::cpu.inst 312.920483 # Average occupied blocks per requestor 680system.cpu.icache.tags.occ_percent::cpu.inst 0.152793 # Average percentage of cache occupancy 681system.cpu.icache.tags.occ_percent::total 0.152793 # Average percentage of cache occupancy 682system.cpu.icache.tags.occ_task_id_blocks::1024 620 # Occupied blocks per task id 683system.cpu.icache.tags.age_task_id_blocks_1024::0 263 # Occupied blocks per task id 684system.cpu.icache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id 685system.cpu.icache.tags.occ_task_id_percent::1024 0.302734 # Percentage of cache occupancy per task id 686system.cpu.icache.tags.tag_accesses 11372 # Number of tag accesses 687system.cpu.icache.tags.data_accesses 11372 # Number of data accesses 688system.cpu.icache.ReadReq_hits::cpu.inst 4342 # number of ReadReq hits 689system.cpu.icache.ReadReq_hits::total 4342 # number of ReadReq hits 690system.cpu.icache.demand_hits::cpu.inst 4342 # number of demand (read+write) hits 691system.cpu.icache.demand_hits::total 4342 # number of demand (read+write) hits 692system.cpu.icache.overall_hits::cpu.inst 4342 # number of overall hits 693system.cpu.icache.overall_hits::total 4342 # number of overall hits 694system.cpu.icache.ReadReq_misses::cpu.inst 1031 # number of ReadReq misses 695system.cpu.icache.ReadReq_misses::total 1031 # number of ReadReq misses 696system.cpu.icache.demand_misses::cpu.inst 1031 # number of demand (read+write) misses 697system.cpu.icache.demand_misses::total 1031 # number of demand (read+write) misses 698system.cpu.icache.overall_misses::cpu.inst 1031 # number of overall misses 699system.cpu.icache.overall_misses::total 1031 # number of overall misses 700system.cpu.icache.ReadReq_miss_latency::cpu.inst 69474496 # number of ReadReq miss cycles 701system.cpu.icache.ReadReq_miss_latency::total 69474496 # number of ReadReq miss cycles 702system.cpu.icache.demand_miss_latency::cpu.inst 69474496 # number of demand (read+write) miss cycles 703system.cpu.icache.demand_miss_latency::total 69474496 # number of demand (read+write) miss cycles 704system.cpu.icache.overall_miss_latency::cpu.inst 69474496 # number of overall miss cycles 705system.cpu.icache.overall_miss_latency::total 69474496 # number of overall miss cycles 706system.cpu.icache.ReadReq_accesses::cpu.inst 5373 # number of ReadReq accesses(hits+misses) 707system.cpu.icache.ReadReq_accesses::total 5373 # number of ReadReq accesses(hits+misses) 708system.cpu.icache.demand_accesses::cpu.inst 5373 # number of demand (read+write) accesses 709system.cpu.icache.demand_accesses::total 5373 # number of demand (read+write) accesses 710system.cpu.icache.overall_accesses::cpu.inst 5373 # number of overall (read+write) accesses 711system.cpu.icache.overall_accesses::total 5373 # number of overall (read+write) accesses 712system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191885 # miss rate for ReadReq accesses 713system.cpu.icache.ReadReq_miss_rate::total 0.191885 # miss rate for ReadReq accesses 714system.cpu.icache.demand_miss_rate::cpu.inst 0.191885 # miss rate for demand accesses 715system.cpu.icache.demand_miss_rate::total 0.191885 # miss rate for demand accesses 716system.cpu.icache.overall_miss_rate::cpu.inst 0.191885 # miss rate for overall accesses 717system.cpu.icache.overall_miss_rate::total 0.191885 # miss rate for overall accesses 718system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67385.544132 # average ReadReq miss latency 719system.cpu.icache.ReadReq_avg_miss_latency::total 67385.544132 # average ReadReq miss latency 720system.cpu.icache.demand_avg_miss_latency::cpu.inst 67385.544132 # average overall miss latency 721system.cpu.icache.demand_avg_miss_latency::total 67385.544132 # average overall miss latency 722system.cpu.icache.overall_avg_miss_latency::cpu.inst 67385.544132 # average overall miss latency 723system.cpu.icache.overall_avg_miss_latency::total 67385.544132 # average overall miss latency 724system.cpu.icache.blocked_cycles::no_mshrs 2515 # number of cycles access was blocked 725system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 726system.cpu.icache.blocked::no_mshrs 60 # number of cycles access was blocked 727system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 728system.cpu.icache.avg_blocked_cycles::no_mshrs 41.916667 # average number of cycles each access was blocked 729system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 730system.cpu.icache.fast_writes 0 # number of fast writes performed 731system.cpu.icache.cache_copies 0 # number of cache copies performed 732system.cpu.icache.ReadReq_mshr_hits::cpu.inst 405 # number of ReadReq MSHR hits 733system.cpu.icache.ReadReq_mshr_hits::total 405 # number of ReadReq MSHR hits 734system.cpu.icache.demand_mshr_hits::cpu.inst 405 # number of demand (read+write) MSHR hits 735system.cpu.icache.demand_mshr_hits::total 405 # number of demand (read+write) MSHR hits 736system.cpu.icache.overall_mshr_hits::cpu.inst 405 # number of overall MSHR hits 737system.cpu.icache.overall_mshr_hits::total 405 # number of overall MSHR hits 738system.cpu.icache.ReadReq_mshr_misses::cpu.inst 626 # number of ReadReq MSHR misses 739system.cpu.icache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses 740system.cpu.icache.demand_mshr_misses::cpu.inst 626 # number of demand (read+write) MSHR misses 741system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses 742system.cpu.icache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses 743system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses 744system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46641746 # number of ReadReq MSHR miss cycles 745system.cpu.icache.ReadReq_mshr_miss_latency::total 46641746 # number of ReadReq MSHR miss cycles 746system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46641746 # number of demand (read+write) MSHR miss cycles 747system.cpu.icache.demand_mshr_miss_latency::total 46641746 # number of demand (read+write) MSHR miss cycles 748system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46641746 # number of overall MSHR miss cycles 749system.cpu.icache.overall_mshr_miss_latency::total 46641746 # number of overall MSHR miss cycles 750system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116508 # mshr miss rate for ReadReq accesses 751system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116508 # mshr miss rate for ReadReq accesses 752system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116508 # mshr miss rate for demand accesses 753system.cpu.icache.demand_mshr_miss_rate::total 0.116508 # mshr miss rate for demand accesses 754system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116508 # mshr miss rate for overall accesses 755system.cpu.icache.overall_mshr_miss_rate::total 0.116508 # mshr miss rate for overall accesses 756system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74507.581470 # average ReadReq mshr miss latency 757system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74507.581470 # average ReadReq mshr miss latency 758system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74507.581470 # average overall mshr miss latency 759system.cpu.icache.demand_avg_mshr_miss_latency::total 74507.581470 # average overall mshr miss latency 760system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74507.581470 # average overall mshr miss latency 761system.cpu.icache.overall_avg_mshr_miss_latency::total 74507.581470 # average overall mshr miss latency 762system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 763system.cpu.l2cache.tags.replacements::0 0 # number of replacements 764system.cpu.l2cache.tags.replacements::1 0 # number of replacements 765system.cpu.l2cache.tags.replacements::total 0 # number of replacements 766system.cpu.l2cache.tags.tagsinuse 433.824891 # Cycle average of tags in use 767system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 768system.cpu.l2cache.tags.sampled_refs 828 # Sample count of references to valid blocks. 769system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. 770system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 771system.cpu.l2cache.tags.occ_blocks::cpu.inst 313.437243 # Average occupied blocks per requestor 772system.cpu.l2cache.tags.occ_blocks::cpu.data 120.387648 # Average occupied blocks per requestor 773system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009565 # Average percentage of cache occupancy 774system.cpu.l2cache.tags.occ_percent::cpu.data 0.003674 # Average percentage of cache occupancy 775system.cpu.l2cache.tags.occ_percent::total 0.013239 # Average percentage of cache occupancy 776system.cpu.l2cache.tags.occ_task_id_blocks::1024 828 # Occupied blocks per task id 777system.cpu.l2cache.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id 778system.cpu.l2cache.tags.age_task_id_blocks_1024::1 493 # Occupied blocks per task id 779system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025269 # Percentage of cache occupancy per task id 780system.cpu.l2cache.tags.tag_accesses 8782 # Number of tag accesses 781system.cpu.l2cache.tags.data_accesses 8782 # Number of data accesses 782system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 783system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 784system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 785system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 786system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 787system.cpu.l2cache.overall_hits::total 2 # number of overall hits 788system.cpu.l2cache.ReadReq_misses::cpu.inst 624 # number of ReadReq misses 789system.cpu.l2cache.ReadReq_misses::cpu.data 204 # number of ReadReq misses 790system.cpu.l2cache.ReadReq_misses::total 828 # number of ReadReq misses 791system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses 792system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses 793system.cpu.l2cache.demand_misses::cpu.inst 624 # number of demand (read+write) misses 794system.cpu.l2cache.demand_misses::cpu.data 350 # number of demand (read+write) misses 795system.cpu.l2cache.demand_misses::total 974 # number of demand (read+write) misses 796system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses 797system.cpu.l2cache.overall_misses::cpu.data 350 # number of overall misses 798system.cpu.l2cache.overall_misses::total 974 # number of overall misses 799system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45992000 # number of ReadReq miss cycles 800system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16232250 # number of ReadReq miss cycles 801system.cpu.l2cache.ReadReq_miss_latency::total 62224250 # number of ReadReq miss cycles 802system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11972000 # number of ReadExReq miss cycles 803system.cpu.l2cache.ReadExReq_miss_latency::total 11972000 # number of ReadExReq miss cycles 804system.cpu.l2cache.demand_miss_latency::cpu.inst 45992000 # number of demand (read+write) miss cycles 805system.cpu.l2cache.demand_miss_latency::cpu.data 28204250 # number of demand (read+write) miss cycles 806system.cpu.l2cache.demand_miss_latency::total 74196250 # number of demand (read+write) miss cycles 807system.cpu.l2cache.overall_miss_latency::cpu.inst 45992000 # number of overall miss cycles 808system.cpu.l2cache.overall_miss_latency::cpu.data 28204250 # number of overall miss cycles 809system.cpu.l2cache.overall_miss_latency::total 74196250 # number of overall miss cycles 810system.cpu.l2cache.ReadReq_accesses::cpu.inst 626 # number of ReadReq accesses(hits+misses) 811system.cpu.l2cache.ReadReq_accesses::cpu.data 204 # number of ReadReq accesses(hits+misses) 812system.cpu.l2cache.ReadReq_accesses::total 830 # number of ReadReq accesses(hits+misses) 813system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) 814system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) 815system.cpu.l2cache.demand_accesses::cpu.inst 626 # number of demand (read+write) accesses 816system.cpu.l2cache.demand_accesses::cpu.data 350 # number of demand (read+write) accesses 817system.cpu.l2cache.demand_accesses::total 976 # number of demand (read+write) accesses 818system.cpu.l2cache.overall_accesses::cpu.inst 626 # number of overall (read+write) accesses 819system.cpu.l2cache.overall_accesses::cpu.data 350 # number of overall (read+write) accesses 820system.cpu.l2cache.overall_accesses::total 976 # number of overall (read+write) accesses 821system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses 822system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 823system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses 824system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 825system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 826system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses 827system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 828system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses 829system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses 830system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 831system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses 832system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73705.128205 # average ReadReq miss latency 833system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79569.852941 # average ReadReq miss latency 834system.cpu.l2cache.ReadReq_avg_miss_latency::total 75150.060386 # average ReadReq miss latency 835system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82000 # average ReadExReq miss latency 836system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82000 # average ReadExReq miss latency 837system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73705.128205 # average overall miss latency 838system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80583.571429 # average overall miss latency 839system.cpu.l2cache.demand_avg_miss_latency::total 76176.848049 # average overall miss latency 840system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73705.128205 # average overall miss latency 841system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80583.571429 # average overall miss latency 842system.cpu.l2cache.overall_avg_miss_latency::total 76176.848049 # average overall miss latency 843system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 844system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 845system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 846system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 847system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 848system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 849system.cpu.l2cache.fast_writes 0 # number of fast writes performed 850system.cpu.l2cache.cache_copies 0 # number of cache copies performed 851system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses 852system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses 853system.cpu.l2cache.ReadReq_mshr_misses::total 828 # number of ReadReq MSHR misses 854system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses 855system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses 856system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses 857system.cpu.l2cache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses 858system.cpu.l2cache.demand_mshr_misses::total 974 # number of demand (read+write) MSHR misses 859system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses 860system.cpu.l2cache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses 861system.cpu.l2cache.overall_mshr_misses::total 974 # number of overall MSHR misses 862system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38226500 # number of ReadReq MSHR miss cycles 863system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13721250 # number of ReadReq MSHR miss cycles 864system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51947750 # number of ReadReq MSHR miss cycles 865system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10170000 # number of ReadExReq MSHR miss cycles 866system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10170000 # number of ReadExReq MSHR miss cycles 867system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38226500 # number of demand (read+write) MSHR miss cycles 868system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23891250 # number of demand (read+write) MSHR miss cycles 869system.cpu.l2cache.demand_mshr_miss_latency::total 62117750 # number of demand (read+write) MSHR miss cycles 870system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38226500 # number of overall MSHR miss cycles 871system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23891250 # number of overall MSHR miss cycles 872system.cpu.l2cache.overall_mshr_miss_latency::total 62117750 # number of overall MSHR miss cycles 873system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses 874system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 875system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses 876system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 877system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 878system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses 879system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 880system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses 881system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses 882system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 883system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses 884system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61260.416667 # average ReadReq mshr miss latency 885system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67261.029412 # average ReadReq mshr miss latency 886system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62738.828502 # average ReadReq mshr miss latency 887system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69657.534247 # average ReadExReq mshr miss latency 888system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69657.534247 # average ReadExReq mshr miss latency 889system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61260.416667 # average overall mshr miss latency 890system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68260.714286 # average overall mshr miss latency 891system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63775.924025 # average overall mshr miss latency 892system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61260.416667 # average overall mshr miss latency 893system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68260.714286 # average overall mshr miss latency 894system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63775.924025 # average overall mshr miss latency 895system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 896system.cpu.dcache.tags.replacements::0 0 # number of replacements 897system.cpu.dcache.tags.replacements::1 0 # number of replacements 898system.cpu.dcache.tags.replacements::total 0 # number of replacements 899system.cpu.dcache.tags.tagsinuse 213.987948 # Cycle average of tags in use 900system.cpu.dcache.tags.total_refs 4461 # Total number of references to valid blocks. 901system.cpu.dcache.tags.sampled_refs 350 # Sample count of references to valid blocks. 902system.cpu.dcache.tags.avg_refs 12.745714 # Average number of references to valid blocks. 903system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 904system.cpu.dcache.tags.occ_blocks::cpu.data 213.987948 # Average occupied blocks per requestor 905system.cpu.dcache.tags.occ_percent::cpu.data 0.052243 # Average percentage of cache occupancy 906system.cpu.dcache.tags.occ_percent::total 0.052243 # Average percentage of cache occupancy 907system.cpu.dcache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id 908system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id 909system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 910system.cpu.dcache.tags.occ_task_id_percent::1024 0.085449 # Percentage of cache occupancy per task id 911system.cpu.dcache.tags.tag_accesses 11334 # Number of tag accesses 912system.cpu.dcache.tags.data_accesses 11334 # Number of data accesses 913system.cpu.dcache.ReadReq_hits::cpu.data 3441 # number of ReadReq hits 914system.cpu.dcache.ReadReq_hits::total 3441 # number of ReadReq hits 915system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits 916system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits 917system.cpu.dcache.demand_hits::cpu.data 4461 # number of demand (read+write) hits 918system.cpu.dcache.demand_hits::total 4461 # number of demand (read+write) hits 919system.cpu.dcache.overall_hits::cpu.data 4461 # number of overall hits 920system.cpu.dcache.overall_hits::total 4461 # number of overall hits 921system.cpu.dcache.ReadReq_misses::cpu.data 321 # number of ReadReq misses 922system.cpu.dcache.ReadReq_misses::total 321 # number of ReadReq misses 923system.cpu.dcache.WriteReq_misses::cpu.data 710 # number of WriteReq misses 924system.cpu.dcache.WriteReq_misses::total 710 # number of WriteReq misses 925system.cpu.dcache.demand_misses::cpu.data 1031 # number of demand (read+write) misses 926system.cpu.dcache.demand_misses::total 1031 # number of demand (read+write) misses 927system.cpu.dcache.overall_misses::cpu.data 1031 # number of overall misses 928system.cpu.dcache.overall_misses::total 1031 # number of overall misses 929system.cpu.dcache.ReadReq_miss_latency::cpu.data 22966250 # number of ReadReq miss cycles 930system.cpu.dcache.ReadReq_miss_latency::total 22966250 # number of ReadReq miss cycles 931system.cpu.dcache.WriteReq_miss_latency::cpu.data 51761962 # number of WriteReq miss cycles 932system.cpu.dcache.WriteReq_miss_latency::total 51761962 # number of WriteReq miss cycles 933system.cpu.dcache.demand_miss_latency::cpu.data 74728212 # number of demand (read+write) miss cycles 934system.cpu.dcache.demand_miss_latency::total 74728212 # number of demand (read+write) miss cycles 935system.cpu.dcache.overall_miss_latency::cpu.data 74728212 # number of overall miss cycles 936system.cpu.dcache.overall_miss_latency::total 74728212 # number of overall miss cycles 937system.cpu.dcache.ReadReq_accesses::cpu.data 3762 # number of ReadReq accesses(hits+misses) 938system.cpu.dcache.ReadReq_accesses::total 3762 # number of ReadReq accesses(hits+misses) 939system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) 940system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) 941system.cpu.dcache.demand_accesses::cpu.data 5492 # number of demand (read+write) accesses 942system.cpu.dcache.demand_accesses::total 5492 # number of demand (read+write) accesses 943system.cpu.dcache.overall_accesses::cpu.data 5492 # number of overall (read+write) accesses 944system.cpu.dcache.overall_accesses::total 5492 # number of overall (read+write) accesses 945system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085327 # miss rate for ReadReq accesses 946system.cpu.dcache.ReadReq_miss_rate::total 0.085327 # miss rate for ReadReq accesses 947system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.410405 # miss rate for WriteReq accesses 948system.cpu.dcache.WriteReq_miss_rate::total 0.410405 # miss rate for WriteReq accesses 949system.cpu.dcache.demand_miss_rate::cpu.data 0.187728 # miss rate for demand accesses 950system.cpu.dcache.demand_miss_rate::total 0.187728 # miss rate for demand accesses 951system.cpu.dcache.overall_miss_rate::cpu.data 0.187728 # miss rate for overall accesses 952system.cpu.dcache.overall_miss_rate::total 0.187728 # miss rate for overall accesses 953system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71545.950156 # average ReadReq miss latency 954system.cpu.dcache.ReadReq_avg_miss_latency::total 71545.950156 # average ReadReq miss latency 955system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72904.171831 # average WriteReq miss latency 956system.cpu.dcache.WriteReq_avg_miss_latency::total 72904.171831 # average WriteReq miss latency 957system.cpu.dcache.demand_avg_miss_latency::cpu.data 72481.291950 # average overall miss latency 958system.cpu.dcache.demand_avg_miss_latency::total 72481.291950 # average overall miss latency 959system.cpu.dcache.overall_avg_miss_latency::cpu.data 72481.291950 # average overall miss latency 960system.cpu.dcache.overall_avg_miss_latency::total 72481.291950 # average overall miss latency 961system.cpu.dcache.blocked_cycles::no_mshrs 4374 # number of cycles access was blocked 962system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 963system.cpu.dcache.blocked::no_mshrs 106 # number of cycles access was blocked 964system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 965system.cpu.dcache.avg_blocked_cycles::no_mshrs 41.264151 # average number of cycles each access was blocked 966system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 967system.cpu.dcache.fast_writes 0 # number of fast writes performed 968system.cpu.dcache.cache_copies 0 # number of cache copies performed 969system.cpu.dcache.ReadReq_mshr_hits::cpu.data 117 # number of ReadReq MSHR hits 970system.cpu.dcache.ReadReq_mshr_hits::total 117 # number of ReadReq MSHR hits 971system.cpu.dcache.WriteReq_mshr_hits::cpu.data 564 # number of WriteReq MSHR hits 972system.cpu.dcache.WriteReq_mshr_hits::total 564 # number of WriteReq MSHR hits 973system.cpu.dcache.demand_mshr_hits::cpu.data 681 # number of demand (read+write) MSHR hits 974system.cpu.dcache.demand_mshr_hits::total 681 # number of demand (read+write) MSHR hits 975system.cpu.dcache.overall_mshr_hits::cpu.data 681 # number of overall MSHR hits 976system.cpu.dcache.overall_mshr_hits::total 681 # number of overall MSHR hits 977system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses 978system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses 979system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses 980system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses 981system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses 982system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 983system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses 984system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses 985system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16444750 # number of ReadReq MSHR miss cycles 986system.cpu.dcache.ReadReq_mshr_miss_latency::total 16444750 # number of ReadReq MSHR miss cycles 987system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12120496 # number of WriteReq MSHR miss cycles 988system.cpu.dcache.WriteReq_mshr_miss_latency::total 12120496 # number of WriteReq MSHR miss cycles 989system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28565246 # number of demand (read+write) MSHR miss cycles 990system.cpu.dcache.demand_mshr_miss_latency::total 28565246 # number of demand (read+write) MSHR miss cycles 991system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28565246 # number of overall MSHR miss cycles 992system.cpu.dcache.overall_mshr_miss_latency::total 28565246 # number of overall MSHR miss cycles 993system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054226 # mshr miss rate for ReadReq accesses 994system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054226 # mshr miss rate for ReadReq accesses 995system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 996system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 997system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063729 # mshr miss rate for demand accesses 998system.cpu.dcache.demand_mshr_miss_rate::total 0.063729 # mshr miss rate for demand accesses 999system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063729 # mshr miss rate for overall accesses 1000system.cpu.dcache.overall_mshr_miss_rate::total 0.063729 # mshr miss rate for overall accesses 1001system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80611.519608 # average ReadReq mshr miss latency 1002system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80611.519608 # average ReadReq mshr miss latency 1003system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83017.095890 # average WriteReq mshr miss latency 1004system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83017.095890 # average WriteReq mshr miss latency 1005system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81614.988571 # average overall mshr miss latency 1006system.cpu.dcache.demand_avg_mshr_miss_latency::total 81614.988571 # average overall mshr miss latency 1007system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81614.988571 # average overall mshr miss latency 1008system.cpu.dcache.overall_avg_mshr_miss_latency::total 81614.988571 # average overall mshr miss latency 1009system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1010 1011---------- End Simulation Statistics ---------- 1012