config.ini revision 9988
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= 26symbolfile= 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.clk_domain] 37type=SrcClockDomain 38clock=1000 39eventq_index=0 40voltage_domain=system.voltage_domain 41 42[system.cpu] 43type=DerivO3CPU 44children=branchPred dcache dtb fuPool icache interrupts isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1 45LFSTSize=1024 46LQEntries=32 47LSQCheckLoads=true 48LSQDepCheckShift=4 49SQEntries=32 50SSITSize=1024 51activity=0 52backComSize=5 53branchPred=system.cpu.branchPred 54cachePorts=200 55checker=Null 56clk_domain=system.cpu_clk_domain 57commitToDecodeDelay=1 58commitToFetchDelay=1 59commitToIEWDelay=1 60commitToRenameDelay=1 61commitWidth=8 62cpu_id=0 63decodeToFetchDelay=1 64decodeToRenameDelay=1 65decodeWidth=8 66dispatchWidth=8 67do_checkpoint_insts=true 68do_quiesce=true 69do_statistics_insts=true 70dtb=system.cpu.dtb 71eventq_index=0 72fetchBufferSize=64 73fetchToDecodeDelay=1 74fetchTrapLatency=1 75fetchWidth=8 76forwardComSize=5 77fuPool=system.cpu.fuPool 78function_trace=false 79function_trace_start=0 80iewToCommitDelay=1 81iewToDecodeDelay=1 82iewToFetchDelay=1 83iewToRenameDelay=1 84interrupts=system.cpu.interrupts 85isa=system.cpu.isa0 system.cpu.isa1 86issueToExecuteDelay=1 87issueWidth=8 88itb=system.cpu.itb 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=false 94numIQEntries=64 95numPhysCCRegs=0 96numPhysFloatRegs=256 97numPhysIntRegs=256 98numROBEntries=192 99numRobs=1 100numThreads=2 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108simpoint_start_insts= 109smtCommitPolicy=RoundRobin 110smtFetchPolicy=SingleThread 111smtIQPolicy=Partitioned 112smtIQThreshold=100 113smtLSQPolicy=Partitioned 114smtLSQThreshold=100 115smtNumFetchingThreads=1 116smtROBPolicy=Partitioned 117smtROBThreshold=100 118squashWidth=8 119store_set_clear_period=250000 120switched_out=false 121system=system 122tracer=system.cpu.tracer 123trapLatency=13 124wbDepth=1 125wbWidth=8 126workload=system.cpu.workload0 system.cpu.workload1 127dcache_port=system.cpu.dcache.cpu_side 128icache_port=system.cpu.icache.cpu_side 129 130[system.cpu.branchPred] 131type=BranchPredictor 132BTBEntries=4096 133BTBTagSize=16 134RASSize=16 135choiceCtrBits=2 136choicePredictorSize=8192 137eventq_index=0 138globalCtrBits=2 139globalPredictorSize=8192 140instShiftAmt=2 141localCtrBits=2 142localHistoryTableSize=2048 143localPredictorSize=2048 144numThreads=2 145predType=tournament 146 147[system.cpu.dcache] 148type=BaseCache 149children=tags 150addr_ranges=0:18446744073709551615 151assoc=2 152clk_domain=system.cpu_clk_domain 153eventq_index=0 154forward_snoops=true 155hit_latency=2 156is_top_level=true 157max_miss_count=0 158mshrs=4 159prefetch_on_access=false 160prefetcher=Null 161response_latency=2 162size=262144 163system=system 164tags=system.cpu.dcache.tags 165tgts_per_mshr=20 166two_queue=false 167write_buffers=8 168cpu_side=system.cpu.dcache_port 169mem_side=system.cpu.toL2Bus.slave[1] 170 171[system.cpu.dcache.tags] 172type=LRU 173assoc=2 174block_size=64 175clk_domain=system.cpu_clk_domain 176eventq_index=0 177hit_latency=2 178size=262144 179 180[system.cpu.dtb] 181type=AlphaTLB 182eventq_index=0 183size=64 184 185[system.cpu.fuPool] 186type=FUPool 187children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 188FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 189eventq_index=0 190 191[system.cpu.fuPool.FUList0] 192type=FUDesc 193children=opList 194count=6 195eventq_index=0 196opList=system.cpu.fuPool.FUList0.opList 197 198[system.cpu.fuPool.FUList0.opList] 199type=OpDesc 200eventq_index=0 201issueLat=1 202opClass=IntAlu 203opLat=1 204 205[system.cpu.fuPool.FUList1] 206type=FUDesc 207children=opList0 opList1 208count=2 209eventq_index=0 210opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 211 212[system.cpu.fuPool.FUList1.opList0] 213type=OpDesc 214eventq_index=0 215issueLat=1 216opClass=IntMult 217opLat=3 218 219[system.cpu.fuPool.FUList1.opList1] 220type=OpDesc 221eventq_index=0 222issueLat=19 223opClass=IntDiv 224opLat=20 225 226[system.cpu.fuPool.FUList2] 227type=FUDesc 228children=opList0 opList1 opList2 229count=4 230eventq_index=0 231opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 232 233[system.cpu.fuPool.FUList2.opList0] 234type=OpDesc 235eventq_index=0 236issueLat=1 237opClass=FloatAdd 238opLat=2 239 240[system.cpu.fuPool.FUList2.opList1] 241type=OpDesc 242eventq_index=0 243issueLat=1 244opClass=FloatCmp 245opLat=2 246 247[system.cpu.fuPool.FUList2.opList2] 248type=OpDesc 249eventq_index=0 250issueLat=1 251opClass=FloatCvt 252opLat=2 253 254[system.cpu.fuPool.FUList3] 255type=FUDesc 256children=opList0 opList1 opList2 257count=2 258eventq_index=0 259opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 260 261[system.cpu.fuPool.FUList3.opList0] 262type=OpDesc 263eventq_index=0 264issueLat=1 265opClass=FloatMult 266opLat=4 267 268[system.cpu.fuPool.FUList3.opList1] 269type=OpDesc 270eventq_index=0 271issueLat=12 272opClass=FloatDiv 273opLat=12 274 275[system.cpu.fuPool.FUList3.opList2] 276type=OpDesc 277eventq_index=0 278issueLat=24 279opClass=FloatSqrt 280opLat=24 281 282[system.cpu.fuPool.FUList4] 283type=FUDesc 284children=opList 285count=0 286eventq_index=0 287opList=system.cpu.fuPool.FUList4.opList 288 289[system.cpu.fuPool.FUList4.opList] 290type=OpDesc 291eventq_index=0 292issueLat=1 293opClass=MemRead 294opLat=1 295 296[system.cpu.fuPool.FUList5] 297type=FUDesc 298children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 299count=4 300eventq_index=0 301opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 302 303[system.cpu.fuPool.FUList5.opList00] 304type=OpDesc 305eventq_index=0 306issueLat=1 307opClass=SimdAdd 308opLat=1 309 310[system.cpu.fuPool.FUList5.opList01] 311type=OpDesc 312eventq_index=0 313issueLat=1 314opClass=SimdAddAcc 315opLat=1 316 317[system.cpu.fuPool.FUList5.opList02] 318type=OpDesc 319eventq_index=0 320issueLat=1 321opClass=SimdAlu 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList03] 325type=OpDesc 326eventq_index=0 327issueLat=1 328opClass=SimdCmp 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList04] 332type=OpDesc 333eventq_index=0 334issueLat=1 335opClass=SimdCvt 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList05] 339type=OpDesc 340eventq_index=0 341issueLat=1 342opClass=SimdMisc 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList06] 346type=OpDesc 347eventq_index=0 348issueLat=1 349opClass=SimdMult 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList07] 353type=OpDesc 354eventq_index=0 355issueLat=1 356opClass=SimdMultAcc 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList08] 360type=OpDesc 361eventq_index=0 362issueLat=1 363opClass=SimdShift 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList09] 367type=OpDesc 368eventq_index=0 369issueLat=1 370opClass=SimdShiftAcc 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList10] 374type=OpDesc 375eventq_index=0 376issueLat=1 377opClass=SimdSqrt 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList11] 381type=OpDesc 382eventq_index=0 383issueLat=1 384opClass=SimdFloatAdd 385opLat=1 386 387[system.cpu.fuPool.FUList5.opList12] 388type=OpDesc 389eventq_index=0 390issueLat=1 391opClass=SimdFloatAlu 392opLat=1 393 394[system.cpu.fuPool.FUList5.opList13] 395type=OpDesc 396eventq_index=0 397issueLat=1 398opClass=SimdFloatCmp 399opLat=1 400 401[system.cpu.fuPool.FUList5.opList14] 402type=OpDesc 403eventq_index=0 404issueLat=1 405opClass=SimdFloatCvt 406opLat=1 407 408[system.cpu.fuPool.FUList5.opList15] 409type=OpDesc 410eventq_index=0 411issueLat=1 412opClass=SimdFloatDiv 413opLat=1 414 415[system.cpu.fuPool.FUList5.opList16] 416type=OpDesc 417eventq_index=0 418issueLat=1 419opClass=SimdFloatMisc 420opLat=1 421 422[system.cpu.fuPool.FUList5.opList17] 423type=OpDesc 424eventq_index=0 425issueLat=1 426opClass=SimdFloatMult 427opLat=1 428 429[system.cpu.fuPool.FUList5.opList18] 430type=OpDesc 431eventq_index=0 432issueLat=1 433opClass=SimdFloatMultAcc 434opLat=1 435 436[system.cpu.fuPool.FUList5.opList19] 437type=OpDesc 438eventq_index=0 439issueLat=1 440opClass=SimdFloatSqrt 441opLat=1 442 443[system.cpu.fuPool.FUList6] 444type=FUDesc 445children=opList 446count=0 447eventq_index=0 448opList=system.cpu.fuPool.FUList6.opList 449 450[system.cpu.fuPool.FUList6.opList] 451type=OpDesc 452eventq_index=0 453issueLat=1 454opClass=MemWrite 455opLat=1 456 457[system.cpu.fuPool.FUList7] 458type=FUDesc 459children=opList0 opList1 460count=4 461eventq_index=0 462opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 463 464[system.cpu.fuPool.FUList7.opList0] 465type=OpDesc 466eventq_index=0 467issueLat=1 468opClass=MemRead 469opLat=1 470 471[system.cpu.fuPool.FUList7.opList1] 472type=OpDesc 473eventq_index=0 474issueLat=1 475opClass=MemWrite 476opLat=1 477 478[system.cpu.fuPool.FUList8] 479type=FUDesc 480children=opList 481count=1 482eventq_index=0 483opList=system.cpu.fuPool.FUList8.opList 484 485[system.cpu.fuPool.FUList8.opList] 486type=OpDesc 487eventq_index=0 488issueLat=3 489opClass=IprAccess 490opLat=3 491 492[system.cpu.icache] 493type=BaseCache 494children=tags 495addr_ranges=0:18446744073709551615 496assoc=2 497clk_domain=system.cpu_clk_domain 498eventq_index=0 499forward_snoops=true 500hit_latency=2 501is_top_level=true 502max_miss_count=0 503mshrs=4 504prefetch_on_access=false 505prefetcher=Null 506response_latency=2 507size=131072 508system=system 509tags=system.cpu.icache.tags 510tgts_per_mshr=20 511two_queue=false 512write_buffers=8 513cpu_side=system.cpu.icache_port 514mem_side=system.cpu.toL2Bus.slave[0] 515 516[system.cpu.icache.tags] 517type=LRU 518assoc=2 519block_size=64 520clk_domain=system.cpu_clk_domain 521eventq_index=0 522hit_latency=2 523size=131072 524 525[system.cpu.interrupts] 526type=AlphaInterrupts 527eventq_index=0 528 529[system.cpu.isa0] 530type=AlphaISA 531eventq_index=0 532 533[system.cpu.isa1] 534type=AlphaISA 535eventq_index=0 536 537[system.cpu.itb] 538type=AlphaTLB 539eventq_index=0 540size=48 541 542[system.cpu.l2cache] 543type=BaseCache 544children=tags 545addr_ranges=0:18446744073709551615 546assoc=8 547clk_domain=system.cpu_clk_domain 548eventq_index=0 549forward_snoops=true 550hit_latency=20 551is_top_level=false 552max_miss_count=0 553mshrs=20 554prefetch_on_access=false 555prefetcher=Null 556response_latency=20 557size=2097152 558system=system 559tags=system.cpu.l2cache.tags 560tgts_per_mshr=12 561two_queue=false 562write_buffers=8 563cpu_side=system.cpu.toL2Bus.master[0] 564mem_side=system.membus.slave[1] 565 566[system.cpu.l2cache.tags] 567type=LRU 568assoc=8 569block_size=64 570clk_domain=system.cpu_clk_domain 571eventq_index=0 572hit_latency=20 573size=2097152 574 575[system.cpu.toL2Bus] 576type=CoherentBus 577clk_domain=system.cpu_clk_domain 578eventq_index=0 579header_cycles=1 580system=system 581use_default_range=false 582width=32 583master=system.cpu.l2cache.cpu_side 584slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 585 586[system.cpu.tracer] 587type=ExeTracer 588eventq_index=0 589 590[system.cpu.workload0] 591type=LiveProcess 592cmd=hello 593cwd= 594egid=100 595env= 596errout=cerr 597euid=100 598eventq_index=0 599executable=tests/test-progs/hello/bin/alpha/linux/hello 600gid=100 601input=cin 602max_stack_size=67108864 603output=cout 604pid=100 605ppid=99 606simpoint=0 607system=system 608uid=100 609 610[system.cpu.workload1] 611type=LiveProcess 612cmd=hello 613cwd= 614egid=100 615env= 616errout=cerr 617euid=100 618eventq_index=0 619executable=tests/test-progs/hello/bin/alpha/linux/hello 620gid=100 621input=cin 622max_stack_size=67108864 623output=cout 624pid=100 625ppid=99 626simpoint=0 627system=system 628uid=100 629 630[system.cpu_clk_domain] 631type=SrcClockDomain 632clock=500 633eventq_index=0 634voltage_domain=system.voltage_domain 635 636[system.membus] 637type=CoherentBus 638clk_domain=system.clk_domain 639eventq_index=0 640header_cycles=1 641system=system 642use_default_range=false 643width=8 644master=system.physmem.port 645slave=system.system_port system.cpu.l2cache.mem_side 646 647[system.physmem] 648type=SimpleDRAM 649activation_limit=4 650addr_mapping=RaBaChCo 651banks_per_rank=8 652burst_length=8 653channels=1 654clk_domain=system.clk_domain 655conf_table_reported=true 656device_bus_width=8 657device_rowbuffer_size=1024 658devices_per_rank=8 659eventq_index=0 660in_addr_map=true 661mem_sched_policy=frfcfs 662null=false 663page_policy=open 664range=0:134217727 665ranks_per_channel=2 666read_buffer_size=32 667static_backend_latency=10000 668static_frontend_latency=10000 669tBURST=5000 670tCL=13750 671tRAS=35000 672tRCD=13750 673tREFI=7800000 674tRFC=300000 675tRP=13750 676tRRD=6250 677tWTR=7500 678tXAW=40000 679write_buffer_size=32 680write_high_thresh_perc=70 681write_low_thresh_perc=0 682port=system.membus.master[0] 683 684[system.voltage_domain] 685type=VoltageDomain 686eventq_index=0 687voltage=1.000000 688 689