1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=System
13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
14boot_osflags=a
15cache_line_size=64
16clk_domain=system.clk_domain
17default_p_state=UNDEFINED
18eventq_index=0
19exit_on_work_items=false
20init_param=0
21kernel=
22kernel_addr_check=true
23load_addr_mask=1099511627775
24load_offset=0
25mem_mode=timing
26mem_ranges=
27memories=system.physmem
28mmap_using_noreserve=false
29multi_thread=true
30num_work_ids=16
31p_state_clk_gate_bins=20
32p_state_clk_gate_max=1000000000000
33p_state_clk_gate_min=1000
34power_model=Null
35readfile=
36symbolfile=
37thermal_components=
38thermal_model=Null
39work_begin_ckpt_count=0
40work_begin_cpu_id_exit=-1
41work_begin_exit_count=0
42work_cpus_ckpt_count=0
43work_end_ckpt_count=0
44work_end_exit_count=0
45work_item_id=-1
46system_port=system.membus.slave[0]
47
48[system.clk_domain]
49type=SrcClockDomain
50clock=1000
51domain_id=-1
52eventq_index=0
53init_perf_level=0
54voltage_domain=system.voltage_domain
55
56[system.cpu]
57type=DerivO3CPU
58children=branchPred dcache dtb fuPool icache interrupts0 interrupts1 isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1
59LFSTSize=1024
60LQEntries=32
61LSQCheckLoads=true
62LSQDepCheckShift=4
63SQEntries=32
64SSITSize=1024
65activity=0
66backComSize=5
67branchPred=system.cpu.branchPred
68cacheStorePorts=200
69checker=Null
70clk_domain=system.cpu_clk_domain
71commitToDecodeDelay=1
72commitToFetchDelay=1
73commitToIEWDelay=1
74commitToRenameDelay=1
75commitWidth=8
76cpu_id=0
77decodeToFetchDelay=1
78decodeToRenameDelay=1
79decodeWidth=8
80default_p_state=UNDEFINED
81dispatchWidth=8
82do_checkpoint_insts=true
83do_quiesce=true
84do_statistics_insts=true
85dtb=system.cpu.dtb
86eventq_index=0
87fetchBufferSize=64
88fetchQueueSize=32
89fetchToDecodeDelay=1
90fetchTrapLatency=1
91fetchWidth=8
92forwardComSize=5
93fuPool=system.cpu.fuPool
94function_trace=false
95function_trace_start=0
96iewToCommitDelay=1
97iewToDecodeDelay=1
98iewToFetchDelay=1
99iewToRenameDelay=1
100interrupts=system.cpu.interrupts0 system.cpu.interrupts1
101isa=system.cpu.isa0 system.cpu.isa1
102issueToExecuteDelay=1
103issueWidth=8
104itb=system.cpu.itb
105max_insts_all_threads=0
106max_insts_any_thread=0
107max_loads_all_threads=0
108max_loads_any_thread=0
109needsTSO=false
110numIQEntries=64
111numPhysCCRegs=0
112numPhysFloatRegs=256
113numPhysIntRegs=256
114numROBEntries=192
115numRobs=1
116numThreads=2
117p_state_clk_gate_bins=20
118p_state_clk_gate_max=1000000000000
119p_state_clk_gate_min=1000
120power_model=Null
121profile=0
122progress_interval=0
123renameToDecodeDelay=1
124renameToFetchDelay=1
125renameToIEWDelay=2
126renameToROBDelay=1
127renameWidth=8
128simpoint_start_insts=
129smtCommitPolicy=RoundRobin
130smtFetchPolicy=SingleThread
131smtIQPolicy=Partitioned
132smtIQThreshold=100
133smtLSQPolicy=Partitioned
134smtLSQThreshold=100
135smtNumFetchingThreads=1
136smtROBPolicy=Partitioned
137smtROBThreshold=100
138socket_id=0
139squashWidth=8
140store_set_clear_period=250000
141switched_out=false
142syscallRetryLatency=10000
143system=system
144tracer=system.cpu.tracer
145trapLatency=13
146wbWidth=8
147workload=system.cpu.workload0 system.cpu.workload1
148dcache_port=system.cpu.dcache.cpu_side
149icache_port=system.cpu.icache.cpu_side
150
151[system.cpu.branchPred]
152type=TournamentBP
153BTBEntries=4096
154BTBTagSize=16
155RASSize=16
156choiceCtrBits=2
157choicePredictorSize=8192
158eventq_index=0
159globalCtrBits=2
160globalPredictorSize=8192
161indirectHashGHR=true
162indirectHashTargets=true
163indirectPathLength=3
164indirectSets=256
165indirectTagSize=16
166indirectWays=2
167instShiftAmt=2
168localCtrBits=2
169localHistoryTableSize=2048
170localPredictorSize=2048
171numThreads=2
172useIndirect=true
173
174[system.cpu.dcache]
175type=Cache
176children=tags
177addr_ranges=0:18446744073709551615:0:0:0:0
178assoc=2
179clk_domain=system.cpu_clk_domain
180clusivity=mostly_incl
181data_latency=2
182default_p_state=UNDEFINED
183demand_mshr_reserve=1
184eventq_index=0
185is_read_only=false
186max_miss_count=0
187mshrs=4
188p_state_clk_gate_bins=20
189p_state_clk_gate_max=1000000000000
190p_state_clk_gate_min=1000
191power_model=Null
192prefetch_on_access=false
193prefetcher=Null
194response_latency=2
195sequential_access=false
196size=262144
197system=system
198tag_latency=2
199tags=system.cpu.dcache.tags
200tgts_per_mshr=20
201write_buffers=8
202writeback_clean=false
203cpu_side=system.cpu.dcache_port
204mem_side=system.cpu.toL2Bus.slave[1]
205
206[system.cpu.dcache.tags]
207type=LRU
208assoc=2
209block_size=64
210clk_domain=system.cpu_clk_domain
211data_latency=2
212default_p_state=UNDEFINED
213eventq_index=0
214p_state_clk_gate_bins=20
215p_state_clk_gate_max=1000000000000
216p_state_clk_gate_min=1000
217power_model=Null
218sequential_access=false
219size=262144
220tag_latency=2
221
222[system.cpu.dtb]
223type=AlphaTLB
224eventq_index=0
225size=64
226
227[system.cpu.fuPool]
228type=FUPool
229children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
230FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
231eventq_index=0
232
233[system.cpu.fuPool.FUList0]
234type=FUDesc
235children=opList
236count=6
237eventq_index=0
238opList=system.cpu.fuPool.FUList0.opList
239
240[system.cpu.fuPool.FUList0.opList]
241type=OpDesc
242eventq_index=0
243opClass=IntAlu
244opLat=1
245pipelined=true
246
247[system.cpu.fuPool.FUList1]
248type=FUDesc
249children=opList0 opList1
250count=2
251eventq_index=0
252opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
253
254[system.cpu.fuPool.FUList1.opList0]
255type=OpDesc
256eventq_index=0
257opClass=IntMult
258opLat=3
259pipelined=true
260
261[system.cpu.fuPool.FUList1.opList1]
262type=OpDesc
263eventq_index=0
264opClass=IntDiv
265opLat=20
266pipelined=false
267
268[system.cpu.fuPool.FUList2]
269type=FUDesc
270children=opList0 opList1 opList2
271count=4
272eventq_index=0
273opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
274
275[system.cpu.fuPool.FUList2.opList0]
276type=OpDesc
277eventq_index=0
278opClass=FloatAdd
279opLat=2
280pipelined=true
281
282[system.cpu.fuPool.FUList2.opList1]
283type=OpDesc
284eventq_index=0
285opClass=FloatCmp
286opLat=2
287pipelined=true
288
289[system.cpu.fuPool.FUList2.opList2]
290type=OpDesc
291eventq_index=0
292opClass=FloatCvt
293opLat=2
294pipelined=true
295
296[system.cpu.fuPool.FUList3]
297type=FUDesc
298children=opList0 opList1 opList2 opList3 opList4
299count=2
300eventq_index=0
301opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
302
303[system.cpu.fuPool.FUList3.opList0]
304type=OpDesc
305eventq_index=0
306opClass=FloatMult
307opLat=4
308pipelined=true
309
310[system.cpu.fuPool.FUList3.opList1]
311type=OpDesc
312eventq_index=0
313opClass=FloatMultAcc
314opLat=5
315pipelined=true
316
317[system.cpu.fuPool.FUList3.opList2]
318type=OpDesc
319eventq_index=0
320opClass=FloatMisc
321opLat=3
322pipelined=true
323
324[system.cpu.fuPool.FUList3.opList3]
325type=OpDesc
326eventq_index=0
327opClass=FloatDiv
328opLat=12
329pipelined=false
330
331[system.cpu.fuPool.FUList3.opList4]
332type=OpDesc
333eventq_index=0
334opClass=FloatSqrt
335opLat=24
336pipelined=false
337
338[system.cpu.fuPool.FUList4]
339type=FUDesc
340children=opList0 opList1
341count=0
342eventq_index=0
343opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
344
345[system.cpu.fuPool.FUList4.opList0]
346type=OpDesc
347eventq_index=0
348opClass=MemRead
349opLat=1
350pipelined=true
351
352[system.cpu.fuPool.FUList4.opList1]
353type=OpDesc
354eventq_index=0
355opClass=FloatMemRead
356opLat=1
357pipelined=true
358
359[system.cpu.fuPool.FUList5]
360type=FUDesc
361children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
362count=4
363eventq_index=0
364opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
365
366[system.cpu.fuPool.FUList5.opList00]
367type=OpDesc
368eventq_index=0
369opClass=SimdAdd
370opLat=1
371pipelined=true
372
373[system.cpu.fuPool.FUList5.opList01]
374type=OpDesc
375eventq_index=0
376opClass=SimdAddAcc
377opLat=1
378pipelined=true
379
380[system.cpu.fuPool.FUList5.opList02]
381type=OpDesc
382eventq_index=0
383opClass=SimdAlu
384opLat=1
385pipelined=true
386
387[system.cpu.fuPool.FUList5.opList03]
388type=OpDesc
389eventq_index=0
390opClass=SimdCmp
391opLat=1
392pipelined=true
393
394[system.cpu.fuPool.FUList5.opList04]
395type=OpDesc
396eventq_index=0
397opClass=SimdCvt
398opLat=1
399pipelined=true
400
401[system.cpu.fuPool.FUList5.opList05]
402type=OpDesc
403eventq_index=0
404opClass=SimdMisc
405opLat=1
406pipelined=true
407
408[system.cpu.fuPool.FUList5.opList06]
409type=OpDesc
410eventq_index=0
411opClass=SimdMult
412opLat=1
413pipelined=true
414
415[system.cpu.fuPool.FUList5.opList07]
416type=OpDesc
417eventq_index=0
418opClass=SimdMultAcc
419opLat=1
420pipelined=true
421
422[system.cpu.fuPool.FUList5.opList08]
423type=OpDesc
424eventq_index=0
425opClass=SimdShift
426opLat=1
427pipelined=true
428
429[system.cpu.fuPool.FUList5.opList09]
430type=OpDesc
431eventq_index=0
432opClass=SimdShiftAcc
433opLat=1
434pipelined=true
435
436[system.cpu.fuPool.FUList5.opList10]
437type=OpDesc
438eventq_index=0
439opClass=SimdSqrt
440opLat=1
441pipelined=true
442
443[system.cpu.fuPool.FUList5.opList11]
444type=OpDesc
445eventq_index=0
446opClass=SimdFloatAdd
447opLat=1
448pipelined=true
449
450[system.cpu.fuPool.FUList5.opList12]
451type=OpDesc
452eventq_index=0
453opClass=SimdFloatAlu
454opLat=1
455pipelined=true
456
457[system.cpu.fuPool.FUList5.opList13]
458type=OpDesc
459eventq_index=0
460opClass=SimdFloatCmp
461opLat=1
462pipelined=true
463
464[system.cpu.fuPool.FUList5.opList14]
465type=OpDesc
466eventq_index=0
467opClass=SimdFloatCvt
468opLat=1
469pipelined=true
470
471[system.cpu.fuPool.FUList5.opList15]
472type=OpDesc
473eventq_index=0
474opClass=SimdFloatDiv
475opLat=1
476pipelined=true
477
478[system.cpu.fuPool.FUList5.opList16]
479type=OpDesc
480eventq_index=0
481opClass=SimdFloatMisc
482opLat=1
483pipelined=true
484
485[system.cpu.fuPool.FUList5.opList17]
486type=OpDesc
487eventq_index=0
488opClass=SimdFloatMult
489opLat=1
490pipelined=true
491
492[system.cpu.fuPool.FUList5.opList18]
493type=OpDesc
494eventq_index=0
495opClass=SimdFloatMultAcc
496opLat=1
497pipelined=true
498
499[system.cpu.fuPool.FUList5.opList19]
500type=OpDesc
501eventq_index=0
502opClass=SimdFloatSqrt
503opLat=1
504pipelined=true
505
506[system.cpu.fuPool.FUList6]
507type=FUDesc
508children=opList0 opList1
509count=0
510eventq_index=0
511opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
512
513[system.cpu.fuPool.FUList6.opList0]
514type=OpDesc
515eventq_index=0
516opClass=MemWrite
517opLat=1
518pipelined=true
519
520[system.cpu.fuPool.FUList6.opList1]
521type=OpDesc
522eventq_index=0
523opClass=FloatMemWrite
524opLat=1
525pipelined=true
526
527[system.cpu.fuPool.FUList7]
528type=FUDesc
529children=opList0 opList1 opList2 opList3
530count=4
531eventq_index=0
532opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
533
534[system.cpu.fuPool.FUList7.opList0]
535type=OpDesc
536eventq_index=0
537opClass=MemRead
538opLat=1
539pipelined=true
540
541[system.cpu.fuPool.FUList7.opList1]
542type=OpDesc
543eventq_index=0
544opClass=MemWrite
545opLat=1
546pipelined=true
547
548[system.cpu.fuPool.FUList7.opList2]
549type=OpDesc
550eventq_index=0
551opClass=FloatMemRead
552opLat=1
553pipelined=true
554
555[system.cpu.fuPool.FUList7.opList3]
556type=OpDesc
557eventq_index=0
558opClass=FloatMemWrite
559opLat=1
560pipelined=true
561
562[system.cpu.fuPool.FUList8]
563type=FUDesc
564children=opList
565count=1
566eventq_index=0
567opList=system.cpu.fuPool.FUList8.opList
568
569[system.cpu.fuPool.FUList8.opList]
570type=OpDesc
571eventq_index=0
572opClass=IprAccess
573opLat=3
574pipelined=false
575
576[system.cpu.icache]
577type=Cache
578children=tags
579addr_ranges=0:18446744073709551615:0:0:0:0
580assoc=2
581clk_domain=system.cpu_clk_domain
582clusivity=mostly_incl
583data_latency=2
584default_p_state=UNDEFINED
585demand_mshr_reserve=1
586eventq_index=0
587is_read_only=true
588max_miss_count=0
589mshrs=4
590p_state_clk_gate_bins=20
591p_state_clk_gate_max=1000000000000
592p_state_clk_gate_min=1000
593power_model=Null
594prefetch_on_access=false
595prefetcher=Null
596response_latency=2
597sequential_access=false
598size=131072
599system=system
600tag_latency=2
601tags=system.cpu.icache.tags
602tgts_per_mshr=20
603write_buffers=8
604writeback_clean=true
605cpu_side=system.cpu.icache_port
606mem_side=system.cpu.toL2Bus.slave[0]
607
608[system.cpu.icache.tags]
609type=LRU
610assoc=2
611block_size=64
612clk_domain=system.cpu_clk_domain
613data_latency=2
614default_p_state=UNDEFINED
615eventq_index=0
616p_state_clk_gate_bins=20
617p_state_clk_gate_max=1000000000000
618p_state_clk_gate_min=1000
619power_model=Null
620sequential_access=false
621size=131072
622tag_latency=2
623
624[system.cpu.interrupts0]
625type=AlphaInterrupts
626eventq_index=0
627
628[system.cpu.interrupts1]
629type=AlphaInterrupts
630eventq_index=0
631
632[system.cpu.isa0]
633type=AlphaISA
634eventq_index=0
635system=system
636
637[system.cpu.isa1]
638type=AlphaISA
639eventq_index=0
640system=system
641
642[system.cpu.itb]
643type=AlphaTLB
644eventq_index=0
645size=48
646
647[system.cpu.l2cache]
648type=Cache
649children=tags
650addr_ranges=0:18446744073709551615:0:0:0:0
651assoc=8
652clk_domain=system.cpu_clk_domain
653clusivity=mostly_incl
654data_latency=20
655default_p_state=UNDEFINED
656demand_mshr_reserve=1
657eventq_index=0
658is_read_only=false
659max_miss_count=0
660mshrs=20
661p_state_clk_gate_bins=20
662p_state_clk_gate_max=1000000000000
663p_state_clk_gate_min=1000
664power_model=Null
665prefetch_on_access=false
666prefetcher=Null
667response_latency=20
668sequential_access=false
669size=2097152
670system=system
671tag_latency=20
672tags=system.cpu.l2cache.tags
673tgts_per_mshr=12
674write_buffers=8
675writeback_clean=false
676cpu_side=system.cpu.toL2Bus.master[0]
677mem_side=system.membus.slave[1]
678
679[system.cpu.l2cache.tags]
680type=LRU
681assoc=8
682block_size=64
683clk_domain=system.cpu_clk_domain
684data_latency=20
685default_p_state=UNDEFINED
686eventq_index=0
687p_state_clk_gate_bins=20
688p_state_clk_gate_max=1000000000000
689p_state_clk_gate_min=1000
690power_model=Null
691sequential_access=false
692size=2097152
693tag_latency=20
694
695[system.cpu.toL2Bus]
696type=CoherentXBar
697children=snoop_filter
698clk_domain=system.cpu_clk_domain
699default_p_state=UNDEFINED
700eventq_index=0
701forward_latency=0
702frontend_latency=1
703p_state_clk_gate_bins=20
704p_state_clk_gate_max=1000000000000
705p_state_clk_gate_min=1000
706point_of_coherency=false
707power_model=Null
708response_latency=1
709snoop_filter=system.cpu.toL2Bus.snoop_filter
710snoop_response_latency=1
711system=system
712use_default_range=false
713width=32
714master=system.cpu.l2cache.cpu_side
715slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
716
717[system.cpu.toL2Bus.snoop_filter]
718type=SnoopFilter
719eventq_index=0
720lookup_latency=0
721max_capacity=8388608
722system=system
723
724[system.cpu.tracer]
725type=ExeTracer
726eventq_index=0
727
728[system.cpu.workload0]
729type=Process
730cmd=hello
731cwd=
732drivers=
733egid=100
734env=
735errout=cerr
736euid=100
737eventq_index=0
738executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
739gid=100
740input=cin
741kvmInSE=false
742maxStackSize=67108864
743output=cout
744pgid=100
745pid=100
746ppid=0
747simpoint=0
748system=system
749uid=100
750useArchPT=false
751
752[system.cpu.workload1]
753type=Process
754cmd=hello
755cwd=
756drivers=
757egid=100
758env=
759errout=cerr
760euid=100
761eventq_index=0
762executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
763gid=100
764input=cin
765kvmInSE=false
766maxStackSize=67108864
767output=cout
768pgid=100
769pid=101
770ppid=100
771simpoint=0
772system=system
773uid=100
774useArchPT=false
775
776[system.cpu_clk_domain]
777type=SrcClockDomain
778clock=500
779domain_id=-1
780eventq_index=0
781init_perf_level=0
782voltage_domain=system.voltage_domain
783
784[system.dvfs_handler]
785type=DVFSHandler
786domains=
787enable=false
788eventq_index=0
789sys_clk_domain=system.clk_domain
790transition_latency=100000000
791
792[system.membus]
793type=CoherentXBar
794children=snoop_filter
795clk_domain=system.clk_domain
796default_p_state=UNDEFINED
797eventq_index=0
798forward_latency=4
799frontend_latency=3
800p_state_clk_gate_bins=20
801p_state_clk_gate_max=1000000000000
802p_state_clk_gate_min=1000
803point_of_coherency=true
804power_model=Null
805response_latency=2
806snoop_filter=system.membus.snoop_filter
807snoop_response_latency=4
808system=system
809use_default_range=false
810width=16
811master=system.physmem.port
812slave=system.system_port system.cpu.l2cache.mem_side
813
814[system.membus.snoop_filter]
815type=SnoopFilter
816eventq_index=0
817lookup_latency=1
818max_capacity=8388608
819system=system
820
821[system.physmem]
822type=DRAMCtrl
823IDD0=0.055000
824IDD02=0.000000
825IDD2N=0.032000
826IDD2N2=0.000000
827IDD2P0=0.000000
828IDD2P02=0.000000
829IDD2P1=0.032000
830IDD2P12=0.000000
831IDD3N=0.038000
832IDD3N2=0.000000
833IDD3P0=0.000000
834IDD3P02=0.000000
835IDD3P1=0.038000
836IDD3P12=0.000000
837IDD4R=0.157000
838IDD4R2=0.000000
839IDD4W=0.125000
840IDD4W2=0.000000
841IDD5=0.235000
842IDD52=0.000000
843IDD6=0.020000
844IDD62=0.000000
845VDD=1.500000
846VDD2=0.000000
847activation_limit=4
848addr_mapping=RoRaBaCoCh
849bank_groups_per_rank=0
850banks_per_rank=8
851burst_length=8
852channels=1
853clk_domain=system.clk_domain
854conf_table_reported=true
855default_p_state=UNDEFINED
856device_bus_width=8
857device_rowbuffer_size=1024
858device_size=536870912
859devices_per_rank=8
860dll=true
861eventq_index=0
862in_addr_map=true
863kvm_map=true
864max_accesses_per_row=16
865mem_sched_policy=frfcfs
866min_writes_per_switch=16
867null=false
868p_state_clk_gate_bins=20
869p_state_clk_gate_max=1000000000000
870p_state_clk_gate_min=1000
871page_policy=open_adaptive
872power_model=Null
873range=0:134217727:0:0:0:0
874ranks_per_channel=2
875read_buffer_size=32
876static_backend_latency=10000
877static_frontend_latency=10000
878tBURST=5000
879tCCD_L=0
880tCK=1250
881tCL=13750
882tCS=2500
883tRAS=35000
884tRCD=13750
885tREFI=7800000
886tRFC=260000
887tRP=13750
888tRRD=6000
889tRRD_L=0
890tRTP=7500
891tRTW=2500
892tWR=15000
893tWTR=7500
894tXAW=30000
895tXP=6000
896tXPDLL=0
897tXS=270000
898tXSDLL=0
899write_buffer_size=64
900write_high_thresh_perc=85
901write_low_thresh_perc=50
902port=system.membus.master[0]
903
904[system.voltage_domain]
905type=VoltageDomain
906eventq_index=0
907voltage=1.000000
908
909