config.ini revision 9924
14309Sgblack@eecs.umich.edu[root] 24309Sgblack@eecs.umich.edutype=Root 34309Sgblack@eecs.umich.educhildren=system 44309Sgblack@eecs.umich.edufull_system=false 54309Sgblack@eecs.umich.edutime_sync_enable=false 64309Sgblack@eecs.umich.edutime_sync_period=100000000000 74309Sgblack@eecs.umich.edutime_sync_spin_threshold=100000000 84309Sgblack@eecs.umich.edu 94309Sgblack@eecs.umich.edu[system] 104309Sgblack@eecs.umich.edutype=System 114309Sgblack@eecs.umich.educhildren=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 124309Sgblack@eecs.umich.eduboot_osflags=a 134309Sgblack@eecs.umich.educache_line_size=64 144309Sgblack@eecs.umich.educlk_domain=system.clk_domain 154309Sgblack@eecs.umich.eduinit_param=0 164309Sgblack@eecs.umich.edukernel= 174309Sgblack@eecs.umich.eduload_addr_mask=1099511627775 184309Sgblack@eecs.umich.edumem_mode=timing 194309Sgblack@eecs.umich.edumem_ranges= 204309Sgblack@eecs.umich.edumemories=system.physmem 214309Sgblack@eecs.umich.edunum_work_ids=16 224309Sgblack@eecs.umich.edureadfile= 234309Sgblack@eecs.umich.edusymbolfile= 244309Sgblack@eecs.umich.eduwork_begin_ckpt_count=0 254309Sgblack@eecs.umich.eduwork_begin_cpu_id_exit=-1 264309Sgblack@eecs.umich.eduwork_begin_exit_count=0 274309Sgblack@eecs.umich.eduwork_cpus_ckpt_count=0 284309Sgblack@eecs.umich.eduwork_end_ckpt_count=0 294309Sgblack@eecs.umich.eduwork_end_exit_count=0 304309Sgblack@eecs.umich.eduwork_item_id=-1 314309Sgblack@eecs.umich.edusystem_port=system.membus.slave[0] 324309Sgblack@eecs.umich.edu 334309Sgblack@eecs.umich.edu[system.clk_domain] 344309Sgblack@eecs.umich.edutype=SrcClockDomain 354309Sgblack@eecs.umich.educlock=1000 364309Sgblack@eecs.umich.eduvoltage_domain=system.voltage_domain 374309Sgblack@eecs.umich.edu 384309Sgblack@eecs.umich.edu[system.cpu] 394309Sgblack@eecs.umich.edutype=DerivO3CPU 404309Sgblack@eecs.umich.educhildren=branchPred dcache dtb fuPool icache interrupts isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1 414309Sgblack@eecs.umich.eduLFSTSize=1024 424309Sgblack@eecs.umich.eduLQEntries=32 434309Sgblack@eecs.umich.eduLSQCheckLoads=true 444309Sgblack@eecs.umich.eduLSQDepCheckShift=4 454309Sgblack@eecs.umich.eduSQEntries=32 464309Sgblack@eecs.umich.eduSSITSize=1024 474309Sgblack@eecs.umich.eduactivity=0 484309Sgblack@eecs.umich.edubackComSize=5 494309Sgblack@eecs.umich.edubranchPred=system.cpu.branchPred 504309Sgblack@eecs.umich.educachePorts=200 514309Sgblack@eecs.umich.educhecker=Null 524309Sgblack@eecs.umich.educlk_domain=system.cpu_clk_domain 534309Sgblack@eecs.umich.educommitToDecodeDelay=1 544309Sgblack@eecs.umich.educommitToFetchDelay=1 554309Sgblack@eecs.umich.educommitToIEWDelay=1 564309Sgblack@eecs.umich.educommitToRenameDelay=1 574309Sgblack@eecs.umich.educommitWidth=8 584533Sgblack@eecs.umich.educpu_id=0 594679Sgblack@eecs.umich.edudecodeToFetchDelay=1 604679Sgblack@eecs.umich.edudecodeToRenameDelay=1 614679Sgblack@eecs.umich.edudecodeWidth=8 624533Sgblack@eecs.umich.edudispatchWidth=8 634533Sgblack@eecs.umich.edudo_checkpoint_insts=true 644537Sgblack@eecs.umich.edudo_quiesce=true 654533Sgblack@eecs.umich.edudo_statistics_insts=true 664528Sgblack@eecs.umich.edudtb=system.cpu.dtb 674528Sgblack@eecs.umich.edufetchToDecodeDelay=1 684528Sgblack@eecs.umich.edufetchTrapLatency=1 694528Sgblack@eecs.umich.edufetchWidth=8 704528Sgblack@eecs.umich.eduforwardComSize=5 714605Sgblack@eecs.umich.edufuPool=system.cpu.fuPool 724528Sgblack@eecs.umich.edufunction_trace=false 734528Sgblack@eecs.umich.edufunction_trace_start=0 744528Sgblack@eecs.umich.eduiewToCommitDelay=1 754615Sgblack@eecs.umich.eduiewToDecodeDelay=1 764615Sgblack@eecs.umich.eduiewToFetchDelay=1 774615Sgblack@eecs.umich.eduiewToRenameDelay=1 785045Sgblack@eecs.umich.eduinterrupts=system.cpu.interrupts 795045Sgblack@eecs.umich.eduisa=system.cpu.isa0 system.cpu.isa1 804615Sgblack@eecs.umich.eduissueToExecuteDelay=1 814615Sgblack@eecs.umich.eduissueWidth=8 824615Sgblack@eecs.umich.eduitb=system.cpu.itb 835291Sgblack@eecs.umich.edumax_insts_all_threads=0 845291Sgblack@eecs.umich.edumax_insts_any_thread=0 855291Sgblack@eecs.umich.edumax_loads_all_threads=0 865291Sgblack@eecs.umich.edumax_loads_any_thread=0 874615Sgblack@eecs.umich.eduneedsTSO=false 884615Sgblack@eecs.umich.edunumIQEntries=64 894615Sgblack@eecs.umich.edunumPhysCCRegs=0 905029Sgblack@eecs.umich.edunumPhysFloatRegs=256 915029Sgblack@eecs.umich.edunumPhysIntRegs=256 924615Sgblack@eecs.umich.edunumROBEntries=192 935029Sgblack@eecs.umich.edunumRobs=1 945029Sgblack@eecs.umich.edunumThreads=2 955161Sgblack@eecs.umich.eduprofile=0 965161Sgblack@eecs.umich.eduprogress_interval=0 974863Sgblack@eecs.umich.edurenameToDecodeDelay=1 984615Sgblack@eecs.umich.edurenameToFetchDelay=1 994615Sgblack@eecs.umich.edurenameToIEWDelay=2 1004615Sgblack@eecs.umich.edurenameToROBDelay=1 1014615Sgblack@eecs.umich.edurenameWidth=8 1024953Sgblack@eecs.umich.edusimpoint_start_insts= 1034615Sgblack@eecs.umich.edusmtCommitPolicy=RoundRobin 1044615Sgblack@eecs.umich.edusmtFetchPolicy=SingleThread 1054863Sgblack@eecs.umich.edusmtIQPolicy=Partitioned 1064863Sgblack@eecs.umich.edusmtIQThreshold=100 1074863Sgblack@eecs.umich.edusmtLSQPolicy=Partitioned 1084863Sgblack@eecs.umich.edusmtLSQThreshold=100 1094863Sgblack@eecs.umich.edusmtNumFetchingThreads=1 1104863Sgblack@eecs.umich.edusmtROBPolicy=Partitioned 1114863Sgblack@eecs.umich.edusmtROBThreshold=100 1124620Sgblack@eecs.umich.edusquashWidth=8 1135149Sgblack@eecs.umich.edustore_set_clear_period=250000 1145149Sgblack@eecs.umich.eduswitched_out=false 1155232Sgblack@eecs.umich.edusystem=system 1165149Sgblack@eecs.umich.edutracer=system.cpu.tracer 1174620Sgblack@eecs.umich.edutrapLatency=13 1184620Sgblack@eecs.umich.eduwbDepth=1 1194615Sgblack@eecs.umich.eduwbWidth=8 1205241Sgblack@eecs.umich.eduworkload=system.cpu.workload0 system.cpu.workload1 1215241Sgblack@eecs.umich.edudcache_port=system.cpu.dcache.cpu_side 1225241Sgblack@eecs.umich.eduicache_port=system.cpu.icache.cpu_side 1234686Sgblack@eecs.umich.edu 1244686Sgblack@eecs.umich.edu[system.cpu.branchPred] 1254686Sgblack@eecs.umich.edutype=BranchPredictor 1264686Sgblack@eecs.umich.eduBTBEntries=4096 1274953Sgblack@eecs.umich.eduBTBTagSize=16 1284686Sgblack@eecs.umich.eduRASSize=16 1294686Sgblack@eecs.umich.educhoiceCtrBits=2 1304686Sgblack@eecs.umich.educhoicePredictorSize=8192 1314686Sgblack@eecs.umich.eduglobalCtrBits=2 1324953Sgblack@eecs.umich.eduglobalPredictorSize=8192 1334953Sgblack@eecs.umich.eduinstShiftAmt=2 1344686Sgblack@eecs.umich.edulocalCtrBits=2 1354686Sgblack@eecs.umich.edulocalHistoryTableSize=2048 1364686Sgblack@eecs.umich.edulocalPredictorSize=2048 1374686Sgblack@eecs.umich.edunumThreads=2 1384615Sgblack@eecs.umich.edupredType=tournament 1394615Sgblack@eecs.umich.edu 1404615Sgblack@eecs.umich.edu[system.cpu.dcache] 1414615Sgblack@eecs.umich.edutype=BaseCache 1424615Sgblack@eecs.umich.educhildren=tags 1434615Sgblack@eecs.umich.eduaddr_ranges=0:18446744073709551615 1444615Sgblack@eecs.umich.eduassoc=2 1455291Sgblack@eecs.umich.educlk_domain=system.cpu_clk_domain 1465291Sgblack@eecs.umich.eduforward_snoops=true 1475291Sgblack@eecs.umich.eduhit_latency=2 1485291Sgblack@eecs.umich.eduis_top_level=true 1495291Sgblack@eecs.umich.edumax_miss_count=0 1505291Sgblack@eecs.umich.edumshrs=4 1515291Sgblack@eecs.umich.eduprefetch_on_access=false 1525161Sgblack@eecs.umich.eduprefetcher=Null 1535161Sgblack@eecs.umich.eduresponse_latency=2 1545161Sgblack@eecs.umich.edusize=262144 1555161Sgblack@eecs.umich.edusystem=system 1565161Sgblack@eecs.umich.edutags=system.cpu.dcache.tags 1575008Sgblack@eecs.umich.edutgts_per_mshr=20 1585008Sgblack@eecs.umich.edutwo_queue=false 1595008Sgblack@eecs.umich.eduwrite_buffers=8 1605008Sgblack@eecs.umich.educpu_side=system.cpu.dcache_port 1615008Sgblack@eecs.umich.edumem_side=system.cpu.toL2Bus.slave[1] 1625082Sgblack@eecs.umich.edu 1635121Sgblack@eecs.umich.edu[system.cpu.dcache.tags] 1645082Sgblack@eecs.umich.edutype=LRU 1655082Sgblack@eecs.umich.eduassoc=2 1665082Sgblack@eecs.umich.edublock_size=64 1674528Sgblack@eecs.umich.educlk_domain=system.cpu_clk_domain 1684528Sgblack@eecs.umich.eduhit_latency=2 169size=262144 170 171[system.cpu.dtb] 172type=AlphaTLB 173size=64 174 175[system.cpu.fuPool] 176type=FUPool 177children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 178FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 179 180[system.cpu.fuPool.FUList0] 181type=FUDesc 182children=opList 183count=6 184opList=system.cpu.fuPool.FUList0.opList 185 186[system.cpu.fuPool.FUList0.opList] 187type=OpDesc 188issueLat=1 189opClass=IntAlu 190opLat=1 191 192[system.cpu.fuPool.FUList1] 193type=FUDesc 194children=opList0 opList1 195count=2 196opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 197 198[system.cpu.fuPool.FUList1.opList0] 199type=OpDesc 200issueLat=1 201opClass=IntMult 202opLat=3 203 204[system.cpu.fuPool.FUList1.opList1] 205type=OpDesc 206issueLat=19 207opClass=IntDiv 208opLat=20 209 210[system.cpu.fuPool.FUList2] 211type=FUDesc 212children=opList0 opList1 opList2 213count=4 214opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 215 216[system.cpu.fuPool.FUList2.opList0] 217type=OpDesc 218issueLat=1 219opClass=FloatAdd 220opLat=2 221 222[system.cpu.fuPool.FUList2.opList1] 223type=OpDesc 224issueLat=1 225opClass=FloatCmp 226opLat=2 227 228[system.cpu.fuPool.FUList2.opList2] 229type=OpDesc 230issueLat=1 231opClass=FloatCvt 232opLat=2 233 234[system.cpu.fuPool.FUList3] 235type=FUDesc 236children=opList0 opList1 opList2 237count=2 238opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 239 240[system.cpu.fuPool.FUList3.opList0] 241type=OpDesc 242issueLat=1 243opClass=FloatMult 244opLat=4 245 246[system.cpu.fuPool.FUList3.opList1] 247type=OpDesc 248issueLat=12 249opClass=FloatDiv 250opLat=12 251 252[system.cpu.fuPool.FUList3.opList2] 253type=OpDesc 254issueLat=24 255opClass=FloatSqrt 256opLat=24 257 258[system.cpu.fuPool.FUList4] 259type=FUDesc 260children=opList 261count=0 262opList=system.cpu.fuPool.FUList4.opList 263 264[system.cpu.fuPool.FUList4.opList] 265type=OpDesc 266issueLat=1 267opClass=MemRead 268opLat=1 269 270[system.cpu.fuPool.FUList5] 271type=FUDesc 272children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 273count=4 274opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 275 276[system.cpu.fuPool.FUList5.opList00] 277type=OpDesc 278issueLat=1 279opClass=SimdAdd 280opLat=1 281 282[system.cpu.fuPool.FUList5.opList01] 283type=OpDesc 284issueLat=1 285opClass=SimdAddAcc 286opLat=1 287 288[system.cpu.fuPool.FUList5.opList02] 289type=OpDesc 290issueLat=1 291opClass=SimdAlu 292opLat=1 293 294[system.cpu.fuPool.FUList5.opList03] 295type=OpDesc 296issueLat=1 297opClass=SimdCmp 298opLat=1 299 300[system.cpu.fuPool.FUList5.opList04] 301type=OpDesc 302issueLat=1 303opClass=SimdCvt 304opLat=1 305 306[system.cpu.fuPool.FUList5.opList05] 307type=OpDesc 308issueLat=1 309opClass=SimdMisc 310opLat=1 311 312[system.cpu.fuPool.FUList5.opList06] 313type=OpDesc 314issueLat=1 315opClass=SimdMult 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList07] 319type=OpDesc 320issueLat=1 321opClass=SimdMultAcc 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList08] 325type=OpDesc 326issueLat=1 327opClass=SimdShift 328opLat=1 329 330[system.cpu.fuPool.FUList5.opList09] 331type=OpDesc 332issueLat=1 333opClass=SimdShiftAcc 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList10] 337type=OpDesc 338issueLat=1 339opClass=SimdSqrt 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList11] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatAdd 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList12] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatAlu 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList13] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatCmp 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList14] 361type=OpDesc 362issueLat=1 363opClass=SimdFloatCvt 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList15] 367type=OpDesc 368issueLat=1 369opClass=SimdFloatDiv 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList16] 373type=OpDesc 374issueLat=1 375opClass=SimdFloatMisc 376opLat=1 377 378[system.cpu.fuPool.FUList5.opList17] 379type=OpDesc 380issueLat=1 381opClass=SimdFloatMult 382opLat=1 383 384[system.cpu.fuPool.FUList5.opList18] 385type=OpDesc 386issueLat=1 387opClass=SimdFloatMultAcc 388opLat=1 389 390[system.cpu.fuPool.FUList5.opList19] 391type=OpDesc 392issueLat=1 393opClass=SimdFloatSqrt 394opLat=1 395 396[system.cpu.fuPool.FUList6] 397type=FUDesc 398children=opList 399count=0 400opList=system.cpu.fuPool.FUList6.opList 401 402[system.cpu.fuPool.FUList6.opList] 403type=OpDesc 404issueLat=1 405opClass=MemWrite 406opLat=1 407 408[system.cpu.fuPool.FUList7] 409type=FUDesc 410children=opList0 opList1 411count=4 412opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 413 414[system.cpu.fuPool.FUList7.opList0] 415type=OpDesc 416issueLat=1 417opClass=MemRead 418opLat=1 419 420[system.cpu.fuPool.FUList7.opList1] 421type=OpDesc 422issueLat=1 423opClass=MemWrite 424opLat=1 425 426[system.cpu.fuPool.FUList8] 427type=FUDesc 428children=opList 429count=1 430opList=system.cpu.fuPool.FUList8.opList 431 432[system.cpu.fuPool.FUList8.opList] 433type=OpDesc 434issueLat=3 435opClass=IprAccess 436opLat=3 437 438[system.cpu.icache] 439type=BaseCache 440children=tags 441addr_ranges=0:18446744073709551615 442assoc=2 443clk_domain=system.cpu_clk_domain 444forward_snoops=true 445hit_latency=2 446is_top_level=true 447max_miss_count=0 448mshrs=4 449prefetch_on_access=false 450prefetcher=Null 451response_latency=2 452size=131072 453system=system 454tags=system.cpu.icache.tags 455tgts_per_mshr=20 456two_queue=false 457write_buffers=8 458cpu_side=system.cpu.icache_port 459mem_side=system.cpu.toL2Bus.slave[0] 460 461[system.cpu.icache.tags] 462type=LRU 463assoc=2 464block_size=64 465clk_domain=system.cpu_clk_domain 466hit_latency=2 467size=131072 468 469[system.cpu.interrupts] 470type=AlphaInterrupts 471 472[system.cpu.isa0] 473type=AlphaISA 474 475[system.cpu.isa1] 476type=AlphaISA 477 478[system.cpu.itb] 479type=AlphaTLB 480size=48 481 482[system.cpu.l2cache] 483type=BaseCache 484children=tags 485addr_ranges=0:18446744073709551615 486assoc=8 487clk_domain=system.cpu_clk_domain 488forward_snoops=true 489hit_latency=20 490is_top_level=false 491max_miss_count=0 492mshrs=20 493prefetch_on_access=false 494prefetcher=Null 495response_latency=20 496size=2097152 497system=system 498tags=system.cpu.l2cache.tags 499tgts_per_mshr=12 500two_queue=false 501write_buffers=8 502cpu_side=system.cpu.toL2Bus.master[0] 503mem_side=system.membus.slave[1] 504 505[system.cpu.l2cache.tags] 506type=LRU 507assoc=8 508block_size=64 509clk_domain=system.cpu_clk_domain 510hit_latency=20 511size=2097152 512 513[system.cpu.toL2Bus] 514type=CoherentBus 515clk_domain=system.cpu_clk_domain 516header_cycles=1 517system=system 518use_default_range=false 519width=32 520master=system.cpu.l2cache.cpu_side 521slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 522 523[system.cpu.tracer] 524type=ExeTracer 525 526[system.cpu.workload0] 527type=LiveProcess 528cmd=hello 529cwd= 530egid=100 531env= 532errout=cerr 533euid=100 534executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello 535gid=100 536input=cin 537max_stack_size=67108864 538output=cout 539pid=100 540ppid=99 541simpoint=0 542system=system 543uid=100 544 545[system.cpu.workload1] 546type=LiveProcess 547cmd=hello 548cwd= 549egid=100 550env= 551errout=cerr 552euid=100 553executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello 554gid=100 555input=cin 556max_stack_size=67108864 557output=cout 558pid=100 559ppid=99 560simpoint=0 561system=system 562uid=100 563 564[system.cpu_clk_domain] 565type=SrcClockDomain 566clock=500 567voltage_domain=system.voltage_domain 568 569[system.membus] 570type=CoherentBus 571clk_domain=system.clk_domain 572header_cycles=1 573system=system 574use_default_range=false 575width=8 576master=system.physmem.port 577slave=system.system_port system.cpu.l2cache.mem_side 578 579[system.physmem] 580type=SimpleDRAM 581activation_limit=4 582addr_mapping=RaBaChCo 583banks_per_rank=8 584burst_length=8 585channels=1 586clk_domain=system.clk_domain 587conf_table_reported=true 588device_bus_width=8 589device_rowbuffer_size=1024 590devices_per_rank=8 591in_addr_map=true 592mem_sched_policy=frfcfs 593null=false 594page_policy=open 595range=0:134217727 596ranks_per_channel=2 597read_buffer_size=32 598static_backend_latency=10000 599static_frontend_latency=10000 600tBURST=5000 601tCL=13750 602tRCD=13750 603tREFI=7800000 604tRFC=300000 605tRP=13750 606tWTR=7500 607tXAW=40000 608write_buffer_size=32 609write_thresh_perc=70 610port=system.membus.master[0] 611 612[system.voltage_domain] 613type=VoltageDomain 614voltage=1.000000 615 616