config.ini revision 9885
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= 23symbolfile= 24work_begin_ckpt_count=0 25work_begin_cpu_id_exit=-1 26work_begin_exit_count=0 27work_cpus_ckpt_count=0 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 36voltage_domain=system.voltage_domain 37 38[system.cpu] 39type=DerivO3CPU 40children=branchPred dcache dtb fuPool icache interrupts isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1 41LFSTSize=1024 42LQEntries=32 43LSQCheckLoads=true 44LSQDepCheckShift=4 45SQEntries=32 46SSITSize=1024 47activity=0 48backComSize=5 49branchPred=system.cpu.branchPred 50cachePorts=200 51checker=Null 52clk_domain=system.cpu_clk_domain 53commitToDecodeDelay=1 54commitToFetchDelay=1 55commitToIEWDelay=1 56commitToRenameDelay=1 57commitWidth=8 58cpu_id=0 59decodeToFetchDelay=1 60decodeToRenameDelay=1 61decodeWidth=8 62dispatchWidth=8 63do_checkpoint_insts=true 64do_quiesce=true 65do_statistics_insts=true 66dtb=system.cpu.dtb 67fetchToDecodeDelay=1 68fetchTrapLatency=1 69fetchWidth=8 70forwardComSize=5 71fuPool=system.cpu.fuPool 72function_trace=false 73function_trace_start=0 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78interrupts=system.cpu.interrupts 79isa=system.cpu.isa0 system.cpu.isa1 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu.itb 83max_insts_all_threads=0 84max_insts_any_thread=0 85max_loads_all_threads=0 86max_loads_any_thread=0 87needsTSO=false 88numIQEntries=64 89numPhysFloatRegs=256 90numPhysIntRegs=256 91numROBEntries=192 92numRobs=1 93numThreads=2 94profile=0 95progress_interval=0 96renameToDecodeDelay=1 97renameToFetchDelay=1 98renameToIEWDelay=2 99renameToROBDelay=1 100renameWidth=8 101simpoint_start_insts= 102smtCommitPolicy=RoundRobin 103smtFetchPolicy=SingleThread 104smtIQPolicy=Partitioned 105smtIQThreshold=100 106smtLSQPolicy=Partitioned 107smtLSQThreshold=100 108smtNumFetchingThreads=1 109smtROBPolicy=Partitioned 110smtROBThreshold=100 111squashWidth=8 112store_set_clear_period=250000 113switched_out=false 114system=system 115tracer=system.cpu.tracer 116trapLatency=13 117wbDepth=1 118wbWidth=8 119workload=system.cpu.workload0 system.cpu.workload1 120dcache_port=system.cpu.dcache.cpu_side 121icache_port=system.cpu.icache.cpu_side 122 123[system.cpu.branchPred] 124type=BranchPredictor 125BTBEntries=4096 126BTBTagSize=16 127RASSize=16 128choiceCtrBits=2 129choicePredictorSize=8192 130globalCtrBits=2 131globalPredictorSize=8192 132instShiftAmt=2 133localCtrBits=2 134localHistoryTableSize=2048 135localPredictorSize=2048 136numThreads=2 137predType=tournament 138 139[system.cpu.dcache] 140type=BaseCache 141children=tags 142addr_ranges=0:18446744073709551615 143assoc=2 144clk_domain=system.cpu_clk_domain 145forward_snoops=true 146hit_latency=2 147is_top_level=true 148max_miss_count=0 149mshrs=4 150prefetch_on_access=false 151prefetcher=Null 152response_latency=2 153size=262144 154system=system 155tags=system.cpu.dcache.tags 156tgts_per_mshr=20 157two_queue=false 158write_buffers=8 159cpu_side=system.cpu.dcache_port 160mem_side=system.cpu.toL2Bus.slave[1] 161 162[system.cpu.dcache.tags] 163type=LRU 164assoc=2 165block_size=64 166clk_domain=system.cpu_clk_domain 167hit_latency=2 168size=262144 169 170[system.cpu.dtb] 171type=AlphaTLB 172size=64 173 174[system.cpu.fuPool] 175type=FUPool 176children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 177FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 178 179[system.cpu.fuPool.FUList0] 180type=FUDesc 181children=opList 182count=6 183opList=system.cpu.fuPool.FUList0.opList 184 185[system.cpu.fuPool.FUList0.opList] 186type=OpDesc 187issueLat=1 188opClass=IntAlu 189opLat=1 190 191[system.cpu.fuPool.FUList1] 192type=FUDesc 193children=opList0 opList1 194count=2 195opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 196 197[system.cpu.fuPool.FUList1.opList0] 198type=OpDesc 199issueLat=1 200opClass=IntMult 201opLat=3 202 203[system.cpu.fuPool.FUList1.opList1] 204type=OpDesc 205issueLat=19 206opClass=IntDiv 207opLat=20 208 209[system.cpu.fuPool.FUList2] 210type=FUDesc 211children=opList0 opList1 opList2 212count=4 213opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 214 215[system.cpu.fuPool.FUList2.opList0] 216type=OpDesc 217issueLat=1 218opClass=FloatAdd 219opLat=2 220 221[system.cpu.fuPool.FUList2.opList1] 222type=OpDesc 223issueLat=1 224opClass=FloatCmp 225opLat=2 226 227[system.cpu.fuPool.FUList2.opList2] 228type=OpDesc 229issueLat=1 230opClass=FloatCvt 231opLat=2 232 233[system.cpu.fuPool.FUList3] 234type=FUDesc 235children=opList0 opList1 opList2 236count=2 237opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 238 239[system.cpu.fuPool.FUList3.opList0] 240type=OpDesc 241issueLat=1 242opClass=FloatMult 243opLat=4 244 245[system.cpu.fuPool.FUList3.opList1] 246type=OpDesc 247issueLat=12 248opClass=FloatDiv 249opLat=12 250 251[system.cpu.fuPool.FUList3.opList2] 252type=OpDesc 253issueLat=24 254opClass=FloatSqrt 255opLat=24 256 257[system.cpu.fuPool.FUList4] 258type=FUDesc 259children=opList 260count=0 261opList=system.cpu.fuPool.FUList4.opList 262 263[system.cpu.fuPool.FUList4.opList] 264type=OpDesc 265issueLat=1 266opClass=MemRead 267opLat=1 268 269[system.cpu.fuPool.FUList5] 270type=FUDesc 271children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 272count=4 273opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 274 275[system.cpu.fuPool.FUList5.opList00] 276type=OpDesc 277issueLat=1 278opClass=SimdAdd 279opLat=1 280 281[system.cpu.fuPool.FUList5.opList01] 282type=OpDesc 283issueLat=1 284opClass=SimdAddAcc 285opLat=1 286 287[system.cpu.fuPool.FUList5.opList02] 288type=OpDesc 289issueLat=1 290opClass=SimdAlu 291opLat=1 292 293[system.cpu.fuPool.FUList5.opList03] 294type=OpDesc 295issueLat=1 296opClass=SimdCmp 297opLat=1 298 299[system.cpu.fuPool.FUList5.opList04] 300type=OpDesc 301issueLat=1 302opClass=SimdCvt 303opLat=1 304 305[system.cpu.fuPool.FUList5.opList05] 306type=OpDesc 307issueLat=1 308opClass=SimdMisc 309opLat=1 310 311[system.cpu.fuPool.FUList5.opList06] 312type=OpDesc 313issueLat=1 314opClass=SimdMult 315opLat=1 316 317[system.cpu.fuPool.FUList5.opList07] 318type=OpDesc 319issueLat=1 320opClass=SimdMultAcc 321opLat=1 322 323[system.cpu.fuPool.FUList5.opList08] 324type=OpDesc 325issueLat=1 326opClass=SimdShift 327opLat=1 328 329[system.cpu.fuPool.FUList5.opList09] 330type=OpDesc 331issueLat=1 332opClass=SimdShiftAcc 333opLat=1 334 335[system.cpu.fuPool.FUList5.opList10] 336type=OpDesc 337issueLat=1 338opClass=SimdSqrt 339opLat=1 340 341[system.cpu.fuPool.FUList5.opList11] 342type=OpDesc 343issueLat=1 344opClass=SimdFloatAdd 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList12] 348type=OpDesc 349issueLat=1 350opClass=SimdFloatAlu 351opLat=1 352 353[system.cpu.fuPool.FUList5.opList13] 354type=OpDesc 355issueLat=1 356opClass=SimdFloatCmp 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList14] 360type=OpDesc 361issueLat=1 362opClass=SimdFloatCvt 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList15] 366type=OpDesc 367issueLat=1 368opClass=SimdFloatDiv 369opLat=1 370 371[system.cpu.fuPool.FUList5.opList16] 372type=OpDesc 373issueLat=1 374opClass=SimdFloatMisc 375opLat=1 376 377[system.cpu.fuPool.FUList5.opList17] 378type=OpDesc 379issueLat=1 380opClass=SimdFloatMult 381opLat=1 382 383[system.cpu.fuPool.FUList5.opList18] 384type=OpDesc 385issueLat=1 386opClass=SimdFloatMultAcc 387opLat=1 388 389[system.cpu.fuPool.FUList5.opList19] 390type=OpDesc 391issueLat=1 392opClass=SimdFloatSqrt 393opLat=1 394 395[system.cpu.fuPool.FUList6] 396type=FUDesc 397children=opList 398count=0 399opList=system.cpu.fuPool.FUList6.opList 400 401[system.cpu.fuPool.FUList6.opList] 402type=OpDesc 403issueLat=1 404opClass=MemWrite 405opLat=1 406 407[system.cpu.fuPool.FUList7] 408type=FUDesc 409children=opList0 opList1 410count=4 411opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 412 413[system.cpu.fuPool.FUList7.opList0] 414type=OpDesc 415issueLat=1 416opClass=MemRead 417opLat=1 418 419[system.cpu.fuPool.FUList7.opList1] 420type=OpDesc 421issueLat=1 422opClass=MemWrite 423opLat=1 424 425[system.cpu.fuPool.FUList8] 426type=FUDesc 427children=opList 428count=1 429opList=system.cpu.fuPool.FUList8.opList 430 431[system.cpu.fuPool.FUList8.opList] 432type=OpDesc 433issueLat=3 434opClass=IprAccess 435opLat=3 436 437[system.cpu.icache] 438type=BaseCache 439children=tags 440addr_ranges=0:18446744073709551615 441assoc=2 442clk_domain=system.cpu_clk_domain 443forward_snoops=true 444hit_latency=2 445is_top_level=true 446max_miss_count=0 447mshrs=4 448prefetch_on_access=false 449prefetcher=Null 450response_latency=2 451size=131072 452system=system 453tags=system.cpu.icache.tags 454tgts_per_mshr=20 455two_queue=false 456write_buffers=8 457cpu_side=system.cpu.icache_port 458mem_side=system.cpu.toL2Bus.slave[0] 459 460[system.cpu.icache.tags] 461type=LRU 462assoc=2 463block_size=64 464clk_domain=system.cpu_clk_domain 465hit_latency=2 466size=131072 467 468[system.cpu.interrupts] 469type=AlphaInterrupts 470 471[system.cpu.isa0] 472type=AlphaISA 473 474[system.cpu.isa1] 475type=AlphaISA 476 477[system.cpu.itb] 478type=AlphaTLB 479size=48 480 481[system.cpu.l2cache] 482type=BaseCache 483children=tags 484addr_ranges=0:18446744073709551615 485assoc=8 486clk_domain=system.cpu_clk_domain 487forward_snoops=true 488hit_latency=20 489is_top_level=false 490max_miss_count=0 491mshrs=20 492prefetch_on_access=false 493prefetcher=Null 494response_latency=20 495size=2097152 496system=system 497tags=system.cpu.l2cache.tags 498tgts_per_mshr=12 499two_queue=false 500write_buffers=8 501cpu_side=system.cpu.toL2Bus.master[0] 502mem_side=system.membus.slave[1] 503 504[system.cpu.l2cache.tags] 505type=LRU 506assoc=8 507block_size=64 508clk_domain=system.cpu_clk_domain 509hit_latency=20 510size=2097152 511 512[system.cpu.toL2Bus] 513type=CoherentBus 514clk_domain=system.cpu_clk_domain 515header_cycles=1 516system=system 517use_default_range=false 518width=32 519master=system.cpu.l2cache.cpu_side 520slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 521 522[system.cpu.tracer] 523type=ExeTracer 524 525[system.cpu.workload0] 526type=LiveProcess 527cmd=hello 528cwd= 529egid=100 530env= 531errout=cerr 532euid=100 533executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello 534gid=100 535input=cin 536max_stack_size=67108864 537output=cout 538pid=100 539ppid=99 540simpoint=0 541system=system 542uid=100 543 544[system.cpu.workload1] 545type=LiveProcess 546cmd=hello 547cwd= 548egid=100 549env= 550errout=cerr 551euid=100 552executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello 553gid=100 554input=cin 555max_stack_size=67108864 556output=cout 557pid=100 558ppid=99 559simpoint=0 560system=system 561uid=100 562 563[system.cpu_clk_domain] 564type=SrcClockDomain 565clock=500 566voltage_domain=system.voltage_domain 567 568[system.membus] 569type=CoherentBus 570clk_domain=system.clk_domain 571header_cycles=1 572system=system 573use_default_range=false 574width=8 575master=system.physmem.port 576slave=system.system_port system.cpu.l2cache.mem_side 577 578[system.physmem] 579type=SimpleDRAM 580activation_limit=4 581addr_mapping=RaBaChCo 582banks_per_rank=8 583burst_length=8 584channels=1 585clk_domain=system.clk_domain 586conf_table_reported=true 587device_bus_width=8 588device_rowbuffer_size=1024 589devices_per_rank=8 590in_addr_map=true 591mem_sched_policy=frfcfs 592null=false 593page_policy=open 594range=0:134217727 595ranks_per_channel=2 596read_buffer_size=32 597static_backend_latency=10000 598static_frontend_latency=10000 599tBURST=5000 600tCL=13750 601tRCD=13750 602tREFI=7800000 603tRFC=300000 604tRP=13750 605tWTR=7500 606tXAW=40000 607write_buffer_size=32 608write_thresh_perc=70 609port=system.membus.master[0] 610 611[system.voltage_domain] 612type=VoltageDomain 613voltage=1.000000 614 615