config.ini revision 8835
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 19physmem=system.physmem 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.port[0] 30 31[system.cpu] 32type=DerivO3CPU 33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload0 workload1 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts 81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 89max_insts_any_thread=0 90max_loads_all_threads=0 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=2 99phase=0 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000 119system=system 120tracer=system.cpu.tracer 121trapLatency=13 122wbDepth=1 123wbWidth=8 124workload=system.cpu.workload0 system.cpu.workload1 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache 130addr_range=0:18446744073709551615 131assoc=2 132block_size=64 133forward_snoops=true 134hash_delay=1 135is_top_level=true 136latency=1000 137max_miss_count=0 138mshrs=10 139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null 143size=262144 144subblock_size=0 145system=system 146tgts_per_mshr=20 147trace_addr=0 148two_queue=false 149write_buffers=8 150cpu_side=system.cpu.dcache_port 151mem_side=system.cpu.toL2Bus.port[1] 152 153[system.cpu.dtb] 154type=AlphaTLB 155size=64 156 157[system.cpu.fuPool] 158type=FUPool 159children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 160FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 161 162[system.cpu.fuPool.FUList0] 163type=FUDesc 164children=opList 165count=6 166opList=system.cpu.fuPool.FUList0.opList 167 168[system.cpu.fuPool.FUList0.opList] 169type=OpDesc 170issueLat=1 171opClass=IntAlu 172opLat=1 173 174[system.cpu.fuPool.FUList1] 175type=FUDesc 176children=opList0 opList1 177count=2 178opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 179 180[system.cpu.fuPool.FUList1.opList0] 181type=OpDesc 182issueLat=1 183opClass=IntMult 184opLat=3 185 186[system.cpu.fuPool.FUList1.opList1] 187type=OpDesc 188issueLat=19 189opClass=IntDiv 190opLat=20 191 192[system.cpu.fuPool.FUList2] 193type=FUDesc 194children=opList0 opList1 opList2 195count=4 196opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 197 198[system.cpu.fuPool.FUList2.opList0] 199type=OpDesc 200issueLat=1 201opClass=FloatAdd 202opLat=2 203 204[system.cpu.fuPool.FUList2.opList1] 205type=OpDesc 206issueLat=1 207opClass=FloatCmp 208opLat=2 209 210[system.cpu.fuPool.FUList2.opList2] 211type=OpDesc 212issueLat=1 213opClass=FloatCvt 214opLat=2 215 216[system.cpu.fuPool.FUList3] 217type=FUDesc 218children=opList0 opList1 opList2 219count=2 220opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 221 222[system.cpu.fuPool.FUList3.opList0] 223type=OpDesc 224issueLat=1 225opClass=FloatMult 226opLat=4 227 228[system.cpu.fuPool.FUList3.opList1] 229type=OpDesc 230issueLat=12 231opClass=FloatDiv 232opLat=12 233 234[system.cpu.fuPool.FUList3.opList2] 235type=OpDesc 236issueLat=24 237opClass=FloatSqrt 238opLat=24 239 240[system.cpu.fuPool.FUList4] 241type=FUDesc 242children=opList 243count=0 244opList=system.cpu.fuPool.FUList4.opList 245 246[system.cpu.fuPool.FUList4.opList] 247type=OpDesc 248issueLat=1 249opClass=MemRead 250opLat=1 251 252[system.cpu.fuPool.FUList5] 253type=FUDesc 254children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 255count=4 256opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 257 258[system.cpu.fuPool.FUList5.opList00] 259type=OpDesc 260issueLat=1 261opClass=SimdAdd 262opLat=1 263 264[system.cpu.fuPool.FUList5.opList01] 265type=OpDesc 266issueLat=1 267opClass=SimdAddAcc 268opLat=1 269 270[system.cpu.fuPool.FUList5.opList02] 271type=OpDesc 272issueLat=1 273opClass=SimdAlu 274opLat=1 275 276[system.cpu.fuPool.FUList5.opList03] 277type=OpDesc 278issueLat=1 279opClass=SimdCmp 280opLat=1 281 282[system.cpu.fuPool.FUList5.opList04] 283type=OpDesc 284issueLat=1 285opClass=SimdCvt 286opLat=1 287 288[system.cpu.fuPool.FUList5.opList05] 289type=OpDesc 290issueLat=1 291opClass=SimdMisc 292opLat=1 293 294[system.cpu.fuPool.FUList5.opList06] 295type=OpDesc 296issueLat=1 297opClass=SimdMult 298opLat=1 299 300[system.cpu.fuPool.FUList5.opList07] 301type=OpDesc 302issueLat=1 303opClass=SimdMultAcc 304opLat=1 305 306[system.cpu.fuPool.FUList5.opList08] 307type=OpDesc 308issueLat=1 309opClass=SimdShift 310opLat=1 311 312[system.cpu.fuPool.FUList5.opList09] 313type=OpDesc 314issueLat=1 315opClass=SimdShiftAcc 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList10] 319type=OpDesc 320issueLat=1 321opClass=SimdSqrt 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList11] 325type=OpDesc 326issueLat=1 327opClass=SimdFloatAdd 328opLat=1 329 330[system.cpu.fuPool.FUList5.opList12] 331type=OpDesc 332issueLat=1 333opClass=SimdFloatAlu 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList13] 337type=OpDesc 338issueLat=1 339opClass=SimdFloatCmp 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList14] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatCvt 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList15] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatDiv 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList16] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatMisc 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList17] 361type=OpDesc 362issueLat=1 363opClass=SimdFloatMult 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList18] 367type=OpDesc 368issueLat=1 369opClass=SimdFloatMultAcc 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList19] 373type=OpDesc 374issueLat=1 375opClass=SimdFloatSqrt 376opLat=1 377 378[system.cpu.fuPool.FUList6] 379type=FUDesc 380children=opList 381count=0 382opList=system.cpu.fuPool.FUList6.opList 383 384[system.cpu.fuPool.FUList6.opList] 385type=OpDesc 386issueLat=1 387opClass=MemWrite 388opLat=1 389 390[system.cpu.fuPool.FUList7] 391type=FUDesc 392children=opList0 opList1 393count=4 394opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 395 396[system.cpu.fuPool.FUList7.opList0] 397type=OpDesc 398issueLat=1 399opClass=MemRead 400opLat=1 401 402[system.cpu.fuPool.FUList7.opList1] 403type=OpDesc 404issueLat=1 405opClass=MemWrite 406opLat=1 407 408[system.cpu.fuPool.FUList8] 409type=FUDesc 410children=opList 411count=1 412opList=system.cpu.fuPool.FUList8.opList 413 414[system.cpu.fuPool.FUList8.opList] 415type=OpDesc 416issueLat=3 417opClass=IprAccess 418opLat=3 419 420[system.cpu.icache] 421type=BaseCache 422addr_range=0:18446744073709551615 423assoc=2 424block_size=64 425forward_snoops=true 426hash_delay=1 427is_top_level=true 428latency=1000 429max_miss_count=0 430mshrs=10 431prefetch_on_access=false 432prefetcher=Null 433prioritizeRequests=false 434repl=Null 435size=131072 436subblock_size=0 437system=system 438tgts_per_mshr=20 439trace_addr=0 440two_queue=false 441write_buffers=8 442cpu_side=system.cpu.icache_port 443mem_side=system.cpu.toL2Bus.port[0] 444 445[system.cpu.interrupts] 446type=AlphaInterrupts 447 448[system.cpu.itb] 449type=AlphaTLB 450size=48 451 452[system.cpu.l2cache] 453type=BaseCache 454addr_range=0:18446744073709551615 455assoc=2 456block_size=64 457forward_snoops=true 458hash_delay=1 459is_top_level=false 460latency=1000 461max_miss_count=0 462mshrs=10 463prefetch_on_access=false 464prefetcher=Null 465prioritizeRequests=false 466repl=Null 467size=2097152 468subblock_size=0 469system=system 470tgts_per_mshr=5 471trace_addr=0 472two_queue=false 473write_buffers=8 474cpu_side=system.cpu.toL2Bus.port[2] 475mem_side=system.membus.port[2] 476 477[system.cpu.toL2Bus] 478type=Bus 479block_size=64 480bus_id=0 481clock=1000 482header_cycles=1 483use_default_range=false 484width=64 485port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 486 487[system.cpu.tracer] 488type=ExeTracer 489 490[system.cpu.workload0] 491type=LiveProcess 492cmd=hello 493cwd= 494egid=100 495env= 496errout=cerr 497euid=100 498executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello 499gid=100 500input=cin 501max_stack_size=67108864 502output=cout 503pid=100 504ppid=99 505simpoint=0 506system=system 507uid=100 508 509[system.cpu.workload1] 510type=LiveProcess 511cmd=hello 512cwd= 513egid=100 514env= 515errout=cerr 516euid=100 517executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello 518gid=100 519input=cin 520max_stack_size=67108864 521output=cout 522pid=100 523ppid=99 524simpoint=0 525system=system 526uid=100 527 528[system.membus] 529type=Bus 530block_size=64 531bus_id=0 532clock=1000 533header_cycles=1 534use_default_range=false 535width=64 536port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side 537 538[system.physmem] 539type=PhysicalMemory 540file= 541latency=30000 542latency_var=0 543null=false 544range=0:134217727 545zero=false 546port=system.membus.port[1] 547 548