config.ini revision 11680
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=true 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=branchPred dcache dtb fuPool icache interrupts0 interrupts1 isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred 68cachePorts=200 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 97iewToDecodeDelay=1 98iewToFetchDelay=1 99iewToRenameDelay=1 100interrupts=system.cpu.interrupts0 system.cpu.interrupts1 101isa=system.cpu.isa0 system.cpu.isa1 102issueToExecuteDelay=1 103issueWidth=8 104itb=system.cpu.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109needsTSO=false 110numIQEntries=64 111numPhysCCRegs=0 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=2 117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null 121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= 129smtCommitPolicy=RoundRobin 130smtFetchPolicy=SingleThread 131smtIQPolicy=Partitioned 132smtIQThreshold=100 133smtLSQPolicy=Partitioned 134smtLSQThreshold=100 135smtNumFetchingThreads=1 136smtROBPolicy=Partitioned 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false 142system=system 143tracer=system.cpu.tracer 144trapLatency=13 145wbWidth=8 146workload=system.cpu.workload0 system.cpu.workload1 147dcache_port=system.cpu.dcache.cpu_side 148icache_port=system.cpu.icache.cpu_side 149 150[system.cpu.branchPred] 151type=TournamentBP 152BTBEntries=4096 153BTBTagSize=16 154RASSize=16 155choiceCtrBits=2 156choicePredictorSize=8192 157eventq_index=0 158globalCtrBits=2 159globalPredictorSize=8192 160indirectHashGHR=true 161indirectHashTargets=true 162indirectPathLength=3 163indirectSets=256 164indirectTagSize=16 165indirectWays=2 166instShiftAmt=2 167localCtrBits=2 168localHistoryTableSize=2048 169localPredictorSize=2048 170numThreads=2 171useIndirect=true 172 173[system.cpu.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615:0:0:0:0 177assoc=2 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl 180default_p_state=UNDEFINED 181demand_mshr_reserve=1 182eventq_index=0 183hit_latency=2 184is_read_only=false 185max_miss_count=0 186mshrs=4 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=262144 196system=system 197tags=system.cpu.dcache.tags 198tgts_per_mshr=20 199write_buffers=8 200writeback_clean=false 201cpu_side=system.cpu.dcache_port 202mem_side=system.cpu.toL2Bus.slave[1] 203 204[system.cpu.dcache.tags] 205type=LRU 206assoc=2 207block_size=64 208clk_domain=system.cpu_clk_domain 209default_p_state=UNDEFINED 210eventq_index=0 211hit_latency=2 212p_state_clk_gate_bins=20 213p_state_clk_gate_max=1000000000000 214p_state_clk_gate_min=1000 215power_model=Null 216sequential_access=false 217size=262144 218 219[system.cpu.dtb] 220type=AlphaTLB 221eventq_index=0 222size=64 223 224[system.cpu.fuPool] 225type=FUPool 226children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 227FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 228eventq_index=0 229 230[system.cpu.fuPool.FUList0] 231type=FUDesc 232children=opList 233count=6 234eventq_index=0 235opList=system.cpu.fuPool.FUList0.opList 236 237[system.cpu.fuPool.FUList0.opList] 238type=OpDesc 239eventq_index=0 240opClass=IntAlu 241opLat=1 242pipelined=true 243 244[system.cpu.fuPool.FUList1] 245type=FUDesc 246children=opList0 opList1 247count=2 248eventq_index=0 249opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 250 251[system.cpu.fuPool.FUList1.opList0] 252type=OpDesc 253eventq_index=0 254opClass=IntMult 255opLat=3 256pipelined=true 257 258[system.cpu.fuPool.FUList1.opList1] 259type=OpDesc 260eventq_index=0 261opClass=IntDiv 262opLat=20 263pipelined=false 264 265[system.cpu.fuPool.FUList2] 266type=FUDesc 267children=opList0 opList1 opList2 268count=4 269eventq_index=0 270opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 271 272[system.cpu.fuPool.FUList2.opList0] 273type=OpDesc 274eventq_index=0 275opClass=FloatAdd 276opLat=2 277pipelined=true 278 279[system.cpu.fuPool.FUList2.opList1] 280type=OpDesc 281eventq_index=0 282opClass=FloatCmp 283opLat=2 284pipelined=true 285 286[system.cpu.fuPool.FUList2.opList2] 287type=OpDesc 288eventq_index=0 289opClass=FloatCvt 290opLat=2 291pipelined=true 292 293[system.cpu.fuPool.FUList3] 294type=FUDesc 295children=opList0 opList1 opList2 296count=2 297eventq_index=0 298opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 299 300[system.cpu.fuPool.FUList3.opList0] 301type=OpDesc 302eventq_index=0 303opClass=FloatMult 304opLat=4 305pipelined=true 306 307[system.cpu.fuPool.FUList3.opList1] 308type=OpDesc 309eventq_index=0 310opClass=FloatDiv 311opLat=12 312pipelined=false 313 314[system.cpu.fuPool.FUList3.opList2] 315type=OpDesc 316eventq_index=0 317opClass=FloatSqrt 318opLat=24 319pipelined=false 320 321[system.cpu.fuPool.FUList4] 322type=FUDesc 323children=opList 324count=0 325eventq_index=0 326opList=system.cpu.fuPool.FUList4.opList 327 328[system.cpu.fuPool.FUList4.opList] 329type=OpDesc 330eventq_index=0 331opClass=MemRead 332opLat=1 333pipelined=true 334 335[system.cpu.fuPool.FUList5] 336type=FUDesc 337children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 338count=4 339eventq_index=0 340opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 341 342[system.cpu.fuPool.FUList5.opList00] 343type=OpDesc 344eventq_index=0 345opClass=SimdAdd 346opLat=1 347pipelined=true 348 349[system.cpu.fuPool.FUList5.opList01] 350type=OpDesc 351eventq_index=0 352opClass=SimdAddAcc 353opLat=1 354pipelined=true 355 356[system.cpu.fuPool.FUList5.opList02] 357type=OpDesc 358eventq_index=0 359opClass=SimdAlu 360opLat=1 361pipelined=true 362 363[system.cpu.fuPool.FUList5.opList03] 364type=OpDesc 365eventq_index=0 366opClass=SimdCmp 367opLat=1 368pipelined=true 369 370[system.cpu.fuPool.FUList5.opList04] 371type=OpDesc 372eventq_index=0 373opClass=SimdCvt 374opLat=1 375pipelined=true 376 377[system.cpu.fuPool.FUList5.opList05] 378type=OpDesc 379eventq_index=0 380opClass=SimdMisc 381opLat=1 382pipelined=true 383 384[system.cpu.fuPool.FUList5.opList06] 385type=OpDesc 386eventq_index=0 387opClass=SimdMult 388opLat=1 389pipelined=true 390 391[system.cpu.fuPool.FUList5.opList07] 392type=OpDesc 393eventq_index=0 394opClass=SimdMultAcc 395opLat=1 396pipelined=true 397 398[system.cpu.fuPool.FUList5.opList08] 399type=OpDesc 400eventq_index=0 401opClass=SimdShift 402opLat=1 403pipelined=true 404 405[system.cpu.fuPool.FUList5.opList09] 406type=OpDesc 407eventq_index=0 408opClass=SimdShiftAcc 409opLat=1 410pipelined=true 411 412[system.cpu.fuPool.FUList5.opList10] 413type=OpDesc 414eventq_index=0 415opClass=SimdSqrt 416opLat=1 417pipelined=true 418 419[system.cpu.fuPool.FUList5.opList11] 420type=OpDesc 421eventq_index=0 422opClass=SimdFloatAdd 423opLat=1 424pipelined=true 425 426[system.cpu.fuPool.FUList5.opList12] 427type=OpDesc 428eventq_index=0 429opClass=SimdFloatAlu 430opLat=1 431pipelined=true 432 433[system.cpu.fuPool.FUList5.opList13] 434type=OpDesc 435eventq_index=0 436opClass=SimdFloatCmp 437opLat=1 438pipelined=true 439 440[system.cpu.fuPool.FUList5.opList14] 441type=OpDesc 442eventq_index=0 443opClass=SimdFloatCvt 444opLat=1 445pipelined=true 446 447[system.cpu.fuPool.FUList5.opList15] 448type=OpDesc 449eventq_index=0 450opClass=SimdFloatDiv 451opLat=1 452pipelined=true 453 454[system.cpu.fuPool.FUList5.opList16] 455type=OpDesc 456eventq_index=0 457opClass=SimdFloatMisc 458opLat=1 459pipelined=true 460 461[system.cpu.fuPool.FUList5.opList17] 462type=OpDesc 463eventq_index=0 464opClass=SimdFloatMult 465opLat=1 466pipelined=true 467 468[system.cpu.fuPool.FUList5.opList18] 469type=OpDesc 470eventq_index=0 471opClass=SimdFloatMultAcc 472opLat=1 473pipelined=true 474 475[system.cpu.fuPool.FUList5.opList19] 476type=OpDesc 477eventq_index=0 478opClass=SimdFloatSqrt 479opLat=1 480pipelined=true 481 482[system.cpu.fuPool.FUList6] 483type=FUDesc 484children=opList 485count=0 486eventq_index=0 487opList=system.cpu.fuPool.FUList6.opList 488 489[system.cpu.fuPool.FUList6.opList] 490type=OpDesc 491eventq_index=0 492opClass=MemWrite 493opLat=1 494pipelined=true 495 496[system.cpu.fuPool.FUList7] 497type=FUDesc 498children=opList0 opList1 499count=4 500eventq_index=0 501opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 502 503[system.cpu.fuPool.FUList7.opList0] 504type=OpDesc 505eventq_index=0 506opClass=MemRead 507opLat=1 508pipelined=true 509 510[system.cpu.fuPool.FUList7.opList1] 511type=OpDesc 512eventq_index=0 513opClass=MemWrite 514opLat=1 515pipelined=true 516 517[system.cpu.fuPool.FUList8] 518type=FUDesc 519children=opList 520count=1 521eventq_index=0 522opList=system.cpu.fuPool.FUList8.opList 523 524[system.cpu.fuPool.FUList8.opList] 525type=OpDesc 526eventq_index=0 527opClass=IprAccess 528opLat=3 529pipelined=false 530 531[system.cpu.icache] 532type=Cache 533children=tags 534addr_ranges=0:18446744073709551615:0:0:0:0 535assoc=2 536clk_domain=system.cpu_clk_domain 537clusivity=mostly_incl 538default_p_state=UNDEFINED 539demand_mshr_reserve=1 540eventq_index=0 541hit_latency=2 542is_read_only=true 543max_miss_count=0 544mshrs=4 545p_state_clk_gate_bins=20 546p_state_clk_gate_max=1000000000000 547p_state_clk_gate_min=1000 548power_model=Null 549prefetch_on_access=false 550prefetcher=Null 551response_latency=2 552sequential_access=false 553size=131072 554system=system 555tags=system.cpu.icache.tags 556tgts_per_mshr=20 557write_buffers=8 558writeback_clean=true 559cpu_side=system.cpu.icache_port 560mem_side=system.cpu.toL2Bus.slave[0] 561 562[system.cpu.icache.tags] 563type=LRU 564assoc=2 565block_size=64 566clk_domain=system.cpu_clk_domain 567default_p_state=UNDEFINED 568eventq_index=0 569hit_latency=2 570p_state_clk_gate_bins=20 571p_state_clk_gate_max=1000000000000 572p_state_clk_gate_min=1000 573power_model=Null 574sequential_access=false 575size=131072 576 577[system.cpu.interrupts0] 578type=AlphaInterrupts 579eventq_index=0 580 581[system.cpu.interrupts1] 582type=AlphaInterrupts 583eventq_index=0 584 585[system.cpu.isa0] 586type=AlphaISA 587eventq_index=0 588system=system 589 590[system.cpu.isa1] 591type=AlphaISA 592eventq_index=0 593system=system 594 595[system.cpu.itb] 596type=AlphaTLB 597eventq_index=0 598size=48 599 600[system.cpu.l2cache] 601type=Cache 602children=tags 603addr_ranges=0:18446744073709551615:0:0:0:0 604assoc=8 605clk_domain=system.cpu_clk_domain 606clusivity=mostly_incl 607default_p_state=UNDEFINED 608demand_mshr_reserve=1 609eventq_index=0 610hit_latency=20 611is_read_only=false 612max_miss_count=0 613mshrs=20 614p_state_clk_gate_bins=20 615p_state_clk_gate_max=1000000000000 616p_state_clk_gate_min=1000 617power_model=Null 618prefetch_on_access=false 619prefetcher=Null 620response_latency=20 621sequential_access=false 622size=2097152 623system=system 624tags=system.cpu.l2cache.tags 625tgts_per_mshr=12 626write_buffers=8 627writeback_clean=false 628cpu_side=system.cpu.toL2Bus.master[0] 629mem_side=system.membus.slave[1] 630 631[system.cpu.l2cache.tags] 632type=LRU 633assoc=8 634block_size=64 635clk_domain=system.cpu_clk_domain 636default_p_state=UNDEFINED 637eventq_index=0 638hit_latency=20 639p_state_clk_gate_bins=20 640p_state_clk_gate_max=1000000000000 641p_state_clk_gate_min=1000 642power_model=Null 643sequential_access=false 644size=2097152 645 646[system.cpu.toL2Bus] 647type=CoherentXBar 648children=snoop_filter 649clk_domain=system.cpu_clk_domain 650default_p_state=UNDEFINED 651eventq_index=0 652forward_latency=0 653frontend_latency=1 654p_state_clk_gate_bins=20 655p_state_clk_gate_max=1000000000000 656p_state_clk_gate_min=1000 657point_of_coherency=false 658power_model=Null 659response_latency=1 660snoop_filter=system.cpu.toL2Bus.snoop_filter 661snoop_response_latency=1 662system=system 663use_default_range=false 664width=32 665master=system.cpu.l2cache.cpu_side 666slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 667 668[system.cpu.toL2Bus.snoop_filter] 669type=SnoopFilter 670eventq_index=0 671lookup_latency=0 672max_capacity=8388608 673system=system 674 675[system.cpu.tracer] 676type=ExeTracer 677eventq_index=0 678 679[system.cpu.workload0] 680type=LiveProcess 681cmd=hello 682cwd= 683drivers= 684egid=100 685env= 686errout=cerr 687euid=100 688eventq_index=0 689executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello 690gid=100 691input=cin 692kvmInSE=false 693max_stack_size=67108864 694output=cout 695pid=100 696ppid=99 697simpoint=0 698system=system 699uid=100 700useArchPT=false 701 702[system.cpu.workload1] 703type=LiveProcess 704cmd=hello 705cwd= 706drivers= 707egid=100 708env= 709errout=cerr 710euid=100 711eventq_index=0 712executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello 713gid=100 714input=cin 715kvmInSE=false 716max_stack_size=67108864 717output=cout 718pid=100 719ppid=99 720simpoint=0 721system=system 722uid=100 723useArchPT=false 724 725[system.cpu_clk_domain] 726type=SrcClockDomain 727clock=500 728domain_id=-1 729eventq_index=0 730init_perf_level=0 731voltage_domain=system.voltage_domain 732 733[system.dvfs_handler] 734type=DVFSHandler 735domains= 736enable=false 737eventq_index=0 738sys_clk_domain=system.clk_domain 739transition_latency=100000000 740 741[system.membus] 742type=CoherentXBar 743children=snoop_filter 744clk_domain=system.clk_domain 745default_p_state=UNDEFINED 746eventq_index=0 747forward_latency=4 748frontend_latency=3 749p_state_clk_gate_bins=20 750p_state_clk_gate_max=1000000000000 751p_state_clk_gate_min=1000 752point_of_coherency=true 753power_model=Null 754response_latency=2 755snoop_filter=system.membus.snoop_filter 756snoop_response_latency=4 757system=system 758use_default_range=false 759width=16 760master=system.physmem.port 761slave=system.system_port system.cpu.l2cache.mem_side 762 763[system.membus.snoop_filter] 764type=SnoopFilter 765eventq_index=0 766lookup_latency=1 767max_capacity=8388608 768system=system 769 770[system.physmem] 771type=DRAMCtrl 772IDD0=0.055000 773IDD02=0.000000 774IDD2N=0.032000 775IDD2N2=0.000000 776IDD2P0=0.000000 777IDD2P02=0.000000 778IDD2P1=0.032000 779IDD2P12=0.000000 780IDD3N=0.038000 781IDD3N2=0.000000 782IDD3P0=0.000000 783IDD3P02=0.000000 784IDD3P1=0.038000 785IDD3P12=0.000000 786IDD4R=0.157000 787IDD4R2=0.000000 788IDD4W=0.125000 789IDD4W2=0.000000 790IDD5=0.235000 791IDD52=0.000000 792IDD6=0.020000 793IDD62=0.000000 794VDD=1.500000 795VDD2=0.000000 796activation_limit=4 797addr_mapping=RoRaBaCoCh 798bank_groups_per_rank=0 799banks_per_rank=8 800burst_length=8 801channels=1 802clk_domain=system.clk_domain 803conf_table_reported=true 804default_p_state=UNDEFINED 805device_bus_width=8 806device_rowbuffer_size=1024 807device_size=536870912 808devices_per_rank=8 809dll=true 810eventq_index=0 811in_addr_map=true 812kvm_map=true 813max_accesses_per_row=16 814mem_sched_policy=frfcfs 815min_writes_per_switch=16 816null=false 817p_state_clk_gate_bins=20 818p_state_clk_gate_max=1000000000000 819p_state_clk_gate_min=1000 820page_policy=open_adaptive 821power_model=Null 822range=0:134217727:0:0:0:0 823ranks_per_channel=2 824read_buffer_size=32 825static_backend_latency=10000 826static_frontend_latency=10000 827tBURST=5000 828tCCD_L=0 829tCK=1250 830tCL=13750 831tCS=2500 832tRAS=35000 833tRCD=13750 834tREFI=7800000 835tRFC=260000 836tRP=13750 837tRRD=6000 838tRRD_L=0 839tRTP=7500 840tRTW=2500 841tWR=15000 842tWTR=7500 843tXAW=30000 844tXP=6000 845tXPDLL=0 846tXS=270000 847tXSDLL=0 848write_buffer_size=64 849write_high_thresh_perc=85 850write_low_thresh_perc=50 851port=system.membus.master[0] 852 853[system.voltage_domain] 854type=VoltageDomain 855eventq_index=0 856voltage=1.000000 857 858