config.ini revision 9924:31ef410b6843
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= 23symbolfile= 24work_begin_ckpt_count=0 25work_begin_cpu_id_exit=-1 26work_begin_exit_count=0 27work_cpus_ckpt_count=0 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 36voltage_domain=system.voltage_domain 37 38[system.cpu] 39type=DerivO3CPU 40children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 41LFSTSize=1024 42LQEntries=32 43LSQCheckLoads=true 44LSQDepCheckShift=4 45SQEntries=32 46SSITSize=1024 47UnifiedTLB=true 48activity=0 49backComSize=5 50branchPred=system.cpu.branchPred 51cachePorts=200 52checker=Null 53clk_domain=system.cpu_clk_domain 54commitToDecodeDelay=1 55commitToFetchDelay=1 56commitToIEWDelay=1 57commitToRenameDelay=1 58commitWidth=8 59cpu_id=0 60decodeToFetchDelay=1 61decodeToRenameDelay=1 62decodeWidth=8 63dispatchWidth=8 64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dtb=system.cpu.dtb 68fetchToDecodeDelay=1 69fetchTrapLatency=1 70fetchWidth=8 71forwardComSize=5 72fuPool=system.cpu.fuPool 73function_trace=false 74function_trace_start=0 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79interrupts=system.cpu.interrupts 80isa=system.cpu.isa 81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84max_insts_all_threads=0 85max_insts_any_thread=0 86max_loads_all_threads=0 87max_loads_any_thread=0 88needsTSO=false 89numIQEntries=64 90numPhysCCRegs=0 91numPhysFloatRegs=256 92numPhysIntRegs=256 93numROBEntries=192 94numRobs=1 95numThreads=1 96profile=0 97progress_interval=0 98renameToDecodeDelay=1 99renameToFetchDelay=1 100renameToIEWDelay=2 101renameToROBDelay=1 102renameWidth=8 103simpoint_start_insts= 104smtCommitPolicy=RoundRobin 105smtFetchPolicy=SingleThread 106smtIQPolicy=Partitioned 107smtIQThreshold=100 108smtLSQPolicy=Partitioned 109smtLSQThreshold=100 110smtNumFetchingThreads=1 111smtROBPolicy=Partitioned 112smtROBThreshold=100 113squashWidth=8 114store_set_clear_period=250000 115switched_out=false 116system=system 117tracer=system.cpu.tracer 118trapLatency=13 119wbDepth=1 120wbWidth=8 121workload=system.cpu.workload 122dcache_port=system.cpu.dcache.cpu_side 123icache_port=system.cpu.icache.cpu_side 124 125[system.cpu.branchPred] 126type=BranchPredictor 127BTBEntries=4096 128BTBTagSize=16 129RASSize=16 130choiceCtrBits=2 131choicePredictorSize=8192 132globalCtrBits=2 133globalPredictorSize=8192 134instShiftAmt=2 135localCtrBits=2 136localHistoryTableSize=2048 137localPredictorSize=2048 138numThreads=1 139predType=tournament 140 141[system.cpu.dcache] 142type=BaseCache 143children=tags 144addr_ranges=0:18446744073709551615 145assoc=2 146clk_domain=system.cpu_clk_domain 147forward_snoops=true 148hit_latency=2 149is_top_level=true 150max_miss_count=0 151mshrs=4 152prefetch_on_access=false 153prefetcher=Null 154response_latency=2 155size=262144 156system=system 157tags=system.cpu.dcache.tags 158tgts_per_mshr=20 159two_queue=false 160write_buffers=8 161cpu_side=system.cpu.dcache_port 162mem_side=system.cpu.toL2Bus.slave[1] 163 164[system.cpu.dcache.tags] 165type=LRU 166assoc=2 167block_size=64 168clk_domain=system.cpu_clk_domain 169hit_latency=2 170size=262144 171 172[system.cpu.dtb] 173type=PowerTLB 174size=64 175 176[system.cpu.fuPool] 177type=FUPool 178children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 179FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 180 181[system.cpu.fuPool.FUList0] 182type=FUDesc 183children=opList 184count=6 185opList=system.cpu.fuPool.FUList0.opList 186 187[system.cpu.fuPool.FUList0.opList] 188type=OpDesc 189issueLat=1 190opClass=IntAlu 191opLat=1 192 193[system.cpu.fuPool.FUList1] 194type=FUDesc 195children=opList0 opList1 196count=2 197opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 198 199[system.cpu.fuPool.FUList1.opList0] 200type=OpDesc 201issueLat=1 202opClass=IntMult 203opLat=3 204 205[system.cpu.fuPool.FUList1.opList1] 206type=OpDesc 207issueLat=19 208opClass=IntDiv 209opLat=20 210 211[system.cpu.fuPool.FUList2] 212type=FUDesc 213children=opList0 opList1 opList2 214count=4 215opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 216 217[system.cpu.fuPool.FUList2.opList0] 218type=OpDesc 219issueLat=1 220opClass=FloatAdd 221opLat=2 222 223[system.cpu.fuPool.FUList2.opList1] 224type=OpDesc 225issueLat=1 226opClass=FloatCmp 227opLat=2 228 229[system.cpu.fuPool.FUList2.opList2] 230type=OpDesc 231issueLat=1 232opClass=FloatCvt 233opLat=2 234 235[system.cpu.fuPool.FUList3] 236type=FUDesc 237children=opList0 opList1 opList2 238count=2 239opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 240 241[system.cpu.fuPool.FUList3.opList0] 242type=OpDesc 243issueLat=1 244opClass=FloatMult 245opLat=4 246 247[system.cpu.fuPool.FUList3.opList1] 248type=OpDesc 249issueLat=12 250opClass=FloatDiv 251opLat=12 252 253[system.cpu.fuPool.FUList3.opList2] 254type=OpDesc 255issueLat=24 256opClass=FloatSqrt 257opLat=24 258 259[system.cpu.fuPool.FUList4] 260type=FUDesc 261children=opList 262count=0 263opList=system.cpu.fuPool.FUList4.opList 264 265[system.cpu.fuPool.FUList4.opList] 266type=OpDesc 267issueLat=1 268opClass=MemRead 269opLat=1 270 271[system.cpu.fuPool.FUList5] 272type=FUDesc 273children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 274count=4 275opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 276 277[system.cpu.fuPool.FUList5.opList00] 278type=OpDesc 279issueLat=1 280opClass=SimdAdd 281opLat=1 282 283[system.cpu.fuPool.FUList5.opList01] 284type=OpDesc 285issueLat=1 286opClass=SimdAddAcc 287opLat=1 288 289[system.cpu.fuPool.FUList5.opList02] 290type=OpDesc 291issueLat=1 292opClass=SimdAlu 293opLat=1 294 295[system.cpu.fuPool.FUList5.opList03] 296type=OpDesc 297issueLat=1 298opClass=SimdCmp 299opLat=1 300 301[system.cpu.fuPool.FUList5.opList04] 302type=OpDesc 303issueLat=1 304opClass=SimdCvt 305opLat=1 306 307[system.cpu.fuPool.FUList5.opList05] 308type=OpDesc 309issueLat=1 310opClass=SimdMisc 311opLat=1 312 313[system.cpu.fuPool.FUList5.opList06] 314type=OpDesc 315issueLat=1 316opClass=SimdMult 317opLat=1 318 319[system.cpu.fuPool.FUList5.opList07] 320type=OpDesc 321issueLat=1 322opClass=SimdMultAcc 323opLat=1 324 325[system.cpu.fuPool.FUList5.opList08] 326type=OpDesc 327issueLat=1 328opClass=SimdShift 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList09] 332type=OpDesc 333issueLat=1 334opClass=SimdShiftAcc 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList10] 338type=OpDesc 339issueLat=1 340opClass=SimdSqrt 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList11] 344type=OpDesc 345issueLat=1 346opClass=SimdFloatAdd 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList12] 350type=OpDesc 351issueLat=1 352opClass=SimdFloatAlu 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList13] 356type=OpDesc 357issueLat=1 358opClass=SimdFloatCmp 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList14] 362type=OpDesc 363issueLat=1 364opClass=SimdFloatCvt 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList15] 368type=OpDesc 369issueLat=1 370opClass=SimdFloatDiv 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList16] 374type=OpDesc 375issueLat=1 376opClass=SimdFloatMisc 377opLat=1 378 379[system.cpu.fuPool.FUList5.opList17] 380type=OpDesc 381issueLat=1 382opClass=SimdFloatMult 383opLat=1 384 385[system.cpu.fuPool.FUList5.opList18] 386type=OpDesc 387issueLat=1 388opClass=SimdFloatMultAcc 389opLat=1 390 391[system.cpu.fuPool.FUList5.opList19] 392type=OpDesc 393issueLat=1 394opClass=SimdFloatSqrt 395opLat=1 396 397[system.cpu.fuPool.FUList6] 398type=FUDesc 399children=opList 400count=0 401opList=system.cpu.fuPool.FUList6.opList 402 403[system.cpu.fuPool.FUList6.opList] 404type=OpDesc 405issueLat=1 406opClass=MemWrite 407opLat=1 408 409[system.cpu.fuPool.FUList7] 410type=FUDesc 411children=opList0 opList1 412count=4 413opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 414 415[system.cpu.fuPool.FUList7.opList0] 416type=OpDesc 417issueLat=1 418opClass=MemRead 419opLat=1 420 421[system.cpu.fuPool.FUList7.opList1] 422type=OpDesc 423issueLat=1 424opClass=MemWrite 425opLat=1 426 427[system.cpu.fuPool.FUList8] 428type=FUDesc 429children=opList 430count=1 431opList=system.cpu.fuPool.FUList8.opList 432 433[system.cpu.fuPool.FUList8.opList] 434type=OpDesc 435issueLat=3 436opClass=IprAccess 437opLat=3 438 439[system.cpu.icache] 440type=BaseCache 441children=tags 442addr_ranges=0:18446744073709551615 443assoc=2 444clk_domain=system.cpu_clk_domain 445forward_snoops=true 446hit_latency=2 447is_top_level=true 448max_miss_count=0 449mshrs=4 450prefetch_on_access=false 451prefetcher=Null 452response_latency=2 453size=131072 454system=system 455tags=system.cpu.icache.tags 456tgts_per_mshr=20 457two_queue=false 458write_buffers=8 459cpu_side=system.cpu.icache_port 460mem_side=system.cpu.toL2Bus.slave[0] 461 462[system.cpu.icache.tags] 463type=LRU 464assoc=2 465block_size=64 466clk_domain=system.cpu_clk_domain 467hit_latency=2 468size=131072 469 470[system.cpu.interrupts] 471type=PowerInterrupts 472 473[system.cpu.isa] 474type=PowerISA 475 476[system.cpu.itb] 477type=PowerTLB 478size=64 479 480[system.cpu.l2cache] 481type=BaseCache 482children=tags 483addr_ranges=0:18446744073709551615 484assoc=8 485clk_domain=system.cpu_clk_domain 486forward_snoops=true 487hit_latency=20 488is_top_level=false 489max_miss_count=0 490mshrs=20 491prefetch_on_access=false 492prefetcher=Null 493response_latency=20 494size=2097152 495system=system 496tags=system.cpu.l2cache.tags 497tgts_per_mshr=12 498two_queue=false 499write_buffers=8 500cpu_side=system.cpu.toL2Bus.master[0] 501mem_side=system.membus.slave[1] 502 503[system.cpu.l2cache.tags] 504type=LRU 505assoc=8 506block_size=64 507clk_domain=system.cpu_clk_domain 508hit_latency=20 509size=2097152 510 511[system.cpu.toL2Bus] 512type=CoherentBus 513clk_domain=system.cpu_clk_domain 514header_cycles=1 515system=system 516use_default_range=false 517width=32 518master=system.cpu.l2cache.cpu_side 519slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 520 521[system.cpu.tracer] 522type=ExeTracer 523 524[system.cpu.workload] 525type=LiveProcess 526cmd=hello 527cwd= 528egid=100 529env= 530errout=cerr 531euid=100 532executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello 533gid=100 534input=cin 535max_stack_size=67108864 536output=cout 537pid=100 538ppid=99 539simpoint=0 540system=system 541uid=100 542 543[system.cpu_clk_domain] 544type=SrcClockDomain 545clock=500 546voltage_domain=system.voltage_domain 547 548[system.membus] 549type=CoherentBus 550clk_domain=system.clk_domain 551header_cycles=1 552system=system 553use_default_range=false 554width=8 555master=system.physmem.port 556slave=system.system_port system.cpu.l2cache.mem_side 557 558[system.physmem] 559type=SimpleDRAM 560activation_limit=4 561addr_mapping=RaBaChCo 562banks_per_rank=8 563burst_length=8 564channels=1 565clk_domain=system.clk_domain 566conf_table_reported=true 567device_bus_width=8 568device_rowbuffer_size=1024 569devices_per_rank=8 570in_addr_map=true 571mem_sched_policy=frfcfs 572null=false 573page_policy=open 574range=0:134217727 575ranks_per_channel=2 576read_buffer_size=32 577static_backend_latency=10000 578static_frontend_latency=10000 579tBURST=5000 580tCL=13750 581tRCD=13750 582tREFI=7800000 583tRFC=300000 584tRP=13750 585tWTR=7500 586tXAW=40000 587write_buffer_size=32 588write_thresh_perc=70 589port=system.membus.master[0] 590 591[system.voltage_domain] 592type=VoltageDomain 593voltage=1.000000 594 595