1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65UnifiedTLB=true 66activity=0 67backComSize=5 68branchPred=system.cpu.branchPred 69cacheStorePorts=200 70checker=Null 71clk_domain=system.cpu_clk_domain 72commitToDecodeDelay=1 73commitToFetchDelay=1 74commitToIEWDelay=1 75commitToRenameDelay=1 76commitWidth=8 77cpu_id=0 78decodeToFetchDelay=1 79decodeToRenameDelay=1 80decodeWidth=8 81default_p_state=UNDEFINED 82dispatchWidth=8 83do_checkpoint_insts=true 84do_quiesce=true 85do_statistics_insts=true 86dtb=system.cpu.dtb 87eventq_index=0 88fetchBufferSize=64 89fetchQueueSize=32 90fetchToDecodeDelay=1 91fetchTrapLatency=1 92fetchWidth=8 93forwardComSize=5 94fuPool=system.cpu.fuPool 95function_trace=false 96function_trace_start=0 97iewToCommitDelay=1 98iewToDecodeDelay=1 99iewToFetchDelay=1 100iewToRenameDelay=1 101interrupts=system.cpu.interrupts 102isa=system.cpu.isa 103issueToExecuteDelay=1 104issueWidth=8 105itb=system.cpu.itb 106max_insts_all_threads=0 107max_insts_any_thread=0 108max_loads_all_threads=0 109max_loads_any_thread=0 110needsTSO=false 111numIQEntries=64 112numPhysCCRegs=0 113numPhysFloatRegs=256 114numPhysIntRegs=256 115numROBEntries=192 116numRobs=1 117numThreads=1 118p_state_clk_gate_bins=20 119p_state_clk_gate_max=1000000000000 120p_state_clk_gate_min=1000 121power_model=Null 122profile=0 123progress_interval=0 124renameToDecodeDelay=1 125renameToFetchDelay=1 126renameToIEWDelay=2 127renameToROBDelay=1 128renameWidth=8 129simpoint_start_insts= 130smtCommitPolicy=RoundRobin 131smtFetchPolicy=SingleThread 132smtIQPolicy=Partitioned 133smtIQThreshold=100 134smtLSQPolicy=Partitioned 135smtLSQThreshold=100 136smtNumFetchingThreads=1 137smtROBPolicy=Partitioned 138smtROBThreshold=100 139socket_id=0 140squashWidth=8 141store_set_clear_period=250000 142switched_out=false 143syscallRetryLatency=10000 144system=system 145tracer=system.cpu.tracer 146trapLatency=13 147wbWidth=8 148workload=system.cpu.workload 149dcache_port=system.cpu.dcache.cpu_side 150icache_port=system.cpu.icache.cpu_side 151 152[system.cpu.branchPred] 153type=TournamentBP 154BTBEntries=4096 155BTBTagSize=16 156RASSize=16 157choiceCtrBits=2 158choicePredictorSize=8192 159eventq_index=0 160globalCtrBits=2 161globalPredictorSize=8192 162indirectHashGHR=true 163indirectHashTargets=true 164indirectPathLength=3 165indirectSets=256 166indirectTagSize=16 167indirectWays=2 168instShiftAmt=2 169localCtrBits=2 170localHistoryTableSize=2048 171localPredictorSize=2048 172numThreads=1 173useIndirect=true 174 175[system.cpu.dcache] 176type=Cache 177children=tags 178addr_ranges=0:18446744073709551615:0:0:0:0 179assoc=2 180clk_domain=system.cpu_clk_domain 181clusivity=mostly_incl 182data_latency=2 183default_p_state=UNDEFINED 184demand_mshr_reserve=1 185eventq_index=0 186is_read_only=false 187max_miss_count=0 188mshrs=4 189p_state_clk_gate_bins=20 190p_state_clk_gate_max=1000000000000 191p_state_clk_gate_min=1000 192power_model=Null 193prefetch_on_access=false 194prefetcher=Null 195response_latency=2 196sequential_access=false 197size=262144 198system=system 199tag_latency=2 200tags=system.cpu.dcache.tags 201tgts_per_mshr=20 202write_buffers=8 203writeback_clean=false 204cpu_side=system.cpu.dcache_port 205mem_side=system.cpu.toL2Bus.slave[1] 206 207[system.cpu.dcache.tags] 208type=LRU 209assoc=2 210block_size=64 211clk_domain=system.cpu_clk_domain 212data_latency=2 213default_p_state=UNDEFINED 214eventq_index=0 215p_state_clk_gate_bins=20 216p_state_clk_gate_max=1000000000000 217p_state_clk_gate_min=1000 218power_model=Null 219sequential_access=false 220size=262144 221tag_latency=2 222 223[system.cpu.dtb] 224type=PowerTLB 225eventq_index=0 226size=64 227 228[system.cpu.fuPool] 229type=FUPool 230children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 231FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 232eventq_index=0 233 234[system.cpu.fuPool.FUList0] 235type=FUDesc 236children=opList 237count=6 238eventq_index=0 239opList=system.cpu.fuPool.FUList0.opList 240 241[system.cpu.fuPool.FUList0.opList] 242type=OpDesc 243eventq_index=0 244opClass=IntAlu 245opLat=1 246pipelined=true 247 248[system.cpu.fuPool.FUList1] 249type=FUDesc 250children=opList0 opList1 251count=2 252eventq_index=0 253opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 254 255[system.cpu.fuPool.FUList1.opList0] 256type=OpDesc 257eventq_index=0 258opClass=IntMult 259opLat=3 260pipelined=true 261 262[system.cpu.fuPool.FUList1.opList1] 263type=OpDesc 264eventq_index=0 265opClass=IntDiv 266opLat=20 267pipelined=false 268 269[system.cpu.fuPool.FUList2] 270type=FUDesc 271children=opList0 opList1 opList2 272count=4 273eventq_index=0 274opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 275 276[system.cpu.fuPool.FUList2.opList0] 277type=OpDesc 278eventq_index=0 279opClass=FloatAdd 280opLat=2 281pipelined=true 282 283[system.cpu.fuPool.FUList2.opList1] 284type=OpDesc 285eventq_index=0 286opClass=FloatCmp 287opLat=2 288pipelined=true 289 290[system.cpu.fuPool.FUList2.opList2] 291type=OpDesc 292eventq_index=0 293opClass=FloatCvt 294opLat=2 295pipelined=true 296 297[system.cpu.fuPool.FUList3] 298type=FUDesc 299children=opList0 opList1 opList2 opList3 opList4 300count=2 301eventq_index=0 302opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 303 304[system.cpu.fuPool.FUList3.opList0] 305type=OpDesc 306eventq_index=0 307opClass=FloatMult 308opLat=4 309pipelined=true 310 311[system.cpu.fuPool.FUList3.opList1] 312type=OpDesc 313eventq_index=0 314opClass=FloatMultAcc 315opLat=5 316pipelined=true 317 318[system.cpu.fuPool.FUList3.opList2] 319type=OpDesc 320eventq_index=0 321opClass=FloatMisc 322opLat=3 323pipelined=true 324 325[system.cpu.fuPool.FUList3.opList3] 326type=OpDesc 327eventq_index=0 328opClass=FloatDiv 329opLat=12 330pipelined=false 331 332[system.cpu.fuPool.FUList3.opList4] 333type=OpDesc 334eventq_index=0 335opClass=FloatSqrt 336opLat=24 337pipelined=false 338 339[system.cpu.fuPool.FUList4] 340type=FUDesc 341children=opList0 opList1 342count=0 343eventq_index=0 344opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 345 346[system.cpu.fuPool.FUList4.opList0] 347type=OpDesc 348eventq_index=0 349opClass=MemRead 350opLat=1 351pipelined=true 352 353[system.cpu.fuPool.FUList4.opList1] 354type=OpDesc 355eventq_index=0 356opClass=FloatMemRead 357opLat=1 358pipelined=true 359 360[system.cpu.fuPool.FUList5] 361type=FUDesc 362children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 363count=4 364eventq_index=0 365opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 366 367[system.cpu.fuPool.FUList5.opList00] 368type=OpDesc 369eventq_index=0 370opClass=SimdAdd 371opLat=1 372pipelined=true 373 374[system.cpu.fuPool.FUList5.opList01] 375type=OpDesc 376eventq_index=0 377opClass=SimdAddAcc 378opLat=1 379pipelined=true 380 381[system.cpu.fuPool.FUList5.opList02] 382type=OpDesc 383eventq_index=0 384opClass=SimdAlu 385opLat=1 386pipelined=true 387 388[system.cpu.fuPool.FUList5.opList03] 389type=OpDesc 390eventq_index=0 391opClass=SimdCmp 392opLat=1 393pipelined=true 394 395[system.cpu.fuPool.FUList5.opList04] 396type=OpDesc 397eventq_index=0 398opClass=SimdCvt 399opLat=1 400pipelined=true 401 402[system.cpu.fuPool.FUList5.opList05] 403type=OpDesc 404eventq_index=0 405opClass=SimdMisc 406opLat=1 407pipelined=true 408 409[system.cpu.fuPool.FUList5.opList06] 410type=OpDesc 411eventq_index=0 412opClass=SimdMult 413opLat=1 414pipelined=true 415 416[system.cpu.fuPool.FUList5.opList07] 417type=OpDesc 418eventq_index=0 419opClass=SimdMultAcc 420opLat=1 421pipelined=true 422 423[system.cpu.fuPool.FUList5.opList08] 424type=OpDesc 425eventq_index=0 426opClass=SimdShift 427opLat=1 428pipelined=true 429 430[system.cpu.fuPool.FUList5.opList09] 431type=OpDesc 432eventq_index=0 433opClass=SimdShiftAcc 434opLat=1 435pipelined=true 436 437[system.cpu.fuPool.FUList5.opList10] 438type=OpDesc 439eventq_index=0 440opClass=SimdSqrt 441opLat=1 442pipelined=true 443 444[system.cpu.fuPool.FUList5.opList11] 445type=OpDesc 446eventq_index=0 447opClass=SimdFloatAdd 448opLat=1 449pipelined=true 450 451[system.cpu.fuPool.FUList5.opList12] 452type=OpDesc 453eventq_index=0 454opClass=SimdFloatAlu 455opLat=1 456pipelined=true 457 458[system.cpu.fuPool.FUList5.opList13] 459type=OpDesc 460eventq_index=0 461opClass=SimdFloatCmp 462opLat=1 463pipelined=true 464 465[system.cpu.fuPool.FUList5.opList14] 466type=OpDesc 467eventq_index=0 468opClass=SimdFloatCvt 469opLat=1 470pipelined=true 471 472[system.cpu.fuPool.FUList5.opList15] 473type=OpDesc 474eventq_index=0 475opClass=SimdFloatDiv 476opLat=1 477pipelined=true 478 479[system.cpu.fuPool.FUList5.opList16] 480type=OpDesc 481eventq_index=0 482opClass=SimdFloatMisc 483opLat=1 484pipelined=true 485 486[system.cpu.fuPool.FUList5.opList17] 487type=OpDesc 488eventq_index=0 489opClass=SimdFloatMult 490opLat=1 491pipelined=true 492 493[system.cpu.fuPool.FUList5.opList18] 494type=OpDesc 495eventq_index=0 496opClass=SimdFloatMultAcc 497opLat=1 498pipelined=true 499 500[system.cpu.fuPool.FUList5.opList19] 501type=OpDesc 502eventq_index=0 503opClass=SimdFloatSqrt 504opLat=1 505pipelined=true 506 507[system.cpu.fuPool.FUList6] 508type=FUDesc 509children=opList0 opList1 510count=0 511eventq_index=0 512opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 513 514[system.cpu.fuPool.FUList6.opList0] 515type=OpDesc 516eventq_index=0 517opClass=MemWrite 518opLat=1 519pipelined=true 520 521[system.cpu.fuPool.FUList6.opList1] 522type=OpDesc 523eventq_index=0 524opClass=FloatMemWrite 525opLat=1 526pipelined=true 527 528[system.cpu.fuPool.FUList7] 529type=FUDesc 530children=opList0 opList1 opList2 opList3 531count=4 532eventq_index=0 533opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 534 535[system.cpu.fuPool.FUList7.opList0] 536type=OpDesc 537eventq_index=0 538opClass=MemRead 539opLat=1 540pipelined=true 541 542[system.cpu.fuPool.FUList7.opList1] 543type=OpDesc 544eventq_index=0 545opClass=MemWrite 546opLat=1 547pipelined=true 548 549[system.cpu.fuPool.FUList7.opList2] 550type=OpDesc 551eventq_index=0 552opClass=FloatMemRead 553opLat=1 554pipelined=true 555 556[system.cpu.fuPool.FUList7.opList3] 557type=OpDesc 558eventq_index=0 559opClass=FloatMemWrite 560opLat=1 561pipelined=true 562 563[system.cpu.fuPool.FUList8] 564type=FUDesc 565children=opList 566count=1 567eventq_index=0 568opList=system.cpu.fuPool.FUList8.opList 569 570[system.cpu.fuPool.FUList8.opList] 571type=OpDesc 572eventq_index=0 573opClass=IprAccess 574opLat=3 575pipelined=false 576 577[system.cpu.icache] 578type=Cache 579children=tags 580addr_ranges=0:18446744073709551615:0:0:0:0 581assoc=2 582clk_domain=system.cpu_clk_domain 583clusivity=mostly_incl 584data_latency=2 585default_p_state=UNDEFINED 586demand_mshr_reserve=1 587eventq_index=0 588is_read_only=true 589max_miss_count=0 590mshrs=4 591p_state_clk_gate_bins=20 592p_state_clk_gate_max=1000000000000 593p_state_clk_gate_min=1000 594power_model=Null 595prefetch_on_access=false 596prefetcher=Null 597response_latency=2 598sequential_access=false 599size=131072 600system=system 601tag_latency=2 602tags=system.cpu.icache.tags 603tgts_per_mshr=20 604write_buffers=8 605writeback_clean=true 606cpu_side=system.cpu.icache_port 607mem_side=system.cpu.toL2Bus.slave[0] 608 609[system.cpu.icache.tags] 610type=LRU 611assoc=2 612block_size=64 613clk_domain=system.cpu_clk_domain 614data_latency=2 615default_p_state=UNDEFINED 616eventq_index=0 617p_state_clk_gate_bins=20 618p_state_clk_gate_max=1000000000000 619p_state_clk_gate_min=1000 620power_model=Null 621sequential_access=false 622size=131072 623tag_latency=2 624 625[system.cpu.interrupts] 626type=PowerInterrupts 627eventq_index=0 628 629[system.cpu.isa] 630type=PowerISA 631eventq_index=0 632 633[system.cpu.itb] 634type=PowerTLB 635eventq_index=0 636size=64 637 638[system.cpu.l2cache] 639type=Cache 640children=tags 641addr_ranges=0:18446744073709551615:0:0:0:0 642assoc=8 643clk_domain=system.cpu_clk_domain 644clusivity=mostly_incl 645data_latency=20 646default_p_state=UNDEFINED 647demand_mshr_reserve=1 648eventq_index=0 649is_read_only=false 650max_miss_count=0 651mshrs=20 652p_state_clk_gate_bins=20 653p_state_clk_gate_max=1000000000000 654p_state_clk_gate_min=1000 655power_model=Null 656prefetch_on_access=false 657prefetcher=Null 658response_latency=20 659sequential_access=false 660size=2097152 661system=system 662tag_latency=20 663tags=system.cpu.l2cache.tags 664tgts_per_mshr=12 665write_buffers=8 666writeback_clean=false 667cpu_side=system.cpu.toL2Bus.master[0] 668mem_side=system.membus.slave[1] 669 670[system.cpu.l2cache.tags] 671type=LRU 672assoc=8 673block_size=64 674clk_domain=system.cpu_clk_domain 675data_latency=20 676default_p_state=UNDEFINED 677eventq_index=0 678p_state_clk_gate_bins=20 679p_state_clk_gate_max=1000000000000 680p_state_clk_gate_min=1000 681power_model=Null 682sequential_access=false 683size=2097152 684tag_latency=20 685 686[system.cpu.toL2Bus] 687type=CoherentXBar 688children=snoop_filter 689clk_domain=system.cpu_clk_domain 690default_p_state=UNDEFINED 691eventq_index=0 692forward_latency=0 693frontend_latency=1 694p_state_clk_gate_bins=20 695p_state_clk_gate_max=1000000000000 696p_state_clk_gate_min=1000 697point_of_coherency=false 698power_model=Null 699response_latency=1 700snoop_filter=system.cpu.toL2Bus.snoop_filter 701snoop_response_latency=1 702system=system 703use_default_range=false 704width=32 705master=system.cpu.l2cache.cpu_side 706slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 707 708[system.cpu.toL2Bus.snoop_filter] 709type=SnoopFilter 710eventq_index=0 711lookup_latency=0 712max_capacity=8388608 713system=system 714 715[system.cpu.tracer] 716type=ExeTracer 717eventq_index=0 718 719[system.cpu.workload] 720type=Process 721cmd=hello 722cwd= 723drivers= 724egid=100 725env= 726errout=cerr 727euid=100 728eventq_index=0 729executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/power/linux/hello 730gid=100 731input=cin 732kvmInSE=false 733maxStackSize=67108864 734output=cout 735pgid=100 736pid=100 737ppid=0 738simpoint=0 739system=system 740uid=100 741useArchPT=false 742 743[system.cpu_clk_domain] 744type=SrcClockDomain 745clock=500 746domain_id=-1 747eventq_index=0 748init_perf_level=0 749voltage_domain=system.voltage_domain 750 751[system.dvfs_handler] 752type=DVFSHandler 753domains= 754enable=false 755eventq_index=0 756sys_clk_domain=system.clk_domain 757transition_latency=100000000 758 759[system.membus] 760type=CoherentXBar 761children=snoop_filter 762clk_domain=system.clk_domain 763default_p_state=UNDEFINED 764eventq_index=0 765forward_latency=4 766frontend_latency=3 767p_state_clk_gate_bins=20 768p_state_clk_gate_max=1000000000000 769p_state_clk_gate_min=1000 770point_of_coherency=true 771power_model=Null 772response_latency=2 773snoop_filter=system.membus.snoop_filter 774snoop_response_latency=4 775system=system 776use_default_range=false 777width=16 778master=system.physmem.port 779slave=system.system_port system.cpu.l2cache.mem_side 780 781[system.membus.snoop_filter] 782type=SnoopFilter 783eventq_index=0 784lookup_latency=1 785max_capacity=8388608 786system=system 787 788[system.physmem] 789type=DRAMCtrl 790IDD0=0.055000 791IDD02=0.000000 792IDD2N=0.032000 793IDD2N2=0.000000 794IDD2P0=0.000000 795IDD2P02=0.000000 796IDD2P1=0.032000 797IDD2P12=0.000000 798IDD3N=0.038000 799IDD3N2=0.000000 800IDD3P0=0.000000 801IDD3P02=0.000000 802IDD3P1=0.038000 803IDD3P12=0.000000 804IDD4R=0.157000 805IDD4R2=0.000000 806IDD4W=0.125000 807IDD4W2=0.000000 808IDD5=0.235000 809IDD52=0.000000 810IDD6=0.020000 811IDD62=0.000000 812VDD=1.500000 813VDD2=0.000000 814activation_limit=4 815addr_mapping=RoRaBaCoCh 816bank_groups_per_rank=0 817banks_per_rank=8 818burst_length=8 819channels=1 820clk_domain=system.clk_domain 821conf_table_reported=true 822default_p_state=UNDEFINED 823device_bus_width=8 824device_rowbuffer_size=1024 825device_size=536870912 826devices_per_rank=8 827dll=true 828eventq_index=0 829in_addr_map=true 830kvm_map=true 831max_accesses_per_row=16 832mem_sched_policy=frfcfs 833min_writes_per_switch=16 834null=false 835p_state_clk_gate_bins=20 836p_state_clk_gate_max=1000000000000 837p_state_clk_gate_min=1000 838page_policy=open_adaptive 839power_model=Null 840range=0:134217727:0:0:0:0 841ranks_per_channel=2 842read_buffer_size=32 843static_backend_latency=10000 844static_frontend_latency=10000 845tBURST=5000 846tCCD_L=0 847tCK=1250 848tCL=13750 849tCS=2500 850tRAS=35000 851tRCD=13750 852tREFI=7800000 853tRFC=260000 854tRP=13750 855tRRD=6000 856tRRD_L=0 857tRTP=7500 858tRTW=2500 859tWR=15000 860tWTR=7500 861tXAW=30000 862tXP=6000 863tXPDLL=0 864tXS=270000 865tXSDLL=0 866write_buffer_size=64 867write_high_thresh_perc=85 868write_low_thresh_perc=50 869port=system.membus.master[0] 870 871[system.voltage_domain] 872type=VoltageDomain 873eventq_index=0 874voltage=1.000000 875 876