config.ini revision 11680:b4d943429dc6
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65UnifiedTLB=true 66activity=0 67backComSize=5 68branchPred=system.cpu.branchPred 69cachePorts=200 70checker=Null 71clk_domain=system.cpu_clk_domain 72commitToDecodeDelay=1 73commitToFetchDelay=1 74commitToIEWDelay=1 75commitToRenameDelay=1 76commitWidth=8 77cpu_id=0 78decodeToFetchDelay=1 79decodeToRenameDelay=1 80decodeWidth=8 81default_p_state=UNDEFINED 82dispatchWidth=8 83do_checkpoint_insts=true 84do_quiesce=true 85do_statistics_insts=true 86dtb=system.cpu.dtb 87eventq_index=0 88fetchBufferSize=64 89fetchQueueSize=32 90fetchToDecodeDelay=1 91fetchTrapLatency=1 92fetchWidth=8 93forwardComSize=5 94fuPool=system.cpu.fuPool 95function_trace=false 96function_trace_start=0 97iewToCommitDelay=1 98iewToDecodeDelay=1 99iewToFetchDelay=1 100iewToRenameDelay=1 101interrupts=system.cpu.interrupts 102isa=system.cpu.isa 103issueToExecuteDelay=1 104issueWidth=8 105itb=system.cpu.itb 106max_insts_all_threads=0 107max_insts_any_thread=0 108max_loads_all_threads=0 109max_loads_any_thread=0 110needsTSO=false 111numIQEntries=64 112numPhysCCRegs=0 113numPhysFloatRegs=256 114numPhysIntRegs=256 115numROBEntries=192 116numRobs=1 117numThreads=1 118p_state_clk_gate_bins=20 119p_state_clk_gate_max=1000000000000 120p_state_clk_gate_min=1000 121power_model=Null 122profile=0 123progress_interval=0 124renameToDecodeDelay=1 125renameToFetchDelay=1 126renameToIEWDelay=2 127renameToROBDelay=1 128renameWidth=8 129simpoint_start_insts= 130smtCommitPolicy=RoundRobin 131smtFetchPolicy=SingleThread 132smtIQPolicy=Partitioned 133smtIQThreshold=100 134smtLSQPolicy=Partitioned 135smtLSQThreshold=100 136smtNumFetchingThreads=1 137smtROBPolicy=Partitioned 138smtROBThreshold=100 139socket_id=0 140squashWidth=8 141store_set_clear_period=250000 142switched_out=false 143system=system 144tracer=system.cpu.tracer 145trapLatency=13 146wbWidth=8 147workload=system.cpu.workload 148dcache_port=system.cpu.dcache.cpu_side 149icache_port=system.cpu.icache.cpu_side 150 151[system.cpu.branchPred] 152type=TournamentBP 153BTBEntries=4096 154BTBTagSize=16 155RASSize=16 156choiceCtrBits=2 157choicePredictorSize=8192 158eventq_index=0 159globalCtrBits=2 160globalPredictorSize=8192 161indirectHashGHR=true 162indirectHashTargets=true 163indirectPathLength=3 164indirectSets=256 165indirectTagSize=16 166indirectWays=2 167instShiftAmt=2 168localCtrBits=2 169localHistoryTableSize=2048 170localPredictorSize=2048 171numThreads=1 172useIndirect=true 173 174[system.cpu.dcache] 175type=Cache 176children=tags 177addr_ranges=0:18446744073709551615:0:0:0:0 178assoc=2 179clk_domain=system.cpu_clk_domain 180clusivity=mostly_incl 181default_p_state=UNDEFINED 182demand_mshr_reserve=1 183eventq_index=0 184hit_latency=2 185is_read_only=false 186max_miss_count=0 187mshrs=4 188p_state_clk_gate_bins=20 189p_state_clk_gate_max=1000000000000 190p_state_clk_gate_min=1000 191power_model=Null 192prefetch_on_access=false 193prefetcher=Null 194response_latency=2 195sequential_access=false 196size=262144 197system=system 198tags=system.cpu.dcache.tags 199tgts_per_mshr=20 200write_buffers=8 201writeback_clean=false 202cpu_side=system.cpu.dcache_port 203mem_side=system.cpu.toL2Bus.slave[1] 204 205[system.cpu.dcache.tags] 206type=LRU 207assoc=2 208block_size=64 209clk_domain=system.cpu_clk_domain 210default_p_state=UNDEFINED 211eventq_index=0 212hit_latency=2 213p_state_clk_gate_bins=20 214p_state_clk_gate_max=1000000000000 215p_state_clk_gate_min=1000 216power_model=Null 217sequential_access=false 218size=262144 219 220[system.cpu.dtb] 221type=PowerTLB 222eventq_index=0 223size=64 224 225[system.cpu.fuPool] 226type=FUPool 227children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 228FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 229eventq_index=0 230 231[system.cpu.fuPool.FUList0] 232type=FUDesc 233children=opList 234count=6 235eventq_index=0 236opList=system.cpu.fuPool.FUList0.opList 237 238[system.cpu.fuPool.FUList0.opList] 239type=OpDesc 240eventq_index=0 241opClass=IntAlu 242opLat=1 243pipelined=true 244 245[system.cpu.fuPool.FUList1] 246type=FUDesc 247children=opList0 opList1 248count=2 249eventq_index=0 250opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 251 252[system.cpu.fuPool.FUList1.opList0] 253type=OpDesc 254eventq_index=0 255opClass=IntMult 256opLat=3 257pipelined=true 258 259[system.cpu.fuPool.FUList1.opList1] 260type=OpDesc 261eventq_index=0 262opClass=IntDiv 263opLat=20 264pipelined=false 265 266[system.cpu.fuPool.FUList2] 267type=FUDesc 268children=opList0 opList1 opList2 269count=4 270eventq_index=0 271opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 272 273[system.cpu.fuPool.FUList2.opList0] 274type=OpDesc 275eventq_index=0 276opClass=FloatAdd 277opLat=2 278pipelined=true 279 280[system.cpu.fuPool.FUList2.opList1] 281type=OpDesc 282eventq_index=0 283opClass=FloatCmp 284opLat=2 285pipelined=true 286 287[system.cpu.fuPool.FUList2.opList2] 288type=OpDesc 289eventq_index=0 290opClass=FloatCvt 291opLat=2 292pipelined=true 293 294[system.cpu.fuPool.FUList3] 295type=FUDesc 296children=opList0 opList1 opList2 297count=2 298eventq_index=0 299opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 300 301[system.cpu.fuPool.FUList3.opList0] 302type=OpDesc 303eventq_index=0 304opClass=FloatMult 305opLat=4 306pipelined=true 307 308[system.cpu.fuPool.FUList3.opList1] 309type=OpDesc 310eventq_index=0 311opClass=FloatDiv 312opLat=12 313pipelined=false 314 315[system.cpu.fuPool.FUList3.opList2] 316type=OpDesc 317eventq_index=0 318opClass=FloatSqrt 319opLat=24 320pipelined=false 321 322[system.cpu.fuPool.FUList4] 323type=FUDesc 324children=opList 325count=0 326eventq_index=0 327opList=system.cpu.fuPool.FUList4.opList 328 329[system.cpu.fuPool.FUList4.opList] 330type=OpDesc 331eventq_index=0 332opClass=MemRead 333opLat=1 334pipelined=true 335 336[system.cpu.fuPool.FUList5] 337type=FUDesc 338children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 339count=4 340eventq_index=0 341opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 342 343[system.cpu.fuPool.FUList5.opList00] 344type=OpDesc 345eventq_index=0 346opClass=SimdAdd 347opLat=1 348pipelined=true 349 350[system.cpu.fuPool.FUList5.opList01] 351type=OpDesc 352eventq_index=0 353opClass=SimdAddAcc 354opLat=1 355pipelined=true 356 357[system.cpu.fuPool.FUList5.opList02] 358type=OpDesc 359eventq_index=0 360opClass=SimdAlu 361opLat=1 362pipelined=true 363 364[system.cpu.fuPool.FUList5.opList03] 365type=OpDesc 366eventq_index=0 367opClass=SimdCmp 368opLat=1 369pipelined=true 370 371[system.cpu.fuPool.FUList5.opList04] 372type=OpDesc 373eventq_index=0 374opClass=SimdCvt 375opLat=1 376pipelined=true 377 378[system.cpu.fuPool.FUList5.opList05] 379type=OpDesc 380eventq_index=0 381opClass=SimdMisc 382opLat=1 383pipelined=true 384 385[system.cpu.fuPool.FUList5.opList06] 386type=OpDesc 387eventq_index=0 388opClass=SimdMult 389opLat=1 390pipelined=true 391 392[system.cpu.fuPool.FUList5.opList07] 393type=OpDesc 394eventq_index=0 395opClass=SimdMultAcc 396opLat=1 397pipelined=true 398 399[system.cpu.fuPool.FUList5.opList08] 400type=OpDesc 401eventq_index=0 402opClass=SimdShift 403opLat=1 404pipelined=true 405 406[system.cpu.fuPool.FUList5.opList09] 407type=OpDesc 408eventq_index=0 409opClass=SimdShiftAcc 410opLat=1 411pipelined=true 412 413[system.cpu.fuPool.FUList5.opList10] 414type=OpDesc 415eventq_index=0 416opClass=SimdSqrt 417opLat=1 418pipelined=true 419 420[system.cpu.fuPool.FUList5.opList11] 421type=OpDesc 422eventq_index=0 423opClass=SimdFloatAdd 424opLat=1 425pipelined=true 426 427[system.cpu.fuPool.FUList5.opList12] 428type=OpDesc 429eventq_index=0 430opClass=SimdFloatAlu 431opLat=1 432pipelined=true 433 434[system.cpu.fuPool.FUList5.opList13] 435type=OpDesc 436eventq_index=0 437opClass=SimdFloatCmp 438opLat=1 439pipelined=true 440 441[system.cpu.fuPool.FUList5.opList14] 442type=OpDesc 443eventq_index=0 444opClass=SimdFloatCvt 445opLat=1 446pipelined=true 447 448[system.cpu.fuPool.FUList5.opList15] 449type=OpDesc 450eventq_index=0 451opClass=SimdFloatDiv 452opLat=1 453pipelined=true 454 455[system.cpu.fuPool.FUList5.opList16] 456type=OpDesc 457eventq_index=0 458opClass=SimdFloatMisc 459opLat=1 460pipelined=true 461 462[system.cpu.fuPool.FUList5.opList17] 463type=OpDesc 464eventq_index=0 465opClass=SimdFloatMult 466opLat=1 467pipelined=true 468 469[system.cpu.fuPool.FUList5.opList18] 470type=OpDesc 471eventq_index=0 472opClass=SimdFloatMultAcc 473opLat=1 474pipelined=true 475 476[system.cpu.fuPool.FUList5.opList19] 477type=OpDesc 478eventq_index=0 479opClass=SimdFloatSqrt 480opLat=1 481pipelined=true 482 483[system.cpu.fuPool.FUList6] 484type=FUDesc 485children=opList 486count=0 487eventq_index=0 488opList=system.cpu.fuPool.FUList6.opList 489 490[system.cpu.fuPool.FUList6.opList] 491type=OpDesc 492eventq_index=0 493opClass=MemWrite 494opLat=1 495pipelined=true 496 497[system.cpu.fuPool.FUList7] 498type=FUDesc 499children=opList0 opList1 500count=4 501eventq_index=0 502opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 503 504[system.cpu.fuPool.FUList7.opList0] 505type=OpDesc 506eventq_index=0 507opClass=MemRead 508opLat=1 509pipelined=true 510 511[system.cpu.fuPool.FUList7.opList1] 512type=OpDesc 513eventq_index=0 514opClass=MemWrite 515opLat=1 516pipelined=true 517 518[system.cpu.fuPool.FUList8] 519type=FUDesc 520children=opList 521count=1 522eventq_index=0 523opList=system.cpu.fuPool.FUList8.opList 524 525[system.cpu.fuPool.FUList8.opList] 526type=OpDesc 527eventq_index=0 528opClass=IprAccess 529opLat=3 530pipelined=false 531 532[system.cpu.icache] 533type=Cache 534children=tags 535addr_ranges=0:18446744073709551615:0:0:0:0 536assoc=2 537clk_domain=system.cpu_clk_domain 538clusivity=mostly_incl 539default_p_state=UNDEFINED 540demand_mshr_reserve=1 541eventq_index=0 542hit_latency=2 543is_read_only=true 544max_miss_count=0 545mshrs=4 546p_state_clk_gate_bins=20 547p_state_clk_gate_max=1000000000000 548p_state_clk_gate_min=1000 549power_model=Null 550prefetch_on_access=false 551prefetcher=Null 552response_latency=2 553sequential_access=false 554size=131072 555system=system 556tags=system.cpu.icache.tags 557tgts_per_mshr=20 558write_buffers=8 559writeback_clean=true 560cpu_side=system.cpu.icache_port 561mem_side=system.cpu.toL2Bus.slave[0] 562 563[system.cpu.icache.tags] 564type=LRU 565assoc=2 566block_size=64 567clk_domain=system.cpu_clk_domain 568default_p_state=UNDEFINED 569eventq_index=0 570hit_latency=2 571p_state_clk_gate_bins=20 572p_state_clk_gate_max=1000000000000 573p_state_clk_gate_min=1000 574power_model=Null 575sequential_access=false 576size=131072 577 578[system.cpu.interrupts] 579type=PowerInterrupts 580eventq_index=0 581 582[system.cpu.isa] 583type=PowerISA 584eventq_index=0 585 586[system.cpu.itb] 587type=PowerTLB 588eventq_index=0 589size=64 590 591[system.cpu.l2cache] 592type=Cache 593children=tags 594addr_ranges=0:18446744073709551615:0:0:0:0 595assoc=8 596clk_domain=system.cpu_clk_domain 597clusivity=mostly_incl 598default_p_state=UNDEFINED 599demand_mshr_reserve=1 600eventq_index=0 601hit_latency=20 602is_read_only=false 603max_miss_count=0 604mshrs=20 605p_state_clk_gate_bins=20 606p_state_clk_gate_max=1000000000000 607p_state_clk_gate_min=1000 608power_model=Null 609prefetch_on_access=false 610prefetcher=Null 611response_latency=20 612sequential_access=false 613size=2097152 614system=system 615tags=system.cpu.l2cache.tags 616tgts_per_mshr=12 617write_buffers=8 618writeback_clean=false 619cpu_side=system.cpu.toL2Bus.master[0] 620mem_side=system.membus.slave[1] 621 622[system.cpu.l2cache.tags] 623type=LRU 624assoc=8 625block_size=64 626clk_domain=system.cpu_clk_domain 627default_p_state=UNDEFINED 628eventq_index=0 629hit_latency=20 630p_state_clk_gate_bins=20 631p_state_clk_gate_max=1000000000000 632p_state_clk_gate_min=1000 633power_model=Null 634sequential_access=false 635size=2097152 636 637[system.cpu.toL2Bus] 638type=CoherentXBar 639children=snoop_filter 640clk_domain=system.cpu_clk_domain 641default_p_state=UNDEFINED 642eventq_index=0 643forward_latency=0 644frontend_latency=1 645p_state_clk_gate_bins=20 646p_state_clk_gate_max=1000000000000 647p_state_clk_gate_min=1000 648point_of_coherency=false 649power_model=Null 650response_latency=1 651snoop_filter=system.cpu.toL2Bus.snoop_filter 652snoop_response_latency=1 653system=system 654use_default_range=false 655width=32 656master=system.cpu.l2cache.cpu_side 657slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 658 659[system.cpu.toL2Bus.snoop_filter] 660type=SnoopFilter 661eventq_index=0 662lookup_latency=0 663max_capacity=8388608 664system=system 665 666[system.cpu.tracer] 667type=ExeTracer 668eventq_index=0 669 670[system.cpu.workload] 671type=LiveProcess 672cmd=hello 673cwd= 674drivers= 675egid=100 676env= 677errout=cerr 678euid=100 679eventq_index=0 680executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/power/linux/hello 681gid=100 682input=cin 683kvmInSE=false 684max_stack_size=67108864 685output=cout 686pid=100 687ppid=99 688simpoint=0 689system=system 690uid=100 691useArchPT=false 692 693[system.cpu_clk_domain] 694type=SrcClockDomain 695clock=500 696domain_id=-1 697eventq_index=0 698init_perf_level=0 699voltage_domain=system.voltage_domain 700 701[system.dvfs_handler] 702type=DVFSHandler 703domains= 704enable=false 705eventq_index=0 706sys_clk_domain=system.clk_domain 707transition_latency=100000000 708 709[system.membus] 710type=CoherentXBar 711children=snoop_filter 712clk_domain=system.clk_domain 713default_p_state=UNDEFINED 714eventq_index=0 715forward_latency=4 716frontend_latency=3 717p_state_clk_gate_bins=20 718p_state_clk_gate_max=1000000000000 719p_state_clk_gate_min=1000 720point_of_coherency=true 721power_model=Null 722response_latency=2 723snoop_filter=system.membus.snoop_filter 724snoop_response_latency=4 725system=system 726use_default_range=false 727width=16 728master=system.physmem.port 729slave=system.system_port system.cpu.l2cache.mem_side 730 731[system.membus.snoop_filter] 732type=SnoopFilter 733eventq_index=0 734lookup_latency=1 735max_capacity=8388608 736system=system 737 738[system.physmem] 739type=DRAMCtrl 740IDD0=0.055000 741IDD02=0.000000 742IDD2N=0.032000 743IDD2N2=0.000000 744IDD2P0=0.000000 745IDD2P02=0.000000 746IDD2P1=0.032000 747IDD2P12=0.000000 748IDD3N=0.038000 749IDD3N2=0.000000 750IDD3P0=0.000000 751IDD3P02=0.000000 752IDD3P1=0.038000 753IDD3P12=0.000000 754IDD4R=0.157000 755IDD4R2=0.000000 756IDD4W=0.125000 757IDD4W2=0.000000 758IDD5=0.235000 759IDD52=0.000000 760IDD6=0.020000 761IDD62=0.000000 762VDD=1.500000 763VDD2=0.000000 764activation_limit=4 765addr_mapping=RoRaBaCoCh 766bank_groups_per_rank=0 767banks_per_rank=8 768burst_length=8 769channels=1 770clk_domain=system.clk_domain 771conf_table_reported=true 772default_p_state=UNDEFINED 773device_bus_width=8 774device_rowbuffer_size=1024 775device_size=536870912 776devices_per_rank=8 777dll=true 778eventq_index=0 779in_addr_map=true 780kvm_map=true 781max_accesses_per_row=16 782mem_sched_policy=frfcfs 783min_writes_per_switch=16 784null=false 785p_state_clk_gate_bins=20 786p_state_clk_gate_max=1000000000000 787p_state_clk_gate_min=1000 788page_policy=open_adaptive 789power_model=Null 790range=0:134217727:0:0:0:0 791ranks_per_channel=2 792read_buffer_size=32 793static_backend_latency=10000 794static_frontend_latency=10000 795tBURST=5000 796tCCD_L=0 797tCK=1250 798tCL=13750 799tCS=2500 800tRAS=35000 801tRCD=13750 802tREFI=7800000 803tRFC=260000 804tRP=13750 805tRRD=6000 806tRRD_L=0 807tRTP=7500 808tRTW=2500 809tWR=15000 810tWTR=7500 811tXAW=30000 812tXP=6000 813tXPDLL=0 814tXS=270000 815tXSDLL=0 816write_buffer_size=64 817write_high_thresh_perc=85 818write_low_thresh_perc=50 819port=system.membus.master[0] 820 821[system.voltage_domain] 822type=VoltageDomain 823eventq_index=0 824voltage=1.000000 825 826