stats.txt revision 8835
13021SN/A 23021SN/A---------- Begin Simulation Statistics ---------- 37670SN/Asim_seconds 0.000032 # Number of seconds simulated 47670SN/Asim_ticks 32088000 # Number of ticks simulated 58721SN/Afinal_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68540SN/Asim_freq 1000000000000 # Frequency of simulated ticks 78835SAli.Saidi@ARM.comhost_inst_rate 603210 # Simulator instruction rate (inst/s) 88835SAli.Saidi@ARM.comhost_op_rate 602100 # Simulator op (including micro ops) rate (op/s) 98835SAli.Saidi@ARM.comhost_tick_rate 3309896144 # Simulator tick rate (ticks/s) 108835SAli.Saidi@ARM.comhost_mem_usage 209992 # Number of bytes of host memory used 118835SAli.Saidi@ARM.comhost_seconds 0.01 # Real time elapsed on the host 128540SN/Asim_insts 5827 # Number of instructions simulated 138835SAli.Saidi@ARM.comsim_ops 5827 # Number of ops (including micro ops) simulated 148721SN/Asystem.physmem.bytes_read 28096 # Number of bytes read from this memory 158721SN/Asystem.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory 168721SN/Asystem.physmem.bytes_written 0 # Number of bytes written to this memory 178721SN/Asystem.physmem.num_reads 439 # Number of read requests responded to by this memory 188721SN/Asystem.physmem.num_writes 0 # Number of write requests responded to by this memory 198721SN/Asystem.physmem.num_other 0 # Number of other requests responded to by this memory 208721SN/Asystem.physmem.bw_read 875592122 # Total read bandwidth from this memory (bytes/s) 218721SN/Asystem.physmem.bw_inst_read 600349040 # Instruction read bandwidth from this memory (bytes/s) 228721SN/Asystem.physmem.bw_total 875592122 # Total bandwidth to/from this memory (bytes/s) 238540SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 248540SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 258540SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 268540SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 278540SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 288540SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 298540SN/Asystem.cpu.dtb.hits 0 # DTB hits 308540SN/Asystem.cpu.dtb.misses 0 # DTB misses 318540SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 328540SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 338540SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 348540SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 358540SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 368540SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 378540SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 388540SN/Asystem.cpu.itb.hits 0 # DTB hits 398540SN/Asystem.cpu.itb.misses 0 # DTB misses 408540SN/Asystem.cpu.itb.accesses 0 # DTB accesses 418540SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 428540SN/Asystem.cpu.numCycles 64176 # number of cpu cycles simulated 438540SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 448540SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 458835SAli.Saidi@ARM.comsystem.cpu.committedInsts 5827 # Number of instructions committed 468835SAli.Saidi@ARM.comsystem.cpu.committedOps 5827 # Number of ops (including micro ops) committed 478540SN/Asystem.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses 488540SN/Asystem.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 498540SN/Asystem.cpu.num_func_calls 194 # number of times a function call or return occured 508540SN/Asystem.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls 518540SN/Asystem.cpu.num_int_insts 5126 # number of integer instructions 528540SN/Asystem.cpu.num_fp_insts 2 # number of float instructions 538554SN/Asystem.cpu.num_int_register_reads 7300 # number of times the integer registers were read 548540SN/Asystem.cpu.num_int_register_writes 3409 # number of times the integer registers were written 558540SN/Asystem.cpu.num_fp_register_reads 3 # number of times the floating registers were read 568540SN/Asystem.cpu.num_fp_register_writes 1 # number of times the floating registers were written 578540SN/Asystem.cpu.num_mem_refs 2090 # number of memory refs 588540SN/Asystem.cpu.num_load_insts 1164 # Number of load instructions 598540SN/Asystem.cpu.num_store_insts 926 # Number of store instructions 608540SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 618540SN/Asystem.cpu.num_busy_cycles 64176 # Number of busy cycles 628540SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 638540SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 648540SN/Asystem.cpu.icache.replacements 13 # number of replacements 658540SN/Asystem.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use 668540SN/Asystem.cpu.icache.total_refs 5526 # Total number of references to valid blocks. 678540SN/Asystem.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. 688540SN/Asystem.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks. 698540SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 708835SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 132.493866 # Average occupied blocks per requestor 718835SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.064694 # Average percentage of cache occupancy 728835SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.064694 # Average percentage of cache occupancy 738835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 5526 # number of ReadReq hits 748835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 5526 # number of ReadReq hits 758835SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 5526 # number of demand (read+write) hits 768835SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 5526 # number of demand (read+write) hits 778835SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 5526 # number of overall hits 788835SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 5526 # number of overall hits 798835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses 808835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses 818835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 303 # number of demand (read+write) misses 828835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses 838835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses 848835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 303 # number of overall misses 858835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 16884000 # number of ReadReq miss cycles 868835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 16884000 # number of ReadReq miss cycles 878835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 16884000 # number of demand (read+write) miss cycles 888835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 16884000 # number of demand (read+write) miss cycles 898835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 16884000 # number of overall miss cycles 908835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 16884000 # number of overall miss cycles 918835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 5829 # number of ReadReq accesses(hits+misses) 928835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 5829 # number of ReadReq accesses(hits+misses) 938835SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 5829 # number of demand (read+write) accesses 948835SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 5829 # number of demand (read+write) accesses 958835SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 5829 # number of overall (read+write) accesses 968835SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 5829 # number of overall (read+write) accesses 978835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.051981 # miss rate for ReadReq accesses 988835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.051981 # miss rate for demand accesses 998835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses 1008835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency 1018835SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency 1028835SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency 1038540SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1048540SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1058540SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1068540SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1078540SN/Asystem.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1088540SN/Asystem.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1098540SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 1108540SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 1118835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses 1128835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 303 # number of ReadReq MSHR misses 1138835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses 1148835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 303 # number of demand (read+write) MSHR misses 1158835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses 1168835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses 1178835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15975000 # number of ReadReq MSHR miss cycles 1188835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 15975000 # number of ReadReq MSHR miss cycles 1198835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 15975000 # number of demand (read+write) MSHR miss cycles 1208835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 15975000 # number of demand (read+write) MSHR miss cycles 1218835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles 1228835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles 1238835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for ReadReq accesses 1248835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for demand accesses 1258835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for overall accesses 1268835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency 1278835SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 1288835SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 1298540SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1308540SN/Asystem.cpu.dcache.replacements 0 # number of replacements 1318540SN/Asystem.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use 1328540SN/Asystem.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. 1338540SN/Asystem.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. 1348540SN/Asystem.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. 1358540SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1368835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 87.458397 # Average occupied blocks per requestor 1378835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.021352 # Average percentage of cache occupancy 1388835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.021352 # Average percentage of cache occupancy 1398835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1077 # number of ReadReq hits 1408835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 1077 # number of ReadReq hits 1418835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits 1428835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits 1438835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 1951 # number of demand (read+write) hits 1448835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 1951 # number of demand (read+write) hits 1458835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 1951 # number of overall hits 1468835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 1951 # number of overall hits 1478835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 1488835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses 1498835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses 1508835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses 1518835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 1528835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 1538835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 1548835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 138 # number of overall misses 1558835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 4872000 # number of ReadReq miss cycles 1568835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 4872000 # number of ReadReq miss cycles 1578835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 2856000 # number of WriteReq miss cycles 1588835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 2856000 # number of WriteReq miss cycles 1598835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles 1608835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles 1618835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles 1628835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles 1638835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) 1648835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) 1658835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 1668835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 1678835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 2089 # number of demand (read+write) accesses 1688835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses 1698835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses 1708835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses 1718835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074742 # miss rate for ReadReq accesses 1728835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses 1738835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.066060 # miss rate for demand accesses 1748835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.066060 # miss rate for overall accesses 1758835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency 1768835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 1778835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency 1788835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency 1798540SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1808540SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1818540SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1828540SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1836127SN/Asystem.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1846127SN/Asystem.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1858540SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 1863041SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 1878835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 1888835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 1898835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 1908835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 1918835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 1928835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 1938835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 1948835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses 1958835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles 1968835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles 1978835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles 1988835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles 1998835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles 2008835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles 2018835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles 2028835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles 2038835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses 2048835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 2058835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses 2068835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses 2078835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 2088835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 2098835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 2108835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 2118540SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2128540SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 2138540SN/Asystem.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use 2148540SN/Asystem.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 2158540SN/Asystem.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. 2168540SN/Asystem.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. 2178540SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2188835SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 133.837577 # Average occupied blocks per requestor 2198835SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 54.207742 # Average occupied blocks per requestor 2208835SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004084 # Average percentage of cache occupancy 2218835SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001654 # Average percentage of cache occupancy 2228835SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::total 0.005739 # Average percentage of cache occupancy 2238835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 2248835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 2258835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 2268835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 2278835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 2288835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 2 # number of overall hits 2298835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses 2308835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 2318835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 388 # number of ReadReq misses 2328835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 2338835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 2348835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses 2358835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses 2368835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 439 # number of demand (read+write) misses 2378835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses 2388835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses 2398835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 439 # number of overall misses 2408835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15652000 # number of ReadReq miss cycles 2418835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles 2428835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 20176000 # number of ReadReq miss cycles 2438835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2652000 # number of ReadExReq miss cycles 2448835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2652000 # number of ReadExReq miss cycles 2458835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 15652000 # number of demand (read+write) miss cycles 2468835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles 2478835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 22828000 # number of demand (read+write) miss cycles 2488835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 15652000 # number of overall miss cycles 2498835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles 2508835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 22828000 # number of overall miss cycles 2518835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 303 # number of ReadReq accesses(hits+misses) 2528835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) 2538835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 390 # number of ReadReq accesses(hits+misses) 2548835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 2558835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 2568835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 303 # number of demand (read+write) accesses 2578835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 2588835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 2598835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 303 # number of overall (read+write) accesses 2608835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses 2618835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 2628835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses 2638835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 2648835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 2658835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses 2668835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 2678835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses 2688835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 2698835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 2708835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 2718835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 2728835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 2738835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 2748835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 2758835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 2768540SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2778540SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2788540SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2798540SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2806127SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 2816127SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 2828540SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 2833041SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 2848835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses 2858835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 2868835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 388 # number of ReadReq MSHR misses 2878835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 2888835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 2898835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses 2908835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 2918835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses 2928835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses 2938835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 2948835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 439 # number of overall MSHR misses 2958835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12040000 # number of ReadReq MSHR miss cycles 2968835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles 2978835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 15520000 # number of ReadReq MSHR miss cycles 2988835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2040000 # number of ReadExReq MSHR miss cycles 2998835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2040000 # number of ReadExReq MSHR miss cycles 3008835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12040000 # number of demand (read+write) MSHR miss cycles 3018835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles 3028835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 17560000 # number of demand (read+write) MSHR miss cycles 3038835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12040000 # number of overall MSHR miss cycles 3048835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles 3058835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles 3068835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses 3078835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 3088835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 3098835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses 3108835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 3118835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses 3128835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 3138835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 3148835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 3158835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 3168835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 3178835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 3188835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 3198835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 3208540SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 3213021SN/A 3223021SN/A---------- End Simulation Statistics ---------- 323