stats.txt revision 8835
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000032 # Number of seconds simulated 4sim_ticks 32088000 # Number of ticks simulated 5final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 603210 # Simulator instruction rate (inst/s) 8host_op_rate 602100 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3309896144 # Simulator tick rate (ticks/s) 10host_mem_usage 209992 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 5827 # Number of instructions simulated 13sim_ops 5827 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 28096 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 439 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 875592122 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 600349040 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 875592122 # Total bandwidth to/from this memory (bytes/s) 23system.cpu.dtb.read_hits 0 # DTB read hits 24system.cpu.dtb.read_misses 0 # DTB read misses 25system.cpu.dtb.read_accesses 0 # DTB read accesses 26system.cpu.dtb.write_hits 0 # DTB write hits 27system.cpu.dtb.write_misses 0 # DTB write misses 28system.cpu.dtb.write_accesses 0 # DTB write accesses 29system.cpu.dtb.hits 0 # DTB hits 30system.cpu.dtb.misses 0 # DTB misses 31system.cpu.dtb.accesses 0 # DTB accesses 32system.cpu.itb.read_hits 0 # DTB read hits 33system.cpu.itb.read_misses 0 # DTB read misses 34system.cpu.itb.read_accesses 0 # DTB read accesses 35system.cpu.itb.write_hits 0 # DTB write hits 36system.cpu.itb.write_misses 0 # DTB write misses 37system.cpu.itb.write_accesses 0 # DTB write accesses 38system.cpu.itb.hits 0 # DTB hits 39system.cpu.itb.misses 0 # DTB misses 40system.cpu.itb.accesses 0 # DTB accesses 41system.cpu.workload.num_syscalls 8 # Number of system calls 42system.cpu.numCycles 64176 # number of cpu cycles simulated 43system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 44system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 45system.cpu.committedInsts 5827 # Number of instructions committed 46system.cpu.committedOps 5827 # Number of ops (including micro ops) committed 47system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses 48system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 49system.cpu.num_func_calls 194 # number of times a function call or return occured 50system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls 51system.cpu.num_int_insts 5126 # number of integer instructions 52system.cpu.num_fp_insts 2 # number of float instructions 53system.cpu.num_int_register_reads 7300 # number of times the integer registers were read 54system.cpu.num_int_register_writes 3409 # number of times the integer registers were written 55system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 56system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 57system.cpu.num_mem_refs 2090 # number of memory refs 58system.cpu.num_load_insts 1164 # Number of load instructions 59system.cpu.num_store_insts 926 # Number of store instructions 60system.cpu.num_idle_cycles 0 # Number of idle cycles 61system.cpu.num_busy_cycles 64176 # Number of busy cycles 62system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 63system.cpu.idle_fraction 0 # Percentage of idle cycles 64system.cpu.icache.replacements 13 # number of replacements 65system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use 66system.cpu.icache.total_refs 5526 # Total number of references to valid blocks. 67system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. 68system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks. 69system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 70system.cpu.icache.occ_blocks::cpu.inst 132.493866 # Average occupied blocks per requestor 71system.cpu.icache.occ_percent::cpu.inst 0.064694 # Average percentage of cache occupancy 72system.cpu.icache.occ_percent::total 0.064694 # Average percentage of cache occupancy 73system.cpu.icache.ReadReq_hits::cpu.inst 5526 # number of ReadReq hits 74system.cpu.icache.ReadReq_hits::total 5526 # number of ReadReq hits 75system.cpu.icache.demand_hits::cpu.inst 5526 # number of demand (read+write) hits 76system.cpu.icache.demand_hits::total 5526 # number of demand (read+write) hits 77system.cpu.icache.overall_hits::cpu.inst 5526 # number of overall hits 78system.cpu.icache.overall_hits::total 5526 # number of overall hits 79system.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses 80system.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses 81system.cpu.icache.demand_misses::cpu.inst 303 # number of demand (read+write) misses 82system.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses 83system.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses 84system.cpu.icache.overall_misses::total 303 # number of overall misses 85system.cpu.icache.ReadReq_miss_latency::cpu.inst 16884000 # number of ReadReq miss cycles 86system.cpu.icache.ReadReq_miss_latency::total 16884000 # number of ReadReq miss cycles 87system.cpu.icache.demand_miss_latency::cpu.inst 16884000 # number of demand (read+write) miss cycles 88system.cpu.icache.demand_miss_latency::total 16884000 # number of demand (read+write) miss cycles 89system.cpu.icache.overall_miss_latency::cpu.inst 16884000 # number of overall miss cycles 90system.cpu.icache.overall_miss_latency::total 16884000 # number of overall miss cycles 91system.cpu.icache.ReadReq_accesses::cpu.inst 5829 # number of ReadReq accesses(hits+misses) 92system.cpu.icache.ReadReq_accesses::total 5829 # number of ReadReq accesses(hits+misses) 93system.cpu.icache.demand_accesses::cpu.inst 5829 # number of demand (read+write) accesses 94system.cpu.icache.demand_accesses::total 5829 # number of demand (read+write) accesses 95system.cpu.icache.overall_accesses::cpu.inst 5829 # number of overall (read+write) accesses 96system.cpu.icache.overall_accesses::total 5829 # number of overall (read+write) accesses 97system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.051981 # miss rate for ReadReq accesses 98system.cpu.icache.demand_miss_rate::cpu.inst 0.051981 # miss rate for demand accesses 99system.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses 100system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency 101system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency 102system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency 103system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 104system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 105system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 106system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 107system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 108system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 109system.cpu.icache.fast_writes 0 # number of fast writes performed 110system.cpu.icache.cache_copies 0 # number of cache copies performed 111system.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses 112system.cpu.icache.ReadReq_mshr_misses::total 303 # number of ReadReq MSHR misses 113system.cpu.icache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses 114system.cpu.icache.demand_mshr_misses::total 303 # number of demand (read+write) MSHR misses 115system.cpu.icache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses 116system.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses 117system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15975000 # number of ReadReq MSHR miss cycles 118system.cpu.icache.ReadReq_mshr_miss_latency::total 15975000 # number of ReadReq MSHR miss cycles 119system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15975000 # number of demand (read+write) MSHR miss cycles 120system.cpu.icache.demand_mshr_miss_latency::total 15975000 # number of demand (read+write) MSHR miss cycles 121system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles 122system.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles 123system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for ReadReq accesses 124system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for demand accesses 125system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for overall accesses 126system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency 127system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 128system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 129system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 130system.cpu.dcache.replacements 0 # number of replacements 131system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use 132system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. 133system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. 134system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. 135system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 136system.cpu.dcache.occ_blocks::cpu.data 87.458397 # Average occupied blocks per requestor 137system.cpu.dcache.occ_percent::cpu.data 0.021352 # Average percentage of cache occupancy 138system.cpu.dcache.occ_percent::total 0.021352 # Average percentage of cache occupancy 139system.cpu.dcache.ReadReq_hits::cpu.data 1077 # number of ReadReq hits 140system.cpu.dcache.ReadReq_hits::total 1077 # number of ReadReq hits 141system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits 142system.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits 143system.cpu.dcache.demand_hits::cpu.data 1951 # number of demand (read+write) hits 144system.cpu.dcache.demand_hits::total 1951 # number of demand (read+write) hits 145system.cpu.dcache.overall_hits::cpu.data 1951 # number of overall hits 146system.cpu.dcache.overall_hits::total 1951 # number of overall hits 147system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 148system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses 149system.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses 150system.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses 151system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 152system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 153system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 154system.cpu.dcache.overall_misses::total 138 # number of overall misses 155system.cpu.dcache.ReadReq_miss_latency::cpu.data 4872000 # number of ReadReq miss cycles 156system.cpu.dcache.ReadReq_miss_latency::total 4872000 # number of ReadReq miss cycles 157system.cpu.dcache.WriteReq_miss_latency::cpu.data 2856000 # number of WriteReq miss cycles 158system.cpu.dcache.WriteReq_miss_latency::total 2856000 # number of WriteReq miss cycles 159system.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles 160system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles 161system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles 162system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles 163system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) 164system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) 165system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 166system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 167system.cpu.dcache.demand_accesses::cpu.data 2089 # number of demand (read+write) accesses 168system.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses 169system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses 170system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses 171system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074742 # miss rate for ReadReq accesses 172system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses 173system.cpu.dcache.demand_miss_rate::cpu.data 0.066060 # miss rate for demand accesses 174system.cpu.dcache.overall_miss_rate::cpu.data 0.066060 # miss rate for overall accesses 175system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency 176system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 177system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency 178system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency 179system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 180system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 181system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 182system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 183system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 184system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 185system.cpu.dcache.fast_writes 0 # number of fast writes performed 186system.cpu.dcache.cache_copies 0 # number of cache copies performed 187system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 188system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 189system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 190system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 191system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 192system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 193system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 194system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses 195system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles 196system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles 197system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles 198system.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles 199system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles 200system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles 201system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles 202system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles 203system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses 204system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 205system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses 206system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses 207system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 208system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 209system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 210system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 211system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 212system.cpu.l2cache.replacements 0 # number of replacements 213system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use 214system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 215system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. 216system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. 217system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 218system.cpu.l2cache.occ_blocks::cpu.inst 133.837577 # Average occupied blocks per requestor 219system.cpu.l2cache.occ_blocks::cpu.data 54.207742 # Average occupied blocks per requestor 220system.cpu.l2cache.occ_percent::cpu.inst 0.004084 # Average percentage of cache occupancy 221system.cpu.l2cache.occ_percent::cpu.data 0.001654 # Average percentage of cache occupancy 222system.cpu.l2cache.occ_percent::total 0.005739 # Average percentage of cache occupancy 223system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 224system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 225system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 226system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 227system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 228system.cpu.l2cache.overall_hits::total 2 # number of overall hits 229system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses 230system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 231system.cpu.l2cache.ReadReq_misses::total 388 # number of ReadReq misses 232system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 233system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 234system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses 235system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses 236system.cpu.l2cache.demand_misses::total 439 # number of demand (read+write) misses 237system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses 238system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses 239system.cpu.l2cache.overall_misses::total 439 # number of overall misses 240system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15652000 # number of ReadReq miss cycles 241system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles 242system.cpu.l2cache.ReadReq_miss_latency::total 20176000 # number of ReadReq miss cycles 243system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2652000 # number of ReadExReq miss cycles 244system.cpu.l2cache.ReadExReq_miss_latency::total 2652000 # number of ReadExReq miss cycles 245system.cpu.l2cache.demand_miss_latency::cpu.inst 15652000 # number of demand (read+write) miss cycles 246system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles 247system.cpu.l2cache.demand_miss_latency::total 22828000 # number of demand (read+write) miss cycles 248system.cpu.l2cache.overall_miss_latency::cpu.inst 15652000 # number of overall miss cycles 249system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles 250system.cpu.l2cache.overall_miss_latency::total 22828000 # number of overall miss cycles 251system.cpu.l2cache.ReadReq_accesses::cpu.inst 303 # number of ReadReq accesses(hits+misses) 252system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) 253system.cpu.l2cache.ReadReq_accesses::total 390 # number of ReadReq accesses(hits+misses) 254system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 255system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 256system.cpu.l2cache.demand_accesses::cpu.inst 303 # number of demand (read+write) accesses 257system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 258system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 259system.cpu.l2cache.overall_accesses::cpu.inst 303 # number of overall (read+write) accesses 260system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses 261system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 262system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses 263system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 264system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 265system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses 266system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 267system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses 268system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 269system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 270system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 271system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 272system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 273system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 274system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 275system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 276system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 277system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 278system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 279system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 280system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 281system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 282system.cpu.l2cache.fast_writes 0 # number of fast writes performed 283system.cpu.l2cache.cache_copies 0 # number of cache copies performed 284system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses 285system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 286system.cpu.l2cache.ReadReq_mshr_misses::total 388 # number of ReadReq MSHR misses 287system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 288system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 289system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses 290system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 291system.cpu.l2cache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses 292system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses 293system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 294system.cpu.l2cache.overall_mshr_misses::total 439 # number of overall MSHR misses 295system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12040000 # number of ReadReq MSHR miss cycles 296system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles 297system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15520000 # number of ReadReq MSHR miss cycles 298system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2040000 # number of ReadExReq MSHR miss cycles 299system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2040000 # number of ReadExReq MSHR miss cycles 300system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12040000 # number of demand (read+write) MSHR miss cycles 301system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles 302system.cpu.l2cache.demand_mshr_miss_latency::total 17560000 # number of demand (read+write) MSHR miss cycles 303system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12040000 # number of overall MSHR miss cycles 304system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles 305system.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles 306system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses 307system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 308system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 309system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses 310system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 311system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses 312system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 313system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 314system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 315system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 316system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 317system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 318system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 319system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 320system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 321 322---------- End Simulation Statistics ---------- 323