config.ini revision 7524
13691SN/A[root] 23691SN/Atype=Root 39449SAli.Saidi@ARM.comchildren=system 410409Sandreas.hansson@arm.comdummy=0 510409Sandreas.hansson@arm.com 68721SN/A[system] 711245Sandreas.sandberg@arm.comtype=System 811245Sandreas.sandberg@arm.comchildren=cpu membus physmem 911245Sandreas.sandberg@arm.commem_mode=atomic 1011245Sandreas.sandberg@arm.comphysmem=system.physmem 1111245Sandreas.sandberg@arm.com 1210409Sandreas.hansson@arm.com[system.cpu] 1310409Sandreas.hansson@arm.comtype=TimingSimpleCPU 1410778Snilay@cs.wisc.educhildren=dcache dtb icache itb l2cache toL2Bus tracer workload 1510778Snilay@cs.wisc.eduCP0_Config=0 1610778Snilay@cs.wisc.eduCP0_Config1=0 1710778Snilay@cs.wisc.eduCP0_Config1_C2=false 1810778Snilay@cs.wisc.eduCP0_Config1_CA=false 1910778Snilay@cs.wisc.eduCP0_Config1_DA=0 2010778Snilay@cs.wisc.eduCP0_Config1_DL=0 2110778Snilay@cs.wisc.eduCP0_Config1_DS=0 2210778Snilay@cs.wisc.eduCP0_Config1_EP=false 2310778Snilay@cs.wisc.eduCP0_Config1_FP=false 2410778Snilay@cs.wisc.eduCP0_Config1_IA=0 2510778Snilay@cs.wisc.eduCP0_Config1_IL=0 2610778Snilay@cs.wisc.eduCP0_Config1_IS=0 2710778Snilay@cs.wisc.eduCP0_Config1_M=0 2810778Snilay@cs.wisc.eduCP0_Config1_MD=false 2910778Snilay@cs.wisc.eduCP0_Config1_MMU=0 3010778Snilay@cs.wisc.eduCP0_Config1_PC=false 3110778Snilay@cs.wisc.eduCP0_Config1_WR=false 3210778Snilay@cs.wisc.eduCP0_Config2=0 3310778Snilay@cs.wisc.eduCP0_Config2_M=false 3410778Snilay@cs.wisc.eduCP0_Config2_SA=0 3510778Snilay@cs.wisc.eduCP0_Config2_SL=0 3610778Snilay@cs.wisc.eduCP0_Config2_SS=0 3710778Snilay@cs.wisc.eduCP0_Config2_SU=0 3810778Snilay@cs.wisc.eduCP0_Config2_TA=0 3910778Snilay@cs.wisc.eduCP0_Config2_TL=0 4010778Snilay@cs.wisc.eduCP0_Config2_TS=0 4110778Snilay@cs.wisc.eduCP0_Config2_TU=0 4210778Snilay@cs.wisc.eduCP0_Config3=0 4310778Snilay@cs.wisc.eduCP0_Config3_DSPP=false 4410778Snilay@cs.wisc.eduCP0_Config3_LPA=false 4510778Snilay@cs.wisc.eduCP0_Config3_M=false 4610778Snilay@cs.wisc.eduCP0_Config3_MT=false 4710778Snilay@cs.wisc.eduCP0_Config3_SM=false 4810778Snilay@cs.wisc.eduCP0_Config3_SP=false 4910778Snilay@cs.wisc.eduCP0_Config3_TL=false 5010778Snilay@cs.wisc.eduCP0_Config3_VEIC=false 5110778Snilay@cs.wisc.eduCP0_Config3_VInt=false 5210778Snilay@cs.wisc.eduCP0_Config_AR=0 5310778Snilay@cs.wisc.eduCP0_Config_AT=0 5410778Snilay@cs.wisc.eduCP0_Config_BE=0 5510778Snilay@cs.wisc.eduCP0_Config_MT=0 5610778Snilay@cs.wisc.eduCP0_Config_VI=0 5710778Snilay@cs.wisc.eduCP0_EBase_CPUNum=0 5810778Snilay@cs.wisc.eduCP0_IntCtl_IPPCI=0 5910778Snilay@cs.wisc.eduCP0_IntCtl_IPTI=0 6010778Snilay@cs.wisc.eduCP0_PRId=0 6110778Snilay@cs.wisc.eduCP0_PRId_CompanyID=0 6210778Snilay@cs.wisc.eduCP0_PRId_CompanyOptions=0 6310778Snilay@cs.wisc.eduCP0_PRId_ProcessorID=1 6410778Snilay@cs.wisc.eduCP0_PRId_Revision=0 6510778Snilay@cs.wisc.eduCP0_PerfCtr_M=false 6610778Snilay@cs.wisc.eduCP0_PerfCtr_W=false 6710778Snilay@cs.wisc.eduCP0_SrsCtl_HSS=0 6810778Snilay@cs.wisc.eduCP0_WatchHi_M=false 6910778Snilay@cs.wisc.educhecker=Null 7010778Snilay@cs.wisc.educlock=500 7110778Snilay@cs.wisc.educpu_id=0 7210778Snilay@cs.wisc.edudefer_registration=false 7310778Snilay@cs.wisc.edudo_checkpoint_insts=true 7410778Snilay@cs.wisc.edudo_statistics_insts=true 7510778Snilay@cs.wisc.edudtb=system.cpu.dtb 7610778Snilay@cs.wisc.edufunction_trace=false 7710778Snilay@cs.wisc.edufunction_trace_start=0 7810778Snilay@cs.wisc.eduitb=system.cpu.itb 7910778Snilay@cs.wisc.edumax_insts_all_threads=0 8010778Snilay@cs.wisc.edumax_insts_any_thread=0 8110778Snilay@cs.wisc.edumax_loads_all_threads=0 8210778Snilay@cs.wisc.edumax_loads_any_thread=0 8310778Snilay@cs.wisc.edunumThreads=1 8410778Snilay@cs.wisc.eduphase=0 8510778Snilay@cs.wisc.eduprogress_interval=0 8610778Snilay@cs.wisc.edusystem=system 8710778Snilay@cs.wisc.edutracer=system.cpu.tracer 8810778Snilay@cs.wisc.eduworkload=system.cpu.workload 8910778Snilay@cs.wisc.edudcache_port=system.cpu.dcache.cpu_side 9010778Snilay@cs.wisc.eduicache_port=system.cpu.icache.cpu_side 9110778Snilay@cs.wisc.edu 9210778Snilay@cs.wisc.edu[system.cpu.dcache] 9310778Snilay@cs.wisc.edutype=BaseCache 9410778Snilay@cs.wisc.eduaddr_range=0:18446744073709551615 9510778Snilay@cs.wisc.eduassoc=2 9610778Snilay@cs.wisc.edublock_size=64 9710778Snilay@cs.wisc.eduforward_snoops=true 9810778Snilay@cs.wisc.eduhash_delay=1 9910778Snilay@cs.wisc.edulatency=1000 10010778Snilay@cs.wisc.edumax_miss_count=0 10110778Snilay@cs.wisc.edumshrs=10 10210778Snilay@cs.wisc.edunum_cpus=1 10310778Snilay@cs.wisc.eduprefetch_data_accesses_only=false 10410778Snilay@cs.wisc.eduprefetch_degree=1 10510778Snilay@cs.wisc.eduprefetch_latency=10000 10610778Snilay@cs.wisc.eduprefetch_on_access=false 10710778Snilay@cs.wisc.eduprefetch_past_page=false 10810778Snilay@cs.wisc.eduprefetch_policy=none 10910778Snilay@cs.wisc.eduprefetch_serial_squash=false 11010778Snilay@cs.wisc.eduprefetch_use_cpu_id=true 11110778Snilay@cs.wisc.eduprefetcher_size=100 11210778Snilay@cs.wisc.eduprioritizeRequests=false 11310778Snilay@cs.wisc.edurepl=Null 11410778Snilay@cs.wisc.edusize=262144 11510778Snilay@cs.wisc.edusubblock_size=0 11610778Snilay@cs.wisc.edutgts_per_mshr=5 11710778Snilay@cs.wisc.edutrace_addr=0 11810778Snilay@cs.wisc.edutwo_queue=false 11910778Snilay@cs.wisc.eduwrite_buffers=8 12010778Snilay@cs.wisc.educpu_side=system.cpu.dcache_port 12110778Snilay@cs.wisc.edumem_side=system.cpu.toL2Bus.port[1] 12210778Snilay@cs.wisc.edu 12310778Snilay@cs.wisc.edu[system.cpu.dtb] 12410778Snilay@cs.wisc.edutype=MipsTLB 12510778Snilay@cs.wisc.edusize=64 12610778Snilay@cs.wisc.edu 12710778Snilay@cs.wisc.edu[system.cpu.icache] 12810778Snilay@cs.wisc.edutype=BaseCache 12910778Snilay@cs.wisc.eduaddr_range=0:18446744073709551615 13010778Snilay@cs.wisc.eduassoc=2 13110778Snilay@cs.wisc.edublock_size=64 13210778Snilay@cs.wisc.eduforward_snoops=true 13310778Snilay@cs.wisc.eduhash_delay=1 13410778Snilay@cs.wisc.edulatency=1000 13510778Snilay@cs.wisc.edumax_miss_count=0 13610778Snilay@cs.wisc.edumshrs=10 13710778Snilay@cs.wisc.edunum_cpus=1 13810778Snilay@cs.wisc.eduprefetch_data_accesses_only=false 13910778Snilay@cs.wisc.eduprefetch_degree=1 14011245Sandreas.sandberg@arm.comprefetch_latency=10000 14111245Sandreas.sandberg@arm.comprefetch_on_access=false 14211245Sandreas.sandberg@arm.comprefetch_past_page=false 14311245Sandreas.sandberg@arm.comprefetch_policy=none 14411245Sandreas.sandberg@arm.comprefetch_serial_squash=false 14511245Sandreas.sandberg@arm.comprefetch_use_cpu_id=true 14611245Sandreas.sandberg@arm.comprefetcher_size=100 14711245Sandreas.sandberg@arm.comprioritizeRequests=false 14811245Sandreas.sandberg@arm.comrepl=Null 14911245Sandreas.sandberg@arm.comsize=131072 15011245Sandreas.sandberg@arm.comsubblock_size=0 15111245Sandreas.sandberg@arm.comtgts_per_mshr=5 15211245Sandreas.sandberg@arm.comtrace_addr=0 15311245Sandreas.sandberg@arm.comtwo_queue=false 15411245Sandreas.sandberg@arm.comwrite_buffers=8 15511245Sandreas.sandberg@arm.comcpu_side=system.cpu.icache_port 15611245Sandreas.sandberg@arm.commem_side=system.cpu.toL2Bus.port[0] 15711245Sandreas.sandberg@arm.com 15811245Sandreas.sandberg@arm.com[system.cpu.itb] 15911245Sandreas.sandberg@arm.comtype=MipsTLB 16011245Sandreas.sandberg@arm.comsize=64 16111245Sandreas.sandberg@arm.com 16211245Sandreas.sandberg@arm.com[system.cpu.l2cache] 16311245Sandreas.sandberg@arm.comtype=BaseCache 16411245Sandreas.sandberg@arm.comaddr_range=0:18446744073709551615 16511245Sandreas.sandberg@arm.comassoc=2 16611245Sandreas.sandberg@arm.comblock_size=64 16711245Sandreas.sandberg@arm.comforward_snoops=true 16811245Sandreas.sandberg@arm.comhash_delay=1 16911245Sandreas.sandberg@arm.comlatency=10000 17011245Sandreas.sandberg@arm.commax_miss_count=0 17111245Sandreas.sandberg@arm.commshrs=10 17211245Sandreas.sandberg@arm.comnum_cpus=1 17311245Sandreas.sandberg@arm.comprefetch_data_accesses_only=false 17411245Sandreas.sandberg@arm.comprefetch_degree=1 17511245Sandreas.sandberg@arm.comprefetch_latency=100000 17611245Sandreas.sandberg@arm.comprefetch_on_access=false 17711245Sandreas.sandberg@arm.comprefetch_past_page=false 17811245Sandreas.sandberg@arm.comprefetch_policy=none 17911245Sandreas.sandberg@arm.comprefetch_serial_squash=false 18011245Sandreas.sandberg@arm.comprefetch_use_cpu_id=true 18111245Sandreas.sandberg@arm.comprefetcher_size=100 18211245Sandreas.sandberg@arm.comprioritizeRequests=false 18311245Sandreas.sandberg@arm.comrepl=Null 18411245Sandreas.sandberg@arm.comsize=2097152 18511245Sandreas.sandberg@arm.comsubblock_size=0 18611245Sandreas.sandberg@arm.comtgts_per_mshr=5 18711245Sandreas.sandberg@arm.comtrace_addr=0 18811245Sandreas.sandberg@arm.comtwo_queue=false 18911245Sandreas.sandberg@arm.comwrite_buffers=8 19011245Sandreas.sandberg@arm.comcpu_side=system.cpu.toL2Bus.port[2] 19111245Sandreas.sandberg@arm.commem_side=system.membus.port[1] 19211245Sandreas.sandberg@arm.com 19311245Sandreas.sandberg@arm.com[system.cpu.toL2Bus] 19411245Sandreas.sandberg@arm.comtype=Bus 19510778Snilay@cs.wisc.edublock_size=64 19610778Snilay@cs.wisc.edubus_id=0 19710778Snilay@cs.wisc.educlock=1000 19810778Snilay@cs.wisc.eduheader_cycles=1 19910778Snilay@cs.wisc.eduuse_default_range=false 20010778Snilay@cs.wisc.eduwidth=64 20110778Snilay@cs.wisc.eduport=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 20210778Snilay@cs.wisc.edu 20310778Snilay@cs.wisc.edu[system.cpu.tracer] 20410778Snilay@cs.wisc.edutype=ExeTracer 20510778Snilay@cs.wisc.edu 20610778Snilay@cs.wisc.edu[system.cpu.workload] 20710778Snilay@cs.wisc.edutype=LiveProcess 20810778Snilay@cs.wisc.educmd=hello 20910778Snilay@cs.wisc.educwd= 21010778Snilay@cs.wisc.eduegid=100 21110778Snilay@cs.wisc.eduenv= 21210778Snilay@cs.wisc.eduerrout=cerr 21310778Snilay@cs.wisc.edueuid=100 21410778Snilay@cs.wisc.eduexecutable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello 21510778Snilay@cs.wisc.edugid=100 21610778Snilay@cs.wisc.eduinput=cin 21710778Snilay@cs.wisc.edumax_stack_size=67108864 21810778Snilay@cs.wisc.eduoutput=cout 21910778Snilay@cs.wisc.edupid=100 22010778Snilay@cs.wisc.eduppid=99 22110778Snilay@cs.wisc.edusimpoint=0 22210778Snilay@cs.wisc.edusystem=system 22310778Snilay@cs.wisc.eduuid=100 22410778Snilay@cs.wisc.edu 22510778Snilay@cs.wisc.edu[system.membus] 22610778Snilay@cs.wisc.edutype=Bus 22710778Snilay@cs.wisc.edublock_size=64 22810778Snilay@cs.wisc.edubus_id=0 22910778Snilay@cs.wisc.educlock=1000 23010778Snilay@cs.wisc.eduheader_cycles=1 23110778Snilay@cs.wisc.eduuse_default_range=false 23210778Snilay@cs.wisc.eduwidth=64 23310778Snilay@cs.wisc.eduport=system.physmem.port[0] system.cpu.l2cache.mem_side 23410778Snilay@cs.wisc.edu 23510778Snilay@cs.wisc.edu[system.physmem] 23610778Snilay@cs.wisc.edutype=PhysicalMemory 23710778Snilay@cs.wisc.edufile= 23810778Snilay@cs.wisc.edulatency=30000 23910778Snilay@cs.wisc.edulatency_var=0 24010778Snilay@cs.wisc.edunull=false 24110778Snilay@cs.wisc.edurange=0:134217727 24210778Snilay@cs.wisc.eduzero=false 24310778Snilay@cs.wisc.eduport=system.membus.port[0] 24410778Snilay@cs.wisc.edu 24510778Snilay@cs.wisc.edu