1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=TimingSimpleCPU 58children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload 59branchPred=Null 60checker=Null 61clk_domain=system.cpu_clk_domain 62cpu_id=0 63default_p_state=UNDEFINED 64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dtb=system.cpu.dtb 68eventq_index=0 69function_trace=false 70function_trace_start=0 71interrupts=system.cpu.interrupts 72isa=system.cpu.isa 73itb=system.cpu.itb 74max_insts_all_threads=0 75max_insts_any_thread=0 76max_loads_all_threads=0 77max_loads_any_thread=0 78numThreads=1 79p_state_clk_gate_bins=20 80p_state_clk_gate_max=1000000000000 81p_state_clk_gate_min=1000 82power_model=Null 83profile=0 84progress_interval=0 85simpoint_start_insts= 86socket_id=0 87switched_out=false 88system=system 89tracer=system.cpu.tracer 90workload=system.cpu.workload 91dcache_port=system.cpu.dcache.cpu_side 92icache_port=system.cpu.icache.cpu_side 93 94[system.cpu.dcache] 95type=Cache 96children=tags 97addr_ranges=0:18446744073709551615 98assoc=2 99clk_domain=system.cpu_clk_domain 100clusivity=mostly_incl 101default_p_state=UNDEFINED 102demand_mshr_reserve=1 103eventq_index=0 104hit_latency=2 105is_read_only=false 106max_miss_count=0 107mshrs=4 108p_state_clk_gate_bins=20 109p_state_clk_gate_max=1000000000000 110p_state_clk_gate_min=1000 111power_model=Null 112prefetch_on_access=false 113prefetcher=Null 114response_latency=2 115sequential_access=false 116size=262144 117system=system 118tags=system.cpu.dcache.tags 119tgts_per_mshr=20 120write_buffers=8 121writeback_clean=false 122cpu_side=system.cpu.dcache_port 123mem_side=system.cpu.toL2Bus.slave[1] 124 125[system.cpu.dcache.tags] 126type=LRU 127assoc=2 128block_size=64 129clk_domain=system.cpu_clk_domain 130default_p_state=UNDEFINED 131eventq_index=0 132hit_latency=2 133p_state_clk_gate_bins=20 134p_state_clk_gate_max=1000000000000 135p_state_clk_gate_min=1000 136power_model=Null 137sequential_access=false 138size=262144 139 140[system.cpu.dtb] 141type=MipsTLB 142eventq_index=0 143size=64 144 145[system.cpu.icache] 146type=Cache 147children=tags 148addr_ranges=0:18446744073709551615 149assoc=2 150clk_domain=system.cpu_clk_domain 151clusivity=mostly_incl 152default_p_state=UNDEFINED 153demand_mshr_reserve=1 154eventq_index=0 155hit_latency=2 156is_read_only=true 157max_miss_count=0 158mshrs=4 159p_state_clk_gate_bins=20 160p_state_clk_gate_max=1000000000000 161p_state_clk_gate_min=1000 162power_model=Null 163prefetch_on_access=false 164prefetcher=Null 165response_latency=2 166sequential_access=false 167size=131072 168system=system 169tags=system.cpu.icache.tags 170tgts_per_mshr=20 171write_buffers=8 172writeback_clean=true 173cpu_side=system.cpu.icache_port 174mem_side=system.cpu.toL2Bus.slave[0] 175 176[system.cpu.icache.tags] 177type=LRU 178assoc=2 179block_size=64 180clk_domain=system.cpu_clk_domain 181default_p_state=UNDEFINED 182eventq_index=0 183hit_latency=2 184p_state_clk_gate_bins=20 185p_state_clk_gate_max=1000000000000 186p_state_clk_gate_min=1000 187power_model=Null 188sequential_access=false 189size=131072 190 191[system.cpu.interrupts] 192type=MipsInterrupts 193eventq_index=0 194 195[system.cpu.isa] 196type=MipsISA 197eventq_index=0 198num_threads=1 199num_vpes=1 200system=system 201 202[system.cpu.itb] 203type=MipsTLB 204eventq_index=0 205size=64 206 207[system.cpu.l2cache] 208type=Cache 209children=tags 210addr_ranges=0:18446744073709551615 211assoc=8 212clk_domain=system.cpu_clk_domain 213clusivity=mostly_incl 214default_p_state=UNDEFINED 215demand_mshr_reserve=1 216eventq_index=0 217hit_latency=20 218is_read_only=false 219max_miss_count=0 220mshrs=20 221p_state_clk_gate_bins=20 222p_state_clk_gate_max=1000000000000 223p_state_clk_gate_min=1000 224power_model=Null 225prefetch_on_access=false 226prefetcher=Null 227response_latency=20 228sequential_access=false 229size=2097152 230system=system 231tags=system.cpu.l2cache.tags 232tgts_per_mshr=12 233write_buffers=8 234writeback_clean=false 235cpu_side=system.cpu.toL2Bus.master[0] 236mem_side=system.membus.slave[1] 237 238[system.cpu.l2cache.tags] 239type=LRU 240assoc=8 241block_size=64 242clk_domain=system.cpu_clk_domain 243default_p_state=UNDEFINED 244eventq_index=0 245hit_latency=20 246p_state_clk_gate_bins=20 247p_state_clk_gate_max=1000000000000 248p_state_clk_gate_min=1000 249power_model=Null 250sequential_access=false 251size=2097152 252 253[system.cpu.toL2Bus] 254type=CoherentXBar 255children=snoop_filter 256clk_domain=system.cpu_clk_domain 257default_p_state=UNDEFINED 258eventq_index=0 259forward_latency=0 260frontend_latency=1 261p_state_clk_gate_bins=20 262p_state_clk_gate_max=1000000000000 263p_state_clk_gate_min=1000 264point_of_coherency=false 265power_model=Null 266response_latency=1 267snoop_filter=system.cpu.toL2Bus.snoop_filter 268snoop_response_latency=1 269system=system 270use_default_range=false 271width=32 272master=system.cpu.l2cache.cpu_side 273slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 274 275[system.cpu.toL2Bus.snoop_filter] 276type=SnoopFilter 277eventq_index=0 278lookup_latency=0 279max_capacity=8388608 280system=system 281 282[system.cpu.tracer] 283type=ExeTracer 284eventq_index=0 285 286[system.cpu.workload] 287type=LiveProcess 288cmd=hello 289cwd= 290drivers= 291egid=100 292env= 293errout=cerr 294euid=100 295eventq_index=0 296executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/mips/linux/hello 297gid=100 298input=cin 299kvmInSE=false 300max_stack_size=67108864 301output=cout 302pid=100 303ppid=99 304simpoint=0 305system=system 306uid=100 307useArchPT=false 308 309[system.cpu_clk_domain] 310type=SrcClockDomain 311clock=500 312domain_id=-1 313eventq_index=0 314init_perf_level=0 315voltage_domain=system.voltage_domain 316 317[system.dvfs_handler] 318type=DVFSHandler 319domains= 320enable=false 321eventq_index=0 322sys_clk_domain=system.clk_domain 323transition_latency=100000000 324 325[system.membus] 326type=CoherentXBar 327clk_domain=system.clk_domain 328default_p_state=UNDEFINED 329eventq_index=0 330forward_latency=4 331frontend_latency=3 332p_state_clk_gate_bins=20 333p_state_clk_gate_max=1000000000000 334p_state_clk_gate_min=1000 335point_of_coherency=true 336power_model=Null 337response_latency=2 338snoop_filter=Null 339snoop_response_latency=4 340system=system 341use_default_range=false 342width=16 343master=system.physmem.port 344slave=system.system_port system.cpu.l2cache.mem_side 345 346[system.physmem] 347type=SimpleMemory 348bandwidth=73.000000 349clk_domain=system.clk_domain 350conf_table_reported=true 351default_p_state=UNDEFINED 352eventq_index=0 353in_addr_map=true 354latency=30000 355latency_var=0 356null=false 357p_state_clk_gate_bins=20 358p_state_clk_gate_max=1000000000000 359p_state_clk_gate_min=1000 360power_model=Null 361range=0:134217727 362port=system.membus.master[0] 363 364[system.voltage_domain] 365type=VoltageDomain 366eventq_index=0 367voltage=1.000000 368 369