config.ini revision 5509
12934Sktlim@umich.edu[root] 22934Sktlim@umich.edutype=Root 32934Sktlim@umich.educhildren=system 42934Sktlim@umich.edudummy=0 52934Sktlim@umich.edu 62934Sktlim@umich.edu[system] 72934Sktlim@umich.edutype=System 82934Sktlim@umich.educhildren=cpu membus physmem 92934Sktlim@umich.edumem_mode=atomic 102934Sktlim@umich.eduphysmem=system.physmem 112934Sktlim@umich.edu 122934Sktlim@umich.edu[system.cpu] 132934Sktlim@umich.edutype=TimingSimpleCPU 142934Sktlim@umich.educhildren=dcache dtb icache itb l2cache tlb toL2Bus tracer workload 152934Sktlim@umich.eduCP0_Config=0 162934Sktlim@umich.eduCP0_Config1=0 172934Sktlim@umich.eduCP0_Config1_C2=false 182934Sktlim@umich.eduCP0_Config1_CA=false 192934Sktlim@umich.eduCP0_Config1_DA=0 202934Sktlim@umich.eduCP0_Config1_DL=0 212934Sktlim@umich.eduCP0_Config1_DS=0 222934Sktlim@umich.eduCP0_Config1_EP=false 232934Sktlim@umich.eduCP0_Config1_FP=false 242934Sktlim@umich.eduCP0_Config1_IA=0 252934Sktlim@umich.eduCP0_Config1_IL=0 262934Sktlim@umich.eduCP0_Config1_IS=0 272934Sktlim@umich.eduCP0_Config1_M=0 282934Sktlim@umich.eduCP0_Config1_MD=false 292934Sktlim@umich.eduCP0_Config1_MMU=0 302969Sktlim@umich.eduCP0_Config1_PC=false 312934Sktlim@umich.eduCP0_Config1_WR=false 322995Ssaidi@eecs.umich.eduCP0_Config2=0 332934Sktlim@umich.eduCP0_Config2_M=false 342934Sktlim@umich.eduCP0_Config2_SA=0 352934Sktlim@umich.eduCP0_Config2_SL=0 362934Sktlim@umich.eduCP0_Config2_SS=0 372934Sktlim@umich.eduCP0_Config2_SU=0 382934Sktlim@umich.eduCP0_Config2_TA=0 392934Sktlim@umich.eduCP0_Config2_TL=0 402934Sktlim@umich.eduCP0_Config2_TS=0 412934Sktlim@umich.eduCP0_Config2_TU=0 422934Sktlim@umich.eduCP0_Config3=0 432934Sktlim@umich.eduCP0_Config3_DSPP=false 442934Sktlim@umich.eduCP0_Config3_LPA=false 452934Sktlim@umich.eduCP0_Config3_M=false 462934Sktlim@umich.eduCP0_Config3_MT=false 472934Sktlim@umich.eduCP0_Config3_SM=false 483005Sstever@eecs.umich.eduCP0_Config3_SP=false 492934Sktlim@umich.eduCP0_Config3_TL=false 503005Sstever@eecs.umich.eduCP0_Config3_VEIC=false 513005Sstever@eecs.umich.eduCP0_Config3_VInt=false 523304Sstever@eecs.umich.eduCP0_Config_AR=0 532995Ssaidi@eecs.umich.eduCP0_Config_AT=0 542934Sktlim@umich.eduCP0_Config_BE=0 552934Sktlim@umich.eduCP0_Config_MT=0 562934Sktlim@umich.eduCP0_Config_VI=0 572995Ssaidi@eecs.umich.eduCP0_EBase_CPUNum=0 582934Sktlim@umich.eduCP0_IntCtl_IPPCI=0 592934Sktlim@umich.eduCP0_IntCtl_IPTI=0 602934Sktlim@umich.eduCP0_PRId=0 612934Sktlim@umich.eduCP0_PRId_CompanyID=0 622934Sktlim@umich.eduCP0_PRId_CompanyOptions=0 632995Ssaidi@eecs.umich.eduCP0_PRId_ProcessorID=1 642934Sktlim@umich.eduCP0_PRId_Revision=0 652934Sktlim@umich.eduCP0_PerfCtr_M=false 662934Sktlim@umich.eduCP0_PerfCtr_W=false 672934Sktlim@umich.eduCP0_SrsCtl_HSS=0 682934Sktlim@umich.eduCP0_WatchHi_M=false 692995Ssaidi@eecs.umich.eduUnifiedTLB=true 702934Sktlim@umich.educlock=500 712934Sktlim@umich.educpu_id=0 722953Sktlim@umich.edudefer_registration=false 732934Sktlim@umich.edudtb=system.cpu.dtb 742934Sktlim@umich.edufunction_trace=false 753449Shsul@eecs.umich.edufunction_trace_start=0 762934Sktlim@umich.eduitb=system.cpu.itb 772934Sktlim@umich.edumax_insts_all_threads=0 782934Sktlim@umich.edumax_insts_any_thread=0 792934Sktlim@umich.edumax_loads_all_threads=0 802934Sktlim@umich.edumax_loads_any_thread=0 813584Ssaidi@eecs.umich.eduphase=0 823584Ssaidi@eecs.umich.eduprogress_interval=0 833584Ssaidi@eecs.umich.edusystem=system 843584Ssaidi@eecs.umich.edutlb=system.cpu.tlb 853584Ssaidi@eecs.umich.edutracer=system.cpu.tracer 863584Ssaidi@eecs.umich.eduworkload=system.cpu.workload 873743Sgblack@eecs.umich.edudcache_port=system.cpu.dcache.cpu_side 883584Ssaidi@eecs.umich.eduicache_port=system.cpu.icache.cpu_side 893743Sgblack@eecs.umich.edu 903743Sgblack@eecs.umich.edu[system.cpu.dcache] 913743Sgblack@eecs.umich.edutype=BaseCache 923823Ssaidi@eecs.umich.eduaddr_range=0:18446744073709551615 933814Ssaidi@eecs.umich.eduassoc=2 943743Sgblack@eecs.umich.edublock_size=64 953743Sgblack@eecs.umich.educpu_side_filter_ranges= 963584Ssaidi@eecs.umich.eduhash_delay=1 973814Ssaidi@eecs.umich.edulatency=1000 983584Ssaidi@eecs.umich.edulifo=false 993745Sgblack@eecs.umich.edumax_miss_count=0 1003745Sgblack@eecs.umich.edumem_side_filter_ranges= 1013745Sgblack@eecs.umich.edumshrs=10 1023584Ssaidi@eecs.umich.eduprefetch_access=false 1033584Ssaidi@eecs.umich.eduprefetch_cache_check_push=true 1043584Ssaidi@eecs.umich.eduprefetch_data_accesses_only=false 1053584Ssaidi@eecs.umich.eduprefetch_degree=1 1063584Ssaidi@eecs.umich.eduprefetch_latency=10000 1073584Ssaidi@eecs.umich.eduprefetch_miss=false 1083745Sgblack@eecs.umich.eduprefetch_past_page=false 1093745Sgblack@eecs.umich.eduprefetch_policy=none 1103745Sgblack@eecs.umich.eduprefetch_serial_squash=false 1113584Ssaidi@eecs.umich.eduprefetch_use_cpu_id=true 1123584Ssaidi@eecs.umich.eduprefetcher_size=100 1133584Ssaidi@eecs.umich.eduprioritizeRequests=false 1143584Ssaidi@eecs.umich.edurepl=Null 1153025Ssaidi@eecs.umich.edusize=262144 1162934Sktlim@umich.edusplit=false 1172995Ssaidi@eecs.umich.edusplit_size=0 1182995Ssaidi@eecs.umich.edusubblock_size=0 1193025Ssaidi@eecs.umich.edutgts_per_mshr=5 1203025Ssaidi@eecs.umich.edutrace_addr=0 1213025Ssaidi@eecs.umich.edutwo_queue=false 1223025Ssaidi@eecs.umich.eduwrite_buffers=8 1233025Ssaidi@eecs.umich.educpu_side=system.cpu.dcache_port 1242934Sktlim@umich.edumem_side=system.cpu.toL2Bus.port[1] 1252934Sktlim@umich.edu 1262934Sktlim@umich.edu[system.cpu.dtb] 127type=MipsDTB 128size=64 129 130[system.cpu.icache] 131type=BaseCache 132addr_range=0:18446744073709551615 133assoc=2 134block_size=64 135cpu_side_filter_ranges= 136hash_delay=1 137latency=1000 138lifo=false 139max_miss_count=0 140mem_side_filter_ranges= 141mshrs=10 142prefetch_access=false 143prefetch_cache_check_push=true 144prefetch_data_accesses_only=false 145prefetch_degree=1 146prefetch_latency=10000 147prefetch_miss=false 148prefetch_past_page=false 149prefetch_policy=none 150prefetch_serial_squash=false 151prefetch_use_cpu_id=true 152prefetcher_size=100 153prioritizeRequests=false 154repl=Null 155size=131072 156split=false 157split_size=0 158subblock_size=0 159tgts_per_mshr=5 160trace_addr=0 161two_queue=false 162write_buffers=8 163cpu_side=system.cpu.icache_port 164mem_side=system.cpu.toL2Bus.port[0] 165 166[system.cpu.itb] 167type=MipsITB 168size=64 169 170[system.cpu.l2cache] 171type=BaseCache 172addr_range=0:18446744073709551615 173assoc=2 174block_size=64 175cpu_side_filter_ranges= 176hash_delay=1 177latency=10000 178lifo=false 179max_miss_count=0 180mem_side_filter_ranges= 181mshrs=10 182prefetch_access=false 183prefetch_cache_check_push=true 184prefetch_data_accesses_only=false 185prefetch_degree=1 186prefetch_latency=100000 187prefetch_miss=false 188prefetch_past_page=false 189prefetch_policy=none 190prefetch_serial_squash=false 191prefetch_use_cpu_id=true 192prefetcher_size=100 193prioritizeRequests=false 194repl=Null 195size=2097152 196split=false 197split_size=0 198subblock_size=0 199tgts_per_mshr=5 200trace_addr=0 201two_queue=false 202write_buffers=8 203cpu_side=system.cpu.toL2Bus.port[2] 204mem_side=system.membus.port[1] 205 206[system.cpu.tlb] 207type=MipsUTB 208size=64 209 210[system.cpu.toL2Bus] 211type=Bus 212block_size=64 213bus_id=0 214clock=1000 215header_cycles=1 216responder_set=false 217width=64 218port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 219 220[system.cpu.tracer] 221type=ExeTracer 222 223[system.cpu.workload] 224type=LiveProcess 225cmd=hello 226cwd= 227egid=100 228env= 229euid=100 230executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello 231gid=100 232input=cin 233max_stack_size=67108864 234output=cout 235pid=100 236ppid=99 237simpoint=0 238system=system 239uid=100 240 241[system.membus] 242type=Bus 243block_size=64 244bus_id=0 245clock=1000 246header_cycles=1 247responder_set=false 248width=64 249port=system.physmem.port[0] system.cpu.l2cache.mem_side 250 251[system.physmem] 252type=PhysicalMemory 253file= 254latency=1 255latency_var=0 256null=false 257range=0:134217727 258zero=false 259port=system.membus.port[0] 260 261