stats.txt revision 8835
16039SN/A 26039SN/A---------- Begin Simulation Statistics ---------- 38464SN/Asim_seconds 0.000012 # Number of seconds simulated 48546SN/Asim_ticks 12272500 # Number of ticks simulated 58721SN/Afinal_tick 12272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 78835SAli.Saidi@ARM.comhost_inst_rate 97350 # Simulator instruction rate (inst/s) 88835SAli.Saidi@ARM.comhost_op_rate 97317 # Simulator op (including micro ops) rate (op/s) 98835SAli.Saidi@ARM.comhost_tick_rate 230983195 # Simulator tick rate (ticks/s) 108835SAli.Saidi@ARM.comhost_mem_usage 211060 # Number of bytes of host memory used 118835SAli.Saidi@ARM.comhost_seconds 0.05 # Real time elapsed on the host 128428SN/Asim_insts 5169 # Number of instructions simulated 138835SAli.Saidi@ARM.comsim_ops 5169 # Number of ops (including micro ops) simulated 148721SN/Asystem.physmem.bytes_read 30400 # Number of bytes read from this memory 158721SN/Asystem.physmem.bytes_inst_read 21312 # Number of instructions bytes read from this memory 168721SN/Asystem.physmem.bytes_written 0 # Number of bytes written to this memory 178721SN/Asystem.physmem.num_reads 475 # Number of read requests responded to by this memory 188721SN/Asystem.physmem.num_writes 0 # Number of write requests responded to by this memory 198721SN/Asystem.physmem.num_other 0 # Number of other requests responded to by this memory 208721SN/Asystem.physmem.bw_read 2477082909 # Total read bandwidth from this memory (bytes/s) 218721SN/Asystem.physmem.bw_inst_read 1736565492 # Instruction read bandwidth from this memory (bytes/s) 228721SN/Asystem.physmem.bw_total 2477082909 # Total bandwidth to/from this memory (bytes/s) 238428SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 248428SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 258428SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 268428SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 278428SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 288428SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 296039SN/Asystem.cpu.dtb.hits 0 # DTB hits 306039SN/Asystem.cpu.dtb.misses 0 # DTB misses 318428SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 328428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 338428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 348428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 358428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 368428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 378428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 388428SN/Asystem.cpu.itb.hits 0 # DTB hits 398428SN/Asystem.cpu.itb.misses 0 # DTB misses 408428SN/Asystem.cpu.itb.accesses 0 # DTB accesses 418428SN/Asystem.cpu.workload.num_syscalls 8 # Number of system calls 428546SN/Asystem.cpu.numCycles 24546 # number of cpu cycles simulated 438428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 448428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 458546SN/Asystem.cpu.BPredUnit.lookups 1975 # Number of BP lookups 468546SN/Asystem.cpu.BPredUnit.condPredicted 1343 # Number of conditional branches predicted 478464SN/Asystem.cpu.BPredUnit.condIncorrect 399 # Number of conditional branches incorrect 488546SN/Asystem.cpu.BPredUnit.BTBLookups 1578 # Number of BTB lookups 498517SN/Asystem.cpu.BPredUnit.BTBHits 493 # Number of BTB hits 508428SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 518464SN/Asystem.cpu.BPredUnit.usedRAS 251 # Number of times the RAS was used to get a target. 528464SN/Asystem.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. 538546SN/Asystem.cpu.fetch.icacheStallCycles 7903 # Number of cycles fetch is stalled on an Icache miss 548546SN/Asystem.cpu.fetch.Insts 12258 # Number of instructions fetch has processed 558546SN/Asystem.cpu.fetch.Branches 1975 # Number of branches that fetch encountered 568517SN/Asystem.cpu.fetch.predictedBranches 744 # Number of branches that fetch has predicted taken 578546SN/Asystem.cpu.fetch.Cycles 3024 # Number of cycles fetch has run and was not squashing or blocked 588546SN/Asystem.cpu.fetch.SquashCycles 1186 # Number of cycles fetch has spent squashing 598464SN/Asystem.cpu.fetch.BlockedCycles 756 # Number of cycles fetch has spent blocked 608464SN/Asystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 618464SN/Asystem.cpu.fetch.PendingTrapStallCycles 145 # Number of stall cycles due to pending traps 628546SN/Asystem.cpu.fetch.CacheLines 1781 # Number of cache lines fetched 638546SN/Asystem.cpu.fetch.IcacheSquashes 229 # Number of outstanding Icache misses that were squashed 648546SN/Asystem.cpu.fetch.rateDist::samples 12608 # Number of instructions fetched each cycle (Total) 658546SN/Asystem.cpu.fetch.rateDist::mean 0.972240 # Number of instructions fetched each cycle (Total) 668546SN/Asystem.cpu.fetch.rateDist::stdev 2.277843 # Number of instructions fetched each cycle (Total) 676291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 688546SN/Asystem.cpu.fetch.rateDist::0 9584 76.02% 76.02% # Number of instructions fetched each cycle (Total) 698546SN/Asystem.cpu.fetch.rateDist::1 1250 9.91% 85.93% # Number of instructions fetched each cycle (Total) 708517SN/Asystem.cpu.fetch.rateDist::2 108 0.86% 86.79% # Number of instructions fetched each cycle (Total) 718517SN/Asystem.cpu.fetch.rateDist::3 139 1.10% 87.89% # Number of instructions fetched each cycle (Total) 728517SN/Asystem.cpu.fetch.rateDist::4 289 2.29% 90.18% # Number of instructions fetched each cycle (Total) 738546SN/Asystem.cpu.fetch.rateDist::5 92 0.73% 90.91% # Number of instructions fetched each cycle (Total) 748517SN/Asystem.cpu.fetch.rateDist::6 132 1.05% 91.96% # Number of instructions fetched each cycle (Total) 758517SN/Asystem.cpu.fetch.rateDist::7 145 1.15% 93.11% # Number of instructions fetched each cycle (Total) 768546SN/Asystem.cpu.fetch.rateDist::8 869 6.89% 100.00% # Number of instructions fetched each cycle (Total) 776291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 786291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 796291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 808546SN/Asystem.cpu.fetch.rateDist::total 12608 # Number of instructions fetched each cycle (Total) 818546SN/Asystem.cpu.fetch.branchRate 0.080461 # Number of branch fetches per cycle 828546SN/Asystem.cpu.fetch.rate 0.499389 # Number of inst fetches per cycle 838546SN/Asystem.cpu.decode.IdleCycles 8092 # Number of cycles decode is idle 848464SN/Asystem.cpu.decode.BlockedCycles 871 # Number of cycles decode is blocked 858546SN/Asystem.cpu.decode.RunCycles 2857 # Number of cycles decode is running 868464SN/Asystem.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking 878546SN/Asystem.cpu.decode.SquashCycles 737 # Number of cycles decode is squashing 888464SN/Asystem.cpu.decode.BranchResolved 107 # Number of times decode resolved a branch 898464SN/Asystem.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction 908546SN/Asystem.cpu.decode.DecodedInsts 11425 # Number of instructions handled by decode 918464SN/Asystem.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode 928546SN/Asystem.cpu.rename.SquashCycles 737 # Number of cycles rename is squashing 938546SN/Asystem.cpu.rename.IdleCycles 8263 # Number of cycles rename is idle 948464SN/Asystem.cpu.rename.BlockCycles 258 # Number of cycles rename is blocking 958464SN/Asystem.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst 968546SN/Asystem.cpu.rename.RunCycles 2740 # Number of cycles rename is running 978464SN/Asystem.cpu.rename.UnblockCycles 111 # Number of cycles rename is unblocking 988546SN/Asystem.cpu.rename.RenamedInsts 11004 # Number of instructions processed by rename 998464SN/Asystem.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full 1008546SN/Asystem.cpu.rename.RenamedOperands 6697 # Number of destination operands rename has renamed 1018554SN/Asystem.cpu.rename.RenameLookups 13109 # Number of register rename lookups that rename has made 1028546SN/Asystem.cpu.rename.int_rename_lookups 13105 # Number of integer rename lookups 1038554SN/Asystem.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 1048428SN/Asystem.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed 1058546SN/Asystem.cpu.rename.UndoneMaps 3287 # Number of HB maps that are undone due to squashing 1068464SN/Asystem.cpu.rename.serializingInsts 18 # count of serializing insts renamed 1078464SN/Asystem.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed 1088464SN/Asystem.cpu.rename.skidInsts 281 # count of insts added to the skid buffer 1098546SN/Asystem.cpu.memDep0.insertedLoads 2346 # Number of loads inserted to the mem dependence unit. 1108546SN/Asystem.cpu.memDep0.insertedStores 1174 # Number of stores inserted to the mem dependence unit. 1118428SN/Asystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 1128428SN/Asystem.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 1138546SN/Asystem.cpu.iq.iqInstsAdded 8640 # Number of instructions added to the IQ (excludes non-spec) 1148464SN/Asystem.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ 1158546SN/Asystem.cpu.iq.iqInstsIssued 7815 # Number of instructions issued 1168517SN/Asystem.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued 1178546SN/Asystem.cpu.iq.iqSquashedInstsExamined 2984 # Number of squashed instructions iterated over during squash; mainly for profiling 1188546SN/Asystem.cpu.iq.iqSquashedOperandsExamined 1806 # Number of squashed operands that are examined and possibly removed from graph 1198464SN/Asystem.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed 1208546SN/Asystem.cpu.iq.issued_per_cycle::samples 12608 # Number of insts issued each cycle 1218546SN/Asystem.cpu.iq.issued_per_cycle::mean 0.619845 # Number of insts issued each cycle 1228546SN/Asystem.cpu.iq.issued_per_cycle::stdev 1.285923 # Number of insts issued each cycle 1238428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1248546SN/Asystem.cpu.iq.issued_per_cycle::0 9257 73.42% 73.42% # Number of insts issued each cycle 1258546SN/Asystem.cpu.iq.issued_per_cycle::1 1317 10.45% 83.87% # Number of insts issued each cycle 1268546SN/Asystem.cpu.iq.issued_per_cycle::2 832 6.60% 90.47% # Number of insts issued each cycle 1278546SN/Asystem.cpu.iq.issued_per_cycle::3 510 4.05% 94.51% # Number of insts issued each cycle 1288546SN/Asystem.cpu.iq.issued_per_cycle::4 356 2.82% 97.34% # Number of insts issued each cycle 1298546SN/Asystem.cpu.iq.issued_per_cycle::5 201 1.59% 98.93% # Number of insts issued each cycle 1308546SN/Asystem.cpu.iq.issued_per_cycle::6 85 0.67% 99.60% # Number of insts issued each cycle 1318517SN/Asystem.cpu.iq.issued_per_cycle::7 35 0.28% 99.88% # Number of insts issued each cycle 1328464SN/Asystem.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle 1338428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1348428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1358428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1368546SN/Asystem.cpu.iq.issued_per_cycle::total 12608 # Number of insts issued each cycle 1378428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1388517SN/Asystem.cpu.iq.fu_full::IntAlu 3 2.05% 2.05% # attempts to use FU when none available 1398517SN/Asystem.cpu.iq.fu_full::IntMult 0 0.00% 2.05% # attempts to use FU when none available 1408517SN/Asystem.cpu.iq.fu_full::IntDiv 0 0.00% 2.05% # attempts to use FU when none available 1418517SN/Asystem.cpu.iq.fu_full::FloatAdd 0 0.00% 2.05% # attempts to use FU when none available 1428517SN/Asystem.cpu.iq.fu_full::FloatCmp 0 0.00% 2.05% # attempts to use FU when none available 1438517SN/Asystem.cpu.iq.fu_full::FloatCvt 0 0.00% 2.05% # attempts to use FU when none available 1448517SN/Asystem.cpu.iq.fu_full::FloatMult 0 0.00% 2.05% # attempts to use FU when none available 1458517SN/Asystem.cpu.iq.fu_full::FloatDiv 0 0.00% 2.05% # attempts to use FU when none available 1468517SN/Asystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.05% # attempts to use FU when none available 1478517SN/Asystem.cpu.iq.fu_full::SimdAdd 0 0.00% 2.05% # attempts to use FU when none available 1488517SN/Asystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.05% # attempts to use FU when none available 1498517SN/Asystem.cpu.iq.fu_full::SimdAlu 0 0.00% 2.05% # attempts to use FU when none available 1508517SN/Asystem.cpu.iq.fu_full::SimdCmp 0 0.00% 2.05% # attempts to use FU when none available 1518517SN/Asystem.cpu.iq.fu_full::SimdCvt 0 0.00% 2.05% # attempts to use FU when none available 1528517SN/Asystem.cpu.iq.fu_full::SimdMisc 0 0.00% 2.05% # attempts to use FU when none available 1538517SN/Asystem.cpu.iq.fu_full::SimdMult 0 0.00% 2.05% # attempts to use FU when none available 1548517SN/Asystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.05% # attempts to use FU when none available 1558517SN/Asystem.cpu.iq.fu_full::SimdShift 0 0.00% 2.05% # attempts to use FU when none available 1568517SN/Asystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.05% # attempts to use FU when none available 1578517SN/Asystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.05% # attempts to use FU when none available 1588517SN/Asystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.05% # attempts to use FU when none available 1598517SN/Asystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.05% # attempts to use FU when none available 1608517SN/Asystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.05% # attempts to use FU when none available 1618517SN/Asystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.05% # attempts to use FU when none available 1628517SN/Asystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.05% # attempts to use FU when none available 1638517SN/Asystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.05% # attempts to use FU when none available 1648517SN/Asystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.05% # attempts to use FU when none available 1658517SN/Asystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.05% # attempts to use FU when none available 1668517SN/Asystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.05% # attempts to use FU when none available 1678517SN/Asystem.cpu.iq.fu_full::MemRead 91 62.33% 64.38% # attempts to use FU when none available 1688517SN/Asystem.cpu.iq.fu_full::MemWrite 52 35.62% 100.00% # attempts to use FU when none available 1698428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1708428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1718241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 1728546SN/Asystem.cpu.iq.FU_type_0::IntAlu 4596 58.81% 58.81% # Type of FU issued 1738546SN/Asystem.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued 1748546SN/Asystem.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.89% # Type of FU issued 1758546SN/Asystem.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.91% # Type of FU issued 1768546SN/Asystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued 1778546SN/Asystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued 1788546SN/Asystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued 1798546SN/Asystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued 1808546SN/Asystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued 1818546SN/Asystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued 1828546SN/Asystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued 1838546SN/Asystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued 1848546SN/Asystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued 1858546SN/Asystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued 1868546SN/Asystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued 1878546SN/Asystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued 1888546SN/Asystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued 1898546SN/Asystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued 1908546SN/Asystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued 1918546SN/Asystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued 1928546SN/Asystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued 1938546SN/Asystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued 1948546SN/Asystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued 1958546SN/Asystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued 1968546SN/Asystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued 1978546SN/Asystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued 1988546SN/Asystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued 1998546SN/Asystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued 2008546SN/Asystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued 2018546SN/Asystem.cpu.iq.FU_type_0::MemRead 2128 27.23% 86.14% # Type of FU issued 2028546SN/Asystem.cpu.iq.FU_type_0::MemWrite 1083 13.86% 100.00% # Type of FU issued 2038241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2048241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2058546SN/Asystem.cpu.iq.FU_type_0::total 7815 # Type of FU issued 2068546SN/Asystem.cpu.iq.rate 0.318382 # Inst issue rate 2078517SN/Asystem.cpu.iq.fu_busy_cnt 146 # FU busy when requested 2088546SN/Asystem.cpu.iq.fu_busy_rate 0.018682 # FU busy rate (busy events/executed inst) 2098546SN/Asystem.cpu.iq.int_inst_queue_reads 28430 # Number of integer instruction queue reads 2108546SN/Asystem.cpu.iq.int_inst_queue_writes 11643 # Number of integer instruction queue writes 2118546SN/Asystem.cpu.iq.int_inst_queue_wakeup_accesses 7116 # Number of integer instruction queue wakeup accesses 2128428SN/Asystem.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 2138428SN/Asystem.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 2148428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 2158546SN/Asystem.cpu.iq.int_alu_accesses 7959 # Number of integer alu accesses 2168428SN/Asystem.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 2178464SN/Asystem.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores 2188428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2198546SN/Asystem.cpu.iew.lsq.thread0.squashedLoads 1182 # Number of loads squashed 2208464SN/Asystem.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 2218546SN/Asystem.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations 2228546SN/Asystem.cpu.iew.lsq.thread0.squashedStores 249 # Number of stores squashed 2238428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2248428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2258428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2268428SN/Asystem.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2278428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2288546SN/Asystem.cpu.iew.iewSquashCycles 737 # Number of cycles IEW is squashing 2298428SN/Asystem.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking 2308464SN/Asystem.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking 2318546SN/Asystem.cpu.iew.iewDispatchedInsts 10031 # Number of instructions dispatched to IQ 2328464SN/Asystem.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch 2338546SN/Asystem.cpu.iew.iewDispLoadInsts 2346 # Number of dispatched load instructions 2348546SN/Asystem.cpu.iew.iewDispStoreInsts 1174 # Number of dispatched store instructions 2358464SN/Asystem.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions 2368428SN/Asystem.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall 2378464SN/Asystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2388546SN/Asystem.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations 2398464SN/Asystem.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly 2408464SN/Asystem.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly 2418464SN/Asystem.cpu.iew.branchMispredicts 416 # Number of branch mispredicts detected at execute 2428546SN/Asystem.cpu.iew.iewExecutedInsts 7531 # Number of executed instructions 2438546SN/Asystem.cpu.iew.iewExecLoadInsts 2028 # Number of load instructions executed 2448546SN/Asystem.cpu.iew.iewExecSquashedInsts 284 # Number of squashed instructions skipped in execute 2458428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 2468546SN/Asystem.cpu.iew.exec_nop 1378 # number of nop insts executed 2478546SN/Asystem.cpu.iew.exec_refs 3087 # number of memory reference insts executed 2488517SN/Asystem.cpu.iew.exec_branches 1271 # Number of branches executed 2498546SN/Asystem.cpu.iew.exec_stores 1059 # Number of stores executed 2508546SN/Asystem.cpu.iew.exec_rate 0.306812 # Inst execution rate 2518546SN/Asystem.cpu.iew.wb_sent 7210 # cumulative count of insts sent to commit 2528546SN/Asystem.cpu.iew.wb_count 7118 # cumulative count of insts written-back 2538546SN/Asystem.cpu.iew.wb_producers 2758 # num instructions producing a value 2548546SN/Asystem.cpu.iew.wb_consumers 3946 # num instructions consuming a value 2558428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2568546SN/Asystem.cpu.iew.wb_rate 0.289986 # insts written-back per cycle 2578546SN/Asystem.cpu.iew.wb_fanout 0.698936 # average fanout of values written-back 2588428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2598428SN/Asystem.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions 2608835SAli.Saidi@ARM.comsystem.cpu.commit.commitCommittedOps 5826 # The number of committed instructions 2618546SN/Asystem.cpu.commit.commitSquashedInsts 4197 # The number of squashed insts skipped by commit 2628428SN/Asystem.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 2638464SN/Asystem.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted 2648546SN/Asystem.cpu.commit.committed_per_cycle::samples 11871 # Number of insts commited each cycle 2658546SN/Asystem.cpu.commit.committed_per_cycle::mean 0.490776 # Number of insts commited each cycle 2668546SN/Asystem.cpu.commit.committed_per_cycle::stdev 1.277197 # Number of insts commited each cycle 2678428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2688546SN/Asystem.cpu.commit.committed_per_cycle::0 9472 79.79% 79.79% # Number of insts commited each cycle 2698546SN/Asystem.cpu.commit.committed_per_cycle::1 966 8.14% 87.93% # Number of insts commited each cycle 2708546SN/Asystem.cpu.commit.committed_per_cycle::2 656 5.53% 93.45% # Number of insts commited each cycle 2718517SN/Asystem.cpu.commit.committed_per_cycle::3 321 2.70% 96.16% # Number of insts commited each cycle 2728517SN/Asystem.cpu.commit.committed_per_cycle::4 147 1.24% 97.40% # Number of insts commited each cycle 2738464SN/Asystem.cpu.commit.committed_per_cycle::5 102 0.86% 98.26% # Number of insts commited each cycle 2748464SN/Asystem.cpu.commit.committed_per_cycle::6 64 0.54% 98.80% # Number of insts commited each cycle 2758517SN/Asystem.cpu.commit.committed_per_cycle::7 41 0.35% 99.14% # Number of insts commited each cycle 2768517SN/Asystem.cpu.commit.committed_per_cycle::8 102 0.86% 100.00% # Number of insts commited each cycle 2778428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2788428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2798428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2808546SN/Asystem.cpu.commit.committed_per_cycle::total 11871 # Number of insts commited each cycle 2818835SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 5826 # Number of instructions committed 2828835SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed 2838428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 2848428SN/Asystem.cpu.commit.refs 2089 # Number of memory references committed 2858428SN/Asystem.cpu.commit.loads 1164 # Number of loads committed 2868428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 2878428SN/Asystem.cpu.commit.branches 916 # Number of branches committed 2888428SN/Asystem.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 2898428SN/Asystem.cpu.commit.int_insts 5124 # Number of committed integer instructions. 2908428SN/Asystem.cpu.commit.function_calls 87 # Number of function calls committed. 2918517SN/Asystem.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached 2928428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 2938546SN/Asystem.cpu.rob.rob_reads 21779 # The number of ROB reads 2948546SN/Asystem.cpu.rob.rob_writes 20794 # The number of ROB writes 2958464SN/Asystem.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself 2968546SN/Asystem.cpu.idleCycles 11938 # Total number of cycles that the CPU has spent unscheduled due to idling 2978428SN/Asystem.cpu.committedInsts 5169 # Number of Instructions Simulated 2988835SAli.Saidi@ARM.comsystem.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated 2998428SN/Asystem.cpu.committedInsts_total 5169 # Number of Instructions Simulated 3008546SN/Asystem.cpu.cpi 4.748694 # CPI: Cycles Per Instruction 3018546SN/Asystem.cpu.cpi_total 4.748694 # CPI: Total CPI of All Threads 3028546SN/Asystem.cpu.ipc 0.210584 # IPC: Instructions Per Cycle 3038546SN/Asystem.cpu.ipc_total 0.210584 # IPC: Total IPC of All Threads 3048546SN/Asystem.cpu.int_regfile_reads 10280 # number of integer regfile reads 3058546SN/Asystem.cpu.int_regfile_writes 4987 # number of integer regfile writes 3068428SN/Asystem.cpu.fp_regfile_reads 3 # number of floating regfile reads 3078428SN/Asystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 3088554SN/Asystem.cpu.misc_regfile_reads 153 # number of misc regfile reads 3098464SN/Asystem.cpu.icache.replacements 17 # number of replacements 3108546SN/Asystem.cpu.icache.tagsinuse 161.224498 # Cycle average of tags in use 3118546SN/Asystem.cpu.icache.total_refs 1363 # Total number of references to valid blocks. 3128464SN/Asystem.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks. 3138546SN/Asystem.cpu.icache.avg_refs 4.056548 # Average number of references to valid blocks. 3148428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3158835SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 161.224498 # Average occupied blocks per requestor 3168835SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.078723 # Average percentage of cache occupancy 3178835SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.078723 # Average percentage of cache occupancy 3188835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1363 # number of ReadReq hits 3198835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 1363 # number of ReadReq hits 3208835SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 1363 # number of demand (read+write) hits 3218835SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 1363 # number of demand (read+write) hits 3228835SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 1363 # number of overall hits 3238835SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 1363 # number of overall hits 3248835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 418 # number of ReadReq misses 3258835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 418 # number of ReadReq misses 3268835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 418 # number of demand (read+write) misses 3278835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 418 # number of demand (read+write) misses 3288835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 418 # number of overall misses 3298835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 418 # number of overall misses 3308835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15148000 # number of ReadReq miss cycles 3318835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 15148000 # number of ReadReq miss cycles 3328835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15148000 # number of demand (read+write) miss cycles 3338835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 15148000 # number of demand (read+write) miss cycles 3348835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15148000 # number of overall miss cycles 3358835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 15148000 # number of overall miss cycles 3368835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1781 # number of ReadReq accesses(hits+misses) 3378835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 1781 # number of ReadReq accesses(hits+misses) 3388835SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 1781 # number of demand (read+write) accesses 3398835SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 1781 # number of demand (read+write) accesses 3408835SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 1781 # number of overall (read+write) accesses 3418835SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 1781 # number of overall (read+write) accesses 3428835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234700 # miss rate for ReadReq accesses 3438835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.234700 # miss rate for demand accesses 3448835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.234700 # miss rate for overall accesses 3458835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36239.234450 # average ReadReq miss latency 3468835SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency 3478835SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency 3488428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3498428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3508428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3518428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3528428SN/Asystem.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 3538428SN/Asystem.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 3548428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3558428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3568835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits 3578835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits 3588835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits 3598835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits 3608835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 82 # number of overall MSHR hits 3618835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::total 82 # number of overall MSHR hits 3628835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses 3638835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 336 # number of ReadReq MSHR misses 3648835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses 3658835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 336 # number of demand (read+write) MSHR misses 3668835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses 3678835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 336 # number of overall MSHR misses 3688835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11784000 # number of ReadReq MSHR miss cycles 3698835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 11784000 # number of ReadReq MSHR miss cycles 3708835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 11784000 # number of demand (read+write) MSHR miss cycles 3718835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 11784000 # number of demand (read+write) MSHR miss cycles 3728835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 11784000 # number of overall MSHR miss cycles 3738835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 11784000 # number of overall MSHR miss cycles 3748835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for ReadReq accesses 3758835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for demand accesses 3768835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for overall accesses 3778835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35071.428571 # average ReadReq mshr miss latency 3788835SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35071.428571 # average overall mshr miss latency 3798835SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35071.428571 # average overall mshr miss latency 3808428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 3818428SN/Asystem.cpu.dcache.replacements 0 # number of replacements 3828546SN/Asystem.cpu.dcache.tagsinuse 92.121984 # Cycle average of tags in use 3838546SN/Asystem.cpu.dcache.total_refs 2380 # Total number of references to valid blocks. 3848464SN/Asystem.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. 3858546SN/Asystem.cpu.dcache.avg_refs 16.760563 # Average number of references to valid blocks. 3868428SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3878835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 92.121984 # Average occupied blocks per requestor 3888835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.022491 # Average percentage of cache occupancy 3898835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.022491 # Average percentage of cache occupancy 3908835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1802 # number of ReadReq hits 3918835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 1802 # number of ReadReq hits 3928835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 578 # number of WriteReq hits 3938835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 578 # number of WriteReq hits 3948835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 2380 # number of demand (read+write) hits 3958835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 2380 # number of demand (read+write) hits 3968835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 2380 # number of overall hits 3978835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 2380 # number of overall hits 3988835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses 3998835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses 4008835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 347 # number of WriteReq misses 4018835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 347 # number of WriteReq misses 4028835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses 4038835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses 4048835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses 4058835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 480 # number of overall misses 4068835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 4767500 # number of ReadReq miss cycles 4078835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 4767500 # number of ReadReq miss cycles 4088835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 11508000 # number of WriteReq miss cycles 4098835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 11508000 # number of WriteReq miss cycles 4108835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 16275500 # number of demand (read+write) miss cycles 4118835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 16275500 # number of demand (read+write) miss cycles 4128835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 16275500 # number of overall miss cycles 4138835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 16275500 # number of overall miss cycles 4148835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1935 # number of ReadReq accesses(hits+misses) 4158835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 1935 # number of ReadReq accesses(hits+misses) 4168835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 4178835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 4188835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 2860 # number of demand (read+write) accesses 4198835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 2860 # number of demand (read+write) accesses 4208835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 2860 # number of overall (read+write) accesses 4218835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 2860 # number of overall (read+write) accesses 4228835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068734 # miss rate for ReadReq accesses 4238835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.375135 # miss rate for WriteReq accesses 4248835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.167832 # miss rate for demand accesses 4258835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.167832 # miss rate for overall accesses 4268835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35845.864662 # average ReadReq miss latency 4278835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33164.265130 # average WriteReq miss latency 4288835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 33907.291667 # average overall miss latency 4298835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 33907.291667 # average overall miss latency 4308428SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4318428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4328428SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4338428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4348428SN/Asystem.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 4358428SN/Asystem.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 4368428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 4378428SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 4388835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits 4398835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits 4408835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 296 # number of WriteReq MSHR hits 4418835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 296 # number of WriteReq MSHR hits 4428835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 338 # number of demand (read+write) MSHR hits 4438835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::total 338 # number of demand (read+write) MSHR hits 4448835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 338 # number of overall MSHR hits 4458835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::total 338 # number of overall MSHR hits 4468835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 4478835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 4488835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 4498835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 4508835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 4518835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 4528835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 4538835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses 4548835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3272000 # number of ReadReq MSHR miss cycles 4558835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 3272000 # number of ReadReq MSHR miss cycles 4568835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1836000 # number of WriteReq MSHR miss cycles 4578835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 1836000 # number of WriteReq MSHR miss cycles 4588835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 5108000 # number of demand (read+write) MSHR miss cycles 4598835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 5108000 # number of demand (read+write) MSHR miss cycles 4608835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 5108000 # number of overall MSHR miss cycles 4618835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 5108000 # number of overall MSHR miss cycles 4628835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047028 # mshr miss rate for ReadReq accesses 4638835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 4648835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.049650 # mshr miss rate for demand accesses 4658835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.049650 # mshr miss rate for overall accesses 4668835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35956.043956 # average ReadReq mshr miss latency 4678835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36000 # average WriteReq mshr miss latency 4688835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35971.830986 # average overall mshr miss latency 4698835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35971.830986 # average overall mshr miss latency 4708428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 4718428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 4728546SN/Asystem.cpu.l2cache.tagsinuse 221.521956 # Cycle average of tags in use 4738428SN/Asystem.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 4748464SN/Asystem.cpu.l2cache.sampled_refs 424 # Sample count of references to valid blocks. 4758464SN/Asystem.cpu.l2cache.avg_refs 0.007075 # Average number of references to valid blocks. 4768428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4778835SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 163.434563 # Average occupied blocks per requestor 4788835SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 58.087393 # Average occupied blocks per requestor 4798835SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004988 # Average percentage of cache occupancy 4808835SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001773 # Average percentage of cache occupancy 4818835SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::total 0.006760 # Average percentage of cache occupancy 4828835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 4838835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 4848835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 4858835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 4868835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 4878835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 3 # number of overall hits 4888835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 333 # number of ReadReq misses 4898835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses 4908835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 424 # number of ReadReq misses 4918835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 4928835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 4938835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 333 # number of demand (read+write) misses 4948835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 4958835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 475 # number of demand (read+write) misses 4968835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 333 # number of overall misses 4978835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 4988835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 475 # number of overall misses 4998835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11418500 # number of ReadReq miss cycles 5008835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 3142500 # number of ReadReq miss cycles 5018835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 14561000 # number of ReadReq miss cycles 5028835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1760500 # number of ReadExReq miss cycles 5038835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1760500 # number of ReadExReq miss cycles 5048835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 11418500 # number of demand (read+write) miss cycles 5058835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 4903000 # number of demand (read+write) miss cycles 5068835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 16321500 # number of demand (read+write) miss cycles 5078835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 11418500 # number of overall miss cycles 5088835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 4903000 # number of overall miss cycles 5098835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 16321500 # number of overall miss cycles 5108835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 336 # number of ReadReq accesses(hits+misses) 5118835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 5128835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 427 # number of ReadReq accesses(hits+misses) 5138835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 5148835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 5158835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 336 # number of demand (read+write) accesses 5168835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 5178835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 478 # number of demand (read+write) accesses 5188835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 336 # number of overall (read+write) accesses 5198835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses 5208835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 478 # number of overall (read+write) accesses 5218835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991071 # miss rate for ReadReq accesses 5228835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 5238835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 5248835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.991071 # miss rate for demand accesses 5258835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 5268835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.991071 # miss rate for overall accesses 5278835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 5288835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.789790 # average ReadReq miss latency 5298835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34532.967033 # average ReadReq miss latency 5308835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34519.607843 # average ReadExReq miss latency 5318835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34289.789790 # average overall miss latency 5328835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 34528.169014 # average overall miss latency 5338835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.789790 # average overall miss latency 5348835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 34528.169014 # average overall miss latency 5358428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5368428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5378428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 5388428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 5398428SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 5408428SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 5418428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 5428428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 5438835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses 5448835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 5458835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses 5468835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 5478835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 5488835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses 5498835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 5508835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 475 # number of demand (read+write) MSHR misses 5518835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses 5528835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 5538835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 475 # number of overall MSHR misses 5548835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10340500 # number of ReadReq MSHR miss cycles 5558835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2857500 # number of ReadReq MSHR miss cycles 5568835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 13198000 # number of ReadReq MSHR miss cycles 5578835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1598500 # number of ReadExReq MSHR miss cycles 5588835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1598500 # number of ReadExReq MSHR miss cycles 5598835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10340500 # number of demand (read+write) MSHR miss cycles 5608835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4456000 # number of demand (read+write) MSHR miss cycles 5618835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 14796500 # number of demand (read+write) MSHR miss cycles 5628835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10340500 # number of overall MSHR miss cycles 5638835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4456000 # number of overall MSHR miss cycles 5648835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 14796500 # number of overall MSHR miss cycles 5658835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for ReadReq accesses 5668835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 5678835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 5688835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for demand accesses 5698835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 5708835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for overall accesses 5718835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 5728835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.552553 # average ReadReq mshr miss latency 5738835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31401.098901 # average ReadReq mshr miss latency 5748835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31343.137255 # average ReadExReq mshr miss latency 5758835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency 5768835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency 5778835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency 5788835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency 5798428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 5806039SN/A 5816039SN/A---------- End Simulation Statistics ---------- 582